Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This is a response to the amendment filed on 01/26/26. The applicant argument regarding Tan et al. is not persuasive; therefore, all the rejections based on Tan et al. is retained and repeated for the following reasons.
Summary of claims
Claims 1-25 are pending.
Claims 1-25 are rejected.
Oath/Declaration
The oath/declaration filed on June 08th, 2022 is acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-25 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tan et al. (US Pub. 2016/0162783).
As to claims 1 the prior art teaches a computing system comprising:
a network controller (see fig 1); a processor coupled to the network controller (see fig 1-2);
and a memory coupled to the processor, the memory including a set of instructions, which when executed by the processor, cause the processor to: identify a plurality of functional blocks in a circuit, wherein each functional block includes a plurality of components (see fig 1-5 paragraph 0061-0070; especially, Tan et al. teach identify a plurality of functional blocks in a circuit, wherein each functional block includes a plurality of components as fig 1-5 paragraph 0062-065 and 0067-0069),
conduct one or more passes of a first optimization loop to determine candidate aspect ratios for the functional blocks based on size data associated with the components (see fig 3-6 paragraph 0079-0089; especially, Tan et al. teach conduct one or more passes of a first optimization loop to determine candidate aspect ratios for the functional blocks based on size data associated with the components as fig 3-6 paragraph 0080-0084 and 0086-0088),
and conduct, within the one or more passes of the first optimization loop, one or more passes of a second optimization loop to determine candidate floorplan data for the circuit based on the candidate aspect ratios (see fig 3-7 paragraph 0096-0105; especially, Tan et al. teach conduct, within the one or more passes of the first optimization loop, one or more passes of a second optimization loop to determine candidate floorplan data for the circuit based on the candidate aspect ratios as fig 3-7 paragraph 0097-0103).
As to claims 2, 8, 14 and 21, the prior art teaches wherein the second optimization loop is to include a simulated annealing optimization with respect to a B*-Tree representation of the candidate floorplan data (see fig 3-7 paragraph 0095-0103).
As to claims 3, 9, 15 and 22 the prior art teaches wherein the simulated annealing optimization is to include a plurality of random perturbation operations (see fig 3-8 paragraph 0088-0094).
As to claims 4, 10, 16 and 23 the prior art teaches wherein the instructions, when executed, further cause the processor to exit the second optimization loop in response to a second time constraint (see fig 3-7 paragraph 0095-0100).
As to claim 5, 11, 17 and 24 the prior art teaches wherein the first optimization loop is to include a Bayesian optimization update of a surrogate model of the circuit based on the candidate floorplan data (see fig 3-10 paragraph 0102-0110).
As to claims 6, 12, 18 and 28 the prior art teaches wherein the instructions, when executed, further cause the processor to:
exit the first optimization loop in response to a first time constraint (see fig 3-11 paragraph 0110-0115);
and output a floorplan associated with a smallest surface area (see fig 3-11 paragraph 0113-0118).
As to claims 7 the prior art teaches at least one computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to:
identify a plurality of functional blocks in a circuit, wherein each functional block includes a plurality of components (see fig 1-5 paragraph 0061-0070; especially, Tan et al. teach identify a plurality of functional blocks in a circuit, wherein each functional block includes a plurality of components as fig 1-5 paragraph 0062-065 and 0067-0069);
conduct one or more passes of a first optimization loop to determine candidate aspect ratios for the functional blocks based on size data associated with the components (see fig 3-6 paragraph 0079-0089; especially, Tan et al. teach conduct one or more passes of a first optimization loop to determine candidate aspect ratios for the functional blocks based on size data associated with the components as fig 3-6 paragraph 0080-0084 and 0086-0088);
and conduct, within the one or more passes of the first optimization loop, one or more passes of a second optimization loop to determine candidate floorplan data for the circuit based on the candidate aspect ratios (see fig 3-7 paragraph 0096-0105 especially, Tan et al. teach conduct, within the one or more passes of the first optimization loop, one or more passes of a second optimization loop to determine candidate floorplan data for the circuit based on the candidate aspect ratios as fig 3-7 paragraph 0097-0103).
As to claims 13 the prior art teaches a semiconductor apparatus comprising: one or more substrates; and logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to:
identify a plurality of functional blocks in a circuit, wherein each functional block includes a plurality of components (see fig 1-5 paragraph 0061-0070; especially, Tan et al. teach identify a plurality of functional blocks in a circuit, wherein each functional block includes a plurality of components as fig 1-5 paragraph 0062-065 and 0067-0069);
conduct one or more passes of a first optimization loop to determine candidate aspect ratios for the functional blocks based on size data associated with the components (see fig 3-7 paragraph 0064-0068 and 0088-0099; especially, Tan et al. teach conduct one or more passes of a first optimization loop to determine candidate aspect ratios for the functional blocks based on size data associated with the components as fig 3-6 paragraph 0080-0084 and 0086-0088));
and conduct, within the one or more passes of the first optimization loop, one or more passes of a second optimization loop to determine candidate floorplan data for the circuit based on the candidate aspect ratios (see fig 3-7 paragraph 0096-0105 especially, Tan et al. teach conduct, within the one or more passes of the first optimization loop, one or more passes of a second optimization loop to determine candidate floorplan data for the circuit based on the candidate aspect ratios as fig 3-7 paragraph 0097-0103).
As to claim 19 the prior art teaches wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.
As to claims 20 the prior art teaches a method comprising:
identifying a plurality of functional blocks in a circuit, wherein each functional block includes a plurality of components (see fig 1-5 paragraph 0061-0070);
conducting one or more passes of a first optimization loop to determine candidate aspect ratios for the functional blocks based on size data associated with the components (see fig 3-6 paragraph 0079-0089);
and conducting, within the one or more passes of the first optimization loop, one or more passes of a second optimization loop to determine candidate floorplan data for the circuit based on the candidate aspect ratios (see fig 3-7 paragraph 0096-0105).
Remarks
Applicant’s response and remarks filed on 01/26/26 have been carefully reviewed. Applicant’s arguments have been fully considered but they are not persuasive. Key argument and their response related to the claims are listed as below:
Applicant contends that Tan et al. do not describe “and a memory coupled to the processor, the memory including a set of instructions, which when executed by the processor, cause the processor to: identify a plurality of functional blocks in a circuit, wherein each functional block includes a plurality of components” probes as claimed, Examiner respectfully disagrees. The prior art (Tan et al US Pub. 2016/0162783) do teach and a memory coupled to the processor, the memory including a set of instructions, which when executed by the processor, cause the processor to: identify a plurality of functional blocks in a circuit, wherein each functional block includes a plurality of components (see fig 1-5 paragraph 0061-0070; especially, Tan et al. teach identify a plurality of functional blocks in a circuit, wherein each functional block includes a plurality of components as fig 1-5 paragraph 0062-065 and 0067-0069).
Applicant contends that Tan et al. do not describe “conduct one or more passes of a first optimization loop to determine candidate aspect ratios for the functional blocks based on size data associated with the components” probes as claimed, Examiner respectfully disagrees. The prior art (Tan et al. US Pub. 2016/0162783) do teach conduct one or more passes of a first optimization loop to determine candidate aspect ratios for the functional blocks based on size data associated with the components (see fig 3-6 paragraph 0079-0089; especially, Tan et al. teach conduct one or more passes of a first optimization loop to determine candidate aspect ratios for the functional blocks based on size data associated with the components as fig 3-6 paragraph 0080-0084 and 0086-0088).
Applicant contends that Tan et al. do not describe “conduct, within the one or more passes of the first optimization loop, one or more passes of a second optimization loop to determine candidate floorplan data for the circuit based on the candidate aspect ratios” probes as claimed, Examiner respectfully disagrees. The prior art (Tan et al. US Pub. 2016/0162783) do teach conduct, within the one or more passes of the first optimization loop, one or more passes of a second optimization loop to determine candidate floorplan data for the circuit based on the candidate aspect ratios (see fig 3-7 paragraph 0096-0105; especially, Tan et al. teach conduct, within the one or more passes of the first optimization loop, one or more passes of a second optimization loop to determine candidate floorplan data for the circuit based on the candidate aspect ratios as fig 3-7 paragraph 0097-0103).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
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/BINH C TAT/Primary Examiner, Art Unit 2851