DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 12, 2026 has been entered.
Response to Arguments
Applicant’s arguments, see Remarks, filed on April 10, 2026, with respect to the rejection(s) of claim(s) 1-28 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Gu (WO 2017/034641 A1).
In summary, the application is not placed in a condition for an allowance.
Claim Objections
Claims 1, 9, 15, and 24 are objected to because of the following informalities:
a. claims 1, 15, and 24 use Roman numerals within parenthesis to do an enumeration of limitations, which generally does not follow the over-all format of the other claim limitations.
b. claim 9, lines 10-11, does not follow the terminology of “plurality interconnects of the substrate,” as defined in parent claim 1 (see last wherein clause of claim 1), and instead used “plurality interconnects from the substrate.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 is amended to add the limitation of “wherein the at least one second bridge interconnect is configured to provide a second electrical path for ground” (line 5). This contradicts a pre-existing limitation that the said interconnect is configured to provide another electrical path for power (line 7). It is not clear whether there is another second bridge interconnect that is configured for power or whether the same second bridge interconnect that is configured for ground is also configured for power. For the purpose of compact prosecution, the examiner will treat this to mean the one third interconnect is configured to provide a second electrical path for ground.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 9-13, 15, 17-18, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable by Deshpande (US 2016/0343666 A1) in view of Nakagawa (US 2018/0374788 A1) and Gu (WO 2017/034641 A1).
Regarding claim 1, Deshpande teaches a package (100; Figs. 1-3D) comprising:
a substrate (110) comprising:
at least one dielectric layer (132); and
a plurality of interconnects (140) located at least partially in the at least one dielectric layer;
a bridge (150) located in a cavity (112) of the substrate, wherein the bridge comprises:
a bridge substrate (202; see Fig. 2F);
at least one first bridge dielectric layer (214) coupled to a first surface (Fig. 1: top surface of 202; Fig. 2F: bottom surface of 202; note: ¶ [0017] states 162 is the dashed line between the bond pads 156 of 1701 and 1702; Fig. 1 shows dashed line 118 on the top surface of 202 and Fig. 2F shows 162 and 156 at the bottom of 202 ) of the bridge substrate;
at least one first bridge interconnect (162, see Fig. 2F ) located in the at least one first bridge dielectric layer;
at least one second bridge dielectric layer (252&234) coupled to a second surface (Fig. 1: bottom surface of 202; Fig. 2F: top surface of 202) of the bridge substrate;
at least one second bridge interconnect (254&158) located in the at least one second bridge dielectric layer; and
at least one bridge interconnect (160 & left 156, see Fig. 2F) that extends through the at least one first bridge dielectric layer and the bridge substrate (Fig. 2F shows 160 & left 156 extending through 214 and 202);
wherein the first bridge dielectric layer is located over the bridge substrate and over the second bridge dielectric layer (Fig. 2F, when viewed upside down, shows 214 on top of 202 and 252&234), and
wherein a side portion (Fig. 1: lower vertical sides of 150; Fig. 2F: vertical sides of 252&234) of the at least one second bridge dielectric layer of the bridge, does not directly touch a side portion (116) of the at least one dielectric layer of the substrate (Fig. 1 shows cavity 112 of substrate 110 completely surrounding the vertical sides of bridge 150);
wherein the bridge includes a front side (top side of 150) and a back side (bottom side of 150).
a first integrated device (1701) coupled to the substrate; and
a second integrated device (1702) coupled to the substrate.
Deshpande further teaches an electrical path (path formed by 136&124&158, see Fig. 1, ¶ [0015], [0017]) between the bridge and the substrate that enters the bridge from the substrate through the back side (bottom side of 150) of the bridge (see ¶ [0017]) and/or exit the back side of the bridge. However, Deshpande does not teach the package wherein any electrical path between the bridge and the substrate does not enter the bridge from the substrate through the back side of the bridge and does not exit the bridge to the substrate through the back side of the bridge.
Nakagawa, in the same field of invention, teaches a package (PKG, see Figs. 1 & 5) wherein any electrical path between the bridge (40) and the substrate (10) does not enter the bridge from the substrate through the back side (40b) of the bridge and does not exit the bridge to the substrate through the back side of the bridge (¶ [0084]: “In the example shown in FIG. 1, the wiring path Lvg2 of the interposer 40 is connected to the wiring substrate 10 via the semiconductor component 20 and is not directly connected to the wiring substrate 10. In this case, a terminal does not need to be provided on a lower surface 40b side of the interposer 40”).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Nakagawa into the device of Deshpande to configure the any electrical path between the bridge and the substrate to not enter the bridge from the substrate through the back side of the bridge and not exit the bridge to the substrate through the back side of the bridge. The ordinary artisan would have been motivated to modify Deshpande in the manner set forth above for at least the purpose of re-arranging parts of the package to suit to the design choice of the skilled artisan (Nakagawa ¶ [0084]). The ordinary artisan further notes that Nakagawa, in another embodiment (Fig. 18), teaches the same inventive concept as that of Deshpande, i.e., an electrical path (using 47 & 54 & 48) between the bridge (40) and the substrate (10) is made to enter/exit through the back side (40b) of the bridge (see also Nakagawa ¶ [0199]) and hence the ordinary skill artisan notes that these two embodiments are equivalent modifications of the other.
See also MPEP § 2144.04 (VI) (C). In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
However, Deshpande in view of Nakagawa does not teach the package wherein an electrical path between the first integrated device and the second integrated device includes (i) one or more interconnects from the plurality of interconnects of the substrate,(ii) the bridge and (iii) one or more other interconnects from the plurality of interconnects of the substrate.
Gu, in the same field of invention, teaches a package (2, Fig. 2), wherein an electrical path between the first integrated device (202) and the second integrated device (204) includes (i) one or more interconnects (266) from the plurality of interconnects (262, 266, 264, 268) of the substrate (201),(ii) the bridge (210) and (iii) one or more other interconnects (268) from the plurality of interconnects of the substrate (see ¶ [0044] for details ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Gu into the device of Deshpande in view of Nakagawa to change the configuration of the cavity of the substrate (note: Gu’s substrate 201 has TSVs 266 and 268 under bridge 210) such that an electrical path is created between the first integrated device and the second integrated device using an interconnect of the substrate, the bridge, and another interconnect of the substrate. The ordinary artisan would have been motivated to modify Deshpande in view of Nakagawa in the manner set forth above for at least the purpose of shortening the path of the power/ground, thereby reducing the cost of manufacturing the package (Gu ¶ [0045] ).
Regarding claim 2, the package of claim 1,
wherein the at least one first bridge interconnect is configured to provide a first electrical path (118, see Fig. 1 and ¶ [0017]) for input /output (I/O) signals (¶ [0017]: signal line extends between 1701 and 1702 using 162), and
wherein the at least one second bridge interconnect is configured to provide a second electrical path (Fig. 1: path formed by 136&124&184&160&156&182&174) for power (¶ [0017]: “the through-bridge conductive vias 160 are electrically coupled to deliver power to the microelectronic devices 1701, 1702”; Fig. 2F shows 160 coupled to 254&158; hence 254&158 provide a path for power).
Regarding claim 9, the package of claim 1,
wherein the front side of the bridge includes the at least one first bridge interconnect (Deshpande Fig. 2F shows first bridge interconnect 162 and contact 156 found on the top side of 150; note that Fig. 2F is the upside-down representation of 150 in Fig.1, wherein contact 156 is shown on the top side of 150),
wherein the front side of the bridge faces in the direction of the first integrated device and the second integrated device (Fig. 2F shows the top side faces 1701 and 1702),
wherein the back side of the bridge includes the at least one second bridge interconnect (Fig. 2Fshows second bridge interconnect 252&234 and contact 158 on the back side of 150; note that Fig. 2F is the upside-down representation of 150 in Fig. 1, wherein contact 158 is on the bottom side of 150),
wherein there is no direct contact between (i) the at least one second bridge interconnect located in the backside of the bridge and (ii) an interconnect (11 and/or wiring within L1-L8, see Nakagawa Fig. 4) from the plurality interconnects from the substrate (Nakagawa Figs. 1, 4, & 5 shows no direct contact between the bottoms side of bridge 40 and the 11 and/or wiring in L1-L8; hence, Deshpande in view of Nakagawa teaches no interconnect between the second bridge interconnect and an interconnect of the substrate)
where the at least one second bridge interconnect located in the back side of the bridge does not touch any solder interconnect (BP1, BP6, BP4, BP7, BP8, see Nakagawa Fig. 1) that touches an interconnect from the plurality interconnects from the substrate, and
wherein the first integrated device is configured to be electrically coupled to the bridge (Deshpande ¶ [0017], ¶ [0023]).
Regarding claim 10, the package of claim 1,
wherein the first integrated device (20, see Nakagawa Fig. 1) is configured to be electrically coupled to the second integrated device (30; see also ¶ [0081]) through the substrate (10 through paths Lsg1, Lvd1, Lvg1, Lvg3, Lvd2) and the bridge (40; through paths Lsg2 and Lvg2;), and
wherein any electrical path between the bridge and the substrate, does not enter the bridge from the substrate through the back side of the bridge and does not exit the bridge to the substrate through the back side of the bridge (Fig. 5 shows bridge 40 not having any back-side terminals) means that all electrical paths between the bridge and the substrate, enter and exit the bridge through the front side of the bridge (see Nakagawa ¶ [0084]).
Regarding claim 11, the package of claim 10, wherein an input and/or output signal (VG1, see Nakagawa Fig. 1) is configured to travel between the first integrated device and the second integrated device through an electrical path that includes interconnects from the substrate (Lvg1) and the bridge interconnects (Lvg2) from the bridge (see Nakagawa Fig. 1 and ¶ [0081]).
Regarding claim 12, the package of claim 1, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet (Deshpande ¶ [0014]: “may be any appropriate microelectronic devices, such as microelectronic dice, including, but not limited to a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit device, and the like”; as defined in Applicant Par. [0062], a chiplet is an integrated circuit device that performs specific functions).
Regarding claim 13, the package of claim 1,
wherein the at least one first bridge interconnect includes a first thickness (vertical thickness of 162 , see Deshpande Fig. 2F)
wherein the at least one second bridge interconnect has a second thickness (vertical thickness of 254&158), and
wherein the second thickness is greater than the first thickness (as shown in Fig. 2F, the vertical thickness of 254&158 is greater than the vertical thickness of 162).
Regarding claim 15, Deshpande teaches a device (100; Figs. 1-3D) comprising:
a package (¶ [0002], ¶ [0012]) comprising:
a substrate (110) comprising:
at least one dielectric layer (132); and
a plurality of interconnects (140) located at least partially in the at least one dielectric layer;
a bridge (150) located in a cavity (112) of the substrate, wherein the bridge comprises:
a bridge substrate (202, see Fig. 2F);
at least one first bridge dielectric layer (214) coupled to a first surface (Fig. 1: top surface of 202; Fig. 2F: bottom surface of 202; note: ¶ 0017 states 162 is the dashed line between the bond pads 156 of 1701 and 1702; Fig. 1 shows dashed line 118 on the top surface of 202 and Fig. 2F shows 162 and 156 at the bottom of 202 ) of the bridge substrate;
at least one first bridge interconnect (162, see Fig. 2F ) located in the at least one first bridge dielectric layer, wherein the at least one first bridge interconnect is configured to provide a first electrical path (118, see Fig. 1 and ¶ [0017]) for input /output (I/O) signals (¶ [0017]: signal line extends between 1701 and 1702 using 162);
at least one second bridge dielectric layer (252&234) coupled to a second surface (Fig. 1: bottom surface of 202; Fig. 2F: top surface of 202) of the bridge substrate;
at least one second bridge interconnect (254&158; Fig. 2F) located in the at least one second bridge dielectric layer, wherein the at least one second bridge interconnect is configured to provide a second electrical path (Fig 1: path formed by 136&124&184&160&156&182&174) for power (¶ [0017]: “through-bridge conductive vias 160 are electrically coupled to deliver power”); and
at least one bridge interconnect (160 & left 156, see Fig. 2F) that extends through the at least one first bridge dielectric layer and the bridge substrate (Fig. 2F shows 160 & left 156 extending through 214 and 202);
wherein the first bridge dielectric layer is located over the bridge substrate and over the second bridge dielectric layer (Fig. 2F, when viewed upside down, shows 214 on top of 202 and 252&234), and
wherein a side portion (Fig. 1: lower vertical sides of 150; Fig. 2F: vertical sides of 252&234) of the at least one second bridge dielectric layer of the bridge, does not directly touch a side portion (116) of the at least one dielectric layer of the substrate (Fig. 1 shows cavity 112 of substrate 110 completely surrounding the vertical sides of bridge 150);
wherein the bridge includes a front side (top side of 150) and back side (bottom side of 150), and
a first integrated device (1701) coupled to the substrate; and
a second integrated device (1702) coupled to the substrate.
Deshpande further teaches an electrical path (path formed by 136&124&158, see Fig. 1, ¶ [0015], [0017]) between the bridge and the substrate enters the bridge from the substrate through the back side (bottom side of 150) of the bridge and exits the bridge through the front side of the bridge (see ¶ [0017]). However, Deshpande does not teach the device wherein any electrical path between the bridge and the substrate, enters and exits through the front side of the bridge.
Nakagawa, in the same field of invention, teaches a package (Fig. 5) wherein any electrical path (Lsg2 and/or Lvg2, see Fig. 1) between the bridge (40) and the substrate (10) enters and exits through the front side of the bridge (Fig. 5 shows terminals 53 provided on the top side of 40 but no terminals at the bottom; also ¶ [0084]: “In the example shown in FIG. 1, the wiring path Lvg2 of the interposer 40 is connected to the wiring substrate 10 via the semiconductor component 20 and is not directly connected to the wiring substrate 10. In this case, a terminal does not need to be provided on a lower surface 40b side of the interposer 40”).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Nakagawa into the device of Deshpande to configure the any electrical path between the bridge and the substrate to enter and exit the bridge through the front side of the bridge. The ordinary artisan would have been motivated to modify Deshpande in the manner set forth above for at least the purpose of re-arranging parts of the package to suit to the design choice of the skilled artisan (Nakagawa ¶ [0084]). The ordinary artisan further notes that Nakagawa, in another embodiment (Fig. 18), teaches the same inventive concept as that of Deshpande, i.e., an electrical path (using 47 & 54 & 48) between the bridge (40) and the substrate (10) is made to enter through the back side (40b) of the bridge and exit through the front side of the bridge (see also Nakagawa ¶ [0199]) and hence the ordinary skill artisan notes that these two embodiments are equivalent modifications of the other.
See also MPEP § 2144.04 (VI) (C). In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
However, Deshpande in view of Nakagawa does not teach the package wherein an electrical path between the first integrated device and the second integrated device includes (i) one or more interconnects from the plurality of interconnects of the substrate,(ii) the bridge and (iii) one or more other interconnects from the plurality of interconnects of the substrate.
Gu, in the same field of invention, teaches a package (2, Fig. 2), wherein an electrical path between the first integrated device (202) and the second integrated device (204) includes (i) one or more interconnects (266) from the plurality of interconnects (262, 266, 264, 268) of the substrate (201),(ii) the bridge (210) and (iii) one or more other interconnects (268) from the plurality of interconnects of the substrate (see ¶ [0044] for details ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Gu into the device of Deshpande in view of Nakagawa to change the configuration of the cavity of the substrate (note: Gu’s substrate 201 has TSVs 266 and 268 under bridge 210) such that an electrical path is created between the first integrated device and the second integrated device using an interconnect of the substrate, the bridge, and another interconnect of the substrate. The ordinary artisan would have been motivated to modify Deshpande in view of Nakagawa in the manner set forth above for at least the purpose of shortening the path of the power/ground, thereby reducing the cost of manufacturing the package (Gu ¶ [0045] ).
Regarding claim 17, the device of claim 15, wherein the input and/or output (I/O) signals are configured to enter through the front side of the bridge and exit through the front side of the bridge (Deshpande Fig. 2A: ¶ [0017]: signal line extends between 1701 and 1702 using 162; illustrated as dashed line 118 in Fig. 1)).
Regarding claim 18, the device of claim 15, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet (Deshpande ¶ [0014]: “may be any appropriate microelectronic devices, such as microelectronic dice, including, but not limited to a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit device, and the like”; as defined in Applicant [0062], a chiplet is an integrated circuit device that performs specific functions).
Regarding claim 23, the device of claim 15, wherein the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (Deshpande ¶ [0030], ¶ [0034]).
Regarding claim 24, Deshpande teaches a method for fabricating a package (100; see Figs. 1-3D; ¶ 0002, ¶ 0012), comprising:
providing a substrate (110) comprising:
at least one dielectric layer (132); and
a plurality of interconnects (140) located at least partially in the at least one dielectric layer;
placing a bridge (150) in the substrate, wherein the bridge comprises:
a bridge substrate (202, see Fig. 2F);
at least one first bridge dielectric layer (214) coupled to a first surface (Fig. 1: top surface of 202; Fig. 2F: bottom surface of 202; note: ¶ 0017 states 162 is the dashed line between the bond pads 156 of 1701 and 1702; Fig. 1 shows dashed line 118 on the top surface of 202 and Fig. 2F shows 162 and 156 at the bottom of 202 ) of the bridge substrate;
at least one first bridge interconnect (162, see Fig. 2F ) located in the at least one first bridge dielectric layer, wherein the at least one first bridge interconnect is configured to provide a first electrical path (118, see Fig. 1 and ¶ [0017]) for input /output (I/O) signals (¶ [0017]: signal line extends between 1701 and 1702 using 162);
at least one second bridge dielectric layer (252&234) coupled to a second surface (Fig. 1: bottom surface of 202; Fig. 2F: top surface of 202) of the bridge substrate;
at least one second bridge interconnect (254&158) located in the at least one second bridge dielectric layer, wherein the at least one second bridge interconnect is configured to provide a second electrical path (Fig 1: path formed by 136&124&184&160&156&182&174) for power (¶ [0017]: “through-bridge conductive vias 160 are electrically coupled to deliver power”); and
at least one bridge interconnect (160 & left 156, see Fig. 2F) that extends through the at least one first bridge dielectric layer and the bridge substrate (Fig. 2F shows 160 & left 156 extending through 214 and 202);
wherein the first bridge dielectric layer is located over the bridge substrate and over the second bridge dielectric layer (Fig. 2F, when viewed upside down, shows 214 on top of 202 and 252&234), and
wherein a side portion (Fig. 1: lower vertical sides of 150; Fig. 2F: vertical sides of 252&234) of the at least one second bridge dielectric layer of the bridge, does not directly touch a side portion (116) of the at least one dielectric layer of the substrate (Fig. 1 shows cavity 112 of substrate 110 completely surrounding the vertical sides of bridge 150);
wherein the bridge includes a front side (top side of 150) and back side (bottom side of 150); and
coupling a first integrated device (1701) to the substrate; and
coupling a second integrated device (1702) to the substrate.
Deshpande further teaches an electrical path (path formed by 136&124&158, see Fig. 1, ¶ [0015], [0017]) between the bridge and the substrate enters the bridge from the substrate through the back side (bottom side of 150) of the bridge and exits the bridge through the front side of the bridge (see ¶ [0017]). However, Deshpande does not teach the device wherein any electrical path between the bridge and the substrate, enters and exits through the front side of the bridge.
Nakagawa, in the same field of invention, teaches a package (Fig. 5) wherein any electrical path (Lsg2 and/or Lvg2, see Fig. 1) between the bridge (40) and the substrate (10) enters and exits through the front side of the bridge (Fig. 5 shows terminals 53 provided on the top side of 40 but no terminals at the bottom side 40b; also ¶ [0084]: “In the example shown in FIG. 1, the wiring path Lvg2 of the interposer 40 is connected to the wiring substrate 10 via the semiconductor component 20 and is not directly connected to the wiring substrate 10. In this case, a terminal does not need to be provided on a lower surface 40b side of the interposer 40”).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Nakagawa into the device of Deshpande to configure the any electrical path between the bridge and the substrate to enter and exit the bridge through the front side of the bridge. The ordinary artisan would have been motivated to modify Deshpande in the manner set forth above for at least the purpose of re-arranging parts of the package to suit to the design choice of the skilled artisan (¶ [0084]). The ordinary artisan further notes that Nakagawa, in another embodiment (Fig. 18), teaches the same inventive concept as that of Deshpande, i.e., an electrical path (using 47 & 54 & 48) between the bridge (40) and the substrate (10) is made to enter through the back side (40b) of the bridge and exit through the front side of the bridge (see also Nakagawa ¶ [0199]) and hence the ordinary skill artisan notes that these two embodiments are equivalent modifications of the other.
See also MPEP § 2144.04 (VI) (C). In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
However, Deshpande in view of Nakagawa does not teach the package wherein an electrical path between the first integrated device and the second integrated device includes (i) one or more interconnects from the plurality of interconnects of the substrate,(ii) the bridge and (iii) one or more other interconnects from the plurality of interconnects of the substrate.
Gu, in the same field of invention, teaches a package (2, Fig. 2), wherein an electrical path between the first integrated device (202) and the second integrated device (204) includes (i) one or more interconnects (266) from the plurality of interconnects (262, 266, 264, 268) of the substrate (201),(ii) the bridge (210) and (iii) one or more other interconnects (268) from the plurality of interconnects of the substrate (see ¶ [0044] for details ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Gu into the device of Deshpande in view of Nakagawa to change the configuration of the cavity of the substrate (note: Gu’s substrate 201 has TSVs 266 and 268 under bridge 210) such that an electrical path is created between the first integrated device and the second integrated device using an interconnect of the substrate, the bridge, and another interconnect of the substrate. The ordinary artisan would have been motivated to modify Deshpande in view of Nakagawa in the manner set forth above for at least the purpose of shortening the path of the power/ground, thereby reducing the cost of manufacturing the package (Gu ¶ [0045] ).
Claims 3-4 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Deshpande (US 2016/0343666 A1) in view of Nakagawa (US 2018/0374788 A1) and Gu (WO 2017/034641 A1) as applied to claims 1, 15, and 24 above, and further in view of Kang (US 2022/0045008 A1).
Regarding claim 3, Deshpande et al. teach the package of claim 1, and further teach:
wherein the at least one first bridge interconnect is configured to provide a first electrical path (118, see Deshpande Fig. 1 and ¶ [0017]) for input /output (I/O) signals (¶ [0017]: signal line extends between 1701 and 1702 using 162), and
wherein the at least one second bridge interconnect is configured to provide a second electrical path (Fig. 1: path formed by the right side elements of 136&124&184&160&156&182&174) for power (¶ [0017]: “the through-bridge conductive vias 160 are electrically coupled to deliver power to the microelectronic devices 1701, 1702”; Fig. 2F shows 160 coupled to 254&158; hence 254&158 provide a path for power).
However, Deshpande et al. do not teach the package further comprising at least one third bridge interconnect located in the at least one first bridge dielectric layer,
wherein the at least one third bridge dielectric interconnect is configured to provide another electrical path for power, and
wherein the at least one second bridge interconnect is configured to provide a second electrical path for ground.
Kang, in the same field of invention, teaches a package (Figs. 1-2) comprising at least one third bridge interconnect (124c in Fig. 2) located in the at least one first bridge dielectric layer (123),
wherein the at least one third bridge dielectric interconnect is configured to provide another electrical path for power (Kang ¶ [0037]: "the first semiconductor chip 200 and the second semiconductor chip 300 may receive a power or ground signal that is externally applied through the lower buildup portion 140, the vias 126, and the third upper chip pads 124c"), and
wherein the at least one second bridge interconnect (127; 127 is an interconnect located at the bottom of bridge 120) is configured to provide a second electrical path (150 & 144 & 127 & 126 & 124 & 134) for either power or ground (Kang ¶ [0037]: "the first semiconductor chip 200 and the second semiconductor chip 300 may receive a power or ground signal that is externally applied through the lower buildup portion 140, the vias 126, and the third upper chip pads 124c").
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kang into the device of Deshpande et al. to add at least one third bridge interconnect located in the at least one first bridge dielectric layer, wherein the at least one third bridge dielectric interconnect is configured to provide another electrical path for power and configure the at least one second bridge interconnect to provide a second electrical path for ground. The ordinary artisan would have been motivated to modify Deshpande et al. in the manner set forth above for at least the purpose of providing grounding as part of the power delivery path (Kang ¶ [0030], ¶ [0037]), with the ordinary artisan noting that it is known in the art that providing a power supply means supplying voltage and that a voltage is a potential difference between two points. Hence power supplied to devices need a power path as the first reference point of the voltage and a ground path as the second reference point of the voltage to constitute the voltage potential difference. See MPEP § 2144.02 and § 2144 (I).
Regarding claim 4, Deshpande et al. teach the package of claim 1, and further teach,
wherein the at least one first bridge interconnect is configured to provide a first electrical path (118, see Deshpande Fig. 1 and ¶ [0017]) for input /output (I/O) signals (¶ [0017]: signal line extends between 1701 and 1702 using 162),
wherein the at least one second bridge interconnect is configured to provide another electrical path (Deshpande Fig. 1: path formed by left side elements of 136&124&184&160&156&182&174) for power (Deshpande ¶ [0017]: “the through-bridge conductive vias 160 are electrically coupled to deliver power to the microelectronic devices 1701, 1702”; Fig. 2F shows 160 coupled to 254&158; hence 254&158 provide a path for power).
However, Deshpande et al. do not teach the package further comprising at least one third bridge interconnect located in the at least one second bridge dielectric layer,
wherein the at least one second bridge interconnect is configured to provide a second electrical path for ground.
Kang, in the same field of invention, teaches a package (Figs. 1-2) comprising at least one third bridge interconnect (128&127; Fig. 2) located in the at least one second bridge dielectric layer (113),
wherein the at least one second bridge interconnect (see 35 USC § 112(b) rejection above) is configured to provide a second electrical path for ground (Kang ¶ [0037]: "the first semiconductor chip 200 and the second semiconductor chip 300 may receive a power or ground signal that is externally applied through the lower buildup portion 140, the vias 126, and the third upper chip pads 124c").
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kang into the device of Deshpande et al. to add at least one third bridge interconnect located in the at least one second bridge dielectric layer, wherein the at least one third bridge dielectric interconnect is configured to provide another electrical path for ground. The ordinary artisan would have been motivated to modify Deshpande et al. in the manner set forth above for at least the purpose of providing grounding as part of the power delivery path (Kang ¶ [0030], ¶ [0037]), with the ordinary artisan noting that it is known in the art that providing a power supply means supplying voltage and that a voltage is a potential difference between two points. Hence power supplied to devices need a power path as the first reference point of the voltage and a ground path as the second reference point of the voltage to constitute the voltage potential difference. See MPEP § 2144.02 and § 2144 (I).
Regarding claim 16, Deshpande et al. teach the device of claim 15, and further teaches: wherein the first integrated device is configured to be electrically coupled to the second integrated device through the substrate and the bridge (¶ [0017], ¶ [0023]: using signal lines 162).
However, Deshpande et al. do not teach the package wherein the first integrated device is configured to be electrically coupled to the second integrated device through the substrate.
Kang, in the same field of invention, teaches a package (Figs. 1 & 2) wherein the first integrated device (200) is configured to be electrically coupled to the second integrated device (300) through the substrate (100; the substrate interconnects 115 & 116 & 117, see ¶ [0019], are connected to 134, see ¶ [0033], and then 134 is connected to chip terminals 230 & 330 of devices 200 & 300; also see ¶ [0035]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kang into the device of Deshpande et al. to configure a first integrated device to be electrically coupled to a second integrated device through a substrate. The ordinary artisan would have been motivated to modify Deshpande et al. in the manner set forth above for at least the purpose of reducing the connection length between the first integrated device and the second integrated device, and hence, improving the electrical characteristics of the package (Kang ¶ [0037]) and for the purpose of device miniaturization (Kang ¶ [0003]).
Claims 5-8, 19-22, and 25-28 are rejected under 35 U.S.C. 103 as being unpatentable over Deshpande (US 2016/0343666 A1) in view of Nakagawa (US 2018/0374788 A1) and Gu (WO 2017/034641 A1) as applied to claims 1, 15, and 24 above, and further in view of Ong (US 2022/0278084 A1).
Regarding claim 5, Deshpande et al. teach the package of claim 1 as stated above. However, Deshpande et al. do not teach the package further comprising a passive device coupled to the at least one second bridge interconnect.
Ong, in the same field of invention, teaches a package (101; Fig. 1A, ¶ [0019]) further comprising a passive device (116 or 118, see ¶ [0019], ¶ [0023]: both 116 & 118 are capacitors) coupled to the at least one second bridge interconnect (127, see ¶0022; element 110 is the bridge, see ¶0019, which is analogous to Deshpande 150; Fig. 1A shows 116 / 118 located on the bottom side of the bridge on the opposite side of the devices 10 & 20).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Ong into the package of Deshpande et al. to couple a passive device to at least one of a second bridge interconnect of a bridge. The ordinary artisan would have been motivated to modify Deshpande et al. in the manner set forth above for at least the purpose of providing decoupling capacitors to ensure proper power delivery as the demands may change proximate to the location of the passive devices (Ong ¶ [0016]) and to optimize the power integrity and device performance by lowering the network impedance (Ong ¶ [0017]), wherein power to the passive device is provided through the at least one second bridge interconnect (Deshpande ¶ [0017]: “through-bridge conductive vias 160 are electrically coupled to deliver power”; hence second bridge interconnect 254&158 are configured to provide power to the passive device ).
Regarding claim 6, the package of claim 5, further comprising an encapsulation layer (112; see Ong Fig. 1A and ¶ [0019]) that encapsulates the passive device.
Regarding claim 7, the package of claim 5,
wherein the front side of the bridge faces in the direction of the first integrated device and the second integrated device (Deshpande Fig. 1 shows the top side of 150 faces upwards in the direction of 1701 and 1702), and
wherein the passive device is coupled to the back side of the bridge (Ong Fig. 1A shows 116/118 coupled at the bottom surface of 110).
Regarding claim 8, the package of claim 7,
wherein the bridge is configured to provide at least one electrical path (Deshpande Fig. 1: path formed by 136&124&184&160&156) for power (Deshpande ¶ [0017]: “the through-bridge conductive vias 160 are electrically coupled to deliver power to the microelectronic devices 1701, 1702”; Fig. 2F shows 160 coupled to 254&158; hence 254&158 of bridge 150 provide a path for power), and
wherein the power that travels through the bridge travels through the back side of the bridge (as previously noted through Deshpande ¶ [0017], power travels from the substrate through bottom side of 150 to devices 170).
Regarding claim 19, Deshpande et al teaches the device of claim 15, and further teaches at least one second bridge interconnect is configured for power (Deshpande ¶ [0017]: “through-bridge conductive vias 160 are electrically coupled to deliver power”). However Deshpande et al. do not teach the device further comprising a passive device coupled to the at least one second bridge interconnect, wherein power to the passive device is provided through the at least one second bridge interconnect.
Ong, in the same field of invention, teaches a package (101; see Fig. 1A and ¶ [0019]) further comprising a passive device (116 or 118, see ¶ [0019], ¶ [0023]: both 116 & 118 are capacitors) coupled to the at least one second bridge interconnect (127, see ¶ [0022]; element 110 is the bridge, see ¶ [0019], which is analogous to Deshpande 150; Fig. 1A shows 116 / 118 located on the bottom side of the bridge on the opposite side of the devices 10 & 20), wherein power to the passive device is provided through the at least one second bridge interconnect (Deshpande in view of Ong teaches this; see teachings of Deshpande above).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Ong into the package of Deshpande et al to couple a passive device to at least one of the second bridge interconnect of a bridge, wherein power to the passive device is provided through the at least one second bridge interconnect.
.The ordinary artisan would have been motivated to modify Deshpande et al in the manner set forth above for at least the purpose of providing decoupling capacitors to ensure proper power delivery as the demands may change proximate to the location of the passive devices (Ong ¶ [0016]) and to optimize the power integrity and device performance by lowering the network impedance (Ong ¶ [0017]).
Regarding claim 20, the device of claim 19, further comprising an encapsulation layer (112, see Ong Fig. 1A and ¶ [0019]) that encapsulates the passive device.
Regarding claim 21, the device of claim 19,
wherein the front side of the bridge faces in the direction of the first integrated device and second integrated device (Deshpande Fig. 1 shows the top side of 150 faces upwards in the direction of 1701 and 1702), and
wherein the passive device is coupled to the back side of the bridge (Ong Fig. 1A shows 116/118 at the back side of the bridge).
Regarding claim 22, the device of claim 21,
wherein the power that travels through the bridge travels through the back side of the bridge (as previously noted through Deshpande ¶ [0017], power travels from the substrate through bottom side of 150 to devices 170).
Regarding claim 25, Deshpande et al teaches the method of claim 24, but does not teach wherein the package comprises a passive device coupled to the at least one second bridge interconnect.
Ong, in the same field of invention, teaches a method wherein the package (101, see Fig. 1A, ¶ [0019]) comprises a passive device (116 or 118; see ¶ [0019], ¶ [0023]: both 116 & 118 are capacitors) coupled to the at least one second bridge interconnect (127, see ¶ [0022]; element 110 is the bridge, see ¶ [0019], which is analogous to Deshpande 150; Fig. 1A shows 116 / 118 located on the bottom side of the bridge on the opposite side of the devices 10 & 20).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Ong into the method of Deshpande et al to couple a passive device to at least one of the second bridge interconnect. The ordinary artisan would have been motivated to modify Deshpande et al in the manner set forth above for at least the purpose of providing decoupling capacitors to ensure proper power delivery as the demands may change proximate to the location of the passive devices (Ong ¶ [0016]), optimize the power integrity and device performance by lowering the network impedance (Ong ¶ [0017]).
Regarding claim 26, the method of claim 25, wherein the package comprises an encapsulation layer (112; see Ong Fig. 1A and ¶ [0019]) that encapsulates the passive device.
Regarding claim 27, the method of claim 25,
wherein the front side of the bridge faces in the direction of the first integrated device and the second integrated device (Deshpande Fig. 1 shows the top side of 150 faces upwards in the direction of 1701 and 1702), and
wherein the passive device is coupled to the back side of the bridge (Ong Fig. 1A shows 116/118 coupled to the back side of 110).
Regarding claim 28, the method of 27,
wherein the bridge is configured to provide at least one electrical path (Deshpande Fig. 1: path formed by 136&124&184&160&156) for power (Deshpande ¶ [0017]: “the through-bridge conductive vias 160 are electrically coupled to deliver power to the microelectronic devices 1701, 1702”; Fig. 2F shows 160 coupled to 254&158; hence 254&158 of bridge 150 provide a path for power), and
wherein the power that travels through the bridge travels through the back side of the bridge (as previously noted through Deshpande ¶ [0017], power travels from the substrate through bottom side of 150 to devices 170).
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Deshpande (US 2016/0343666 A1) in view of Nakagawa (US 2018/0374788 A1) and Gu (WO 2017/034641 A1) as applied to claims 13, and further in view of Mekonnen (US 2021/0296240 A1) and Kariyazaki (US 2016/0218083 A1).
Regarding claim 14, Deshpande et al. teach the package of claim 13, and further teaches the second bridge interconnect to be bond pads (¶ [0017]: 158 are bond pads). However, Deshpande et al. do not teach wherein the second thickness of the second bridge interconnect is in a second range of about 3-6 micrometers.
Mekonnen, in the same field of invention, teaches a conductive layer of a bridge (110, see Fig. 1) made of bond pads 150 with thickness between 5-6 micrometers (¶ [0012]). Hence, Mekonnen teaches a package wherein the second thickness of the second bridge interconnect is in a second range of about 3-6 micrometers.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Mekonnen into the device of Deshpande et al. to have a thickness of a second bridge interconnect to be in a range of about 3-6 micrometers. The ordinary artisan would have been motivated to modify Deshpande et al. in the manner set forth above for at least the purpose of subjecting the second bridge interconnect pads to a wafer thinning process in order to avoid subjecting the entire bridge to the wafer thinning process to avoid undesired effects such as delamination or warping (Mekonnen ¶ [0012]).
However, Deshpande et al. do not teach wherein the first thickness of the first bridge interconnect is in a first range of about 1-2 micrometers.
Kariyazaki, in the same field of invention, teaches a device (Fig. 6: PKG1) wherein the first thickness of a first bridge interconnect (22) is in a first range of about 1-2 micrometers ([0095]: 1 μm to 1.2 μm) as a natural result of a common motivation in the art to improving the signal transmission rate between the logic chip 30B (analogous to Kang 200) and the memory chip 30A (analogous to Kang 300) ( Par. [0092]-[0095]: "when the number of the transmission paths is increased using the interposer, the width of each of the wirings formed in the interposer becomes narrow and its thickness becomes thin").
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kariyazaki into the device of Deshpande et al. to have a thickness of at least one first bridge interconnect to be in a range of 1-2 micrometers. The ordinary artisan would have been motivated to modify Deshpande et al. in the manner set forth above for at least the purpose of improving the signal transmission rate between the logic chip (30B, see Kariyazaki Fig. 1) and the memory chip (30A) (Kariyazaki ¶ [0092] - ¶ [0095]).
Furthermore, optimization of ranges, such as the thickness of conductive layers, is not found to be inventive. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP § 2411.05 (II)(A).
Conclusion
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A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
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