DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 30 December 2025 has been entered. Applicant’s
amendments to the drawings have overcome the drawings objections previously set forth in the Non-Final Office Action filed 01 October 2025.
Specification
The abstract of the disclosure is objected to because it refers to purported merits of the invention. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-7, 9-10, 13-15, 17-18, 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over US 20200242474 A1 Lo et al. (hereinafter “Lo”) in view of Kaczmarski K, Wolant A. GPU R-Trie: Dictionary with ultra fast lookup. Concurrency Computat Pract Exper. 2019; 31:e5027. https://doi.org/10.1002/cpe.5027 (hereinafter “Kaczmarski”) in view of US 11783200 B2 Diamantopoulos et al. (hereinafter “Diamantopoulos”).
Regarding claim 1, Lo teaches a computing system comprising:
a network controller (Fig. 15, 1570, [0146]); and
a decompression pipeline (Fig. 15, 1530, [0147]) coupled to the network controller ([0143]), the decompression pipeline including:
first decoder hardware (Fig. 7, 760, [0108]; Fig. 8, 760, [0117]) to convert (Fig. 8, 840, [0118]; Fig. 14, 1430, [0136-0137]) variable length weights (Fig. 8, 830, [0117]) to fixed length keys (Fig. 8, output from 840, [0118], [0120] additionally compressed form of 830), wherein the variable length weights are non-uniform quantization values (Fig. 9, 920, [0124]; Fig. 10, 1020, [0125]; Fig. 11, 1120, [0126]; Fig. 12, 1220, [0127]; [0043], [0117]), and
second decoder hardware (Fig. 7, 780, [0112]) to convert (Fig. 14, 1450, [0138] dequantizing) the fixed length keys to bit values ([0112] uniform mantissa values, as described by example of original converting in first decoder hardware in Fig. 9, 910, [0124]; Fig. 10, 1010, [0125]; Fig. 11, 1110, [0126]; Fig. 12, 1210, [0127]).
Although Lo teaches processing activation values (Fig. 7, 720, [0106]) in the first and second decoder hardware, it appears they are silent with explicitly teaching these variable length values as weight values. It would have been obvious to one of ordinary skill in the art before the effective filing date to try to modify with weight values because in practicality there are only a finite number of possible values to optimize when performing inferences, the neural network weights and the activation values ([0030-0031]). Given the finite possibilities of ways to optimize inference via data manipulation, it would have been obvious to try weights in place of the activation values.
Lo is silent with explicitly teaching the decompression circuit as a pipeline and to teaching fixed length keys.
Kaczmarski teaches fixed length keys (Pg. 6, Fig. 4 description; Pg. 5, Section Tree nodes creation steps 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify with Kaczmarski’s dictionary for fixed length keys because they are in the claimed invention’s same field of endeavor of computer systems (Pg. 1, Sec. 1, Para. 1). It would have been obvious to one of ordinary skill in the art to implement the dictionary scheme as Kaczmarski’s scheme yields a
3
∙
10
9
lookup per second for 32-bit keys (Pg. 13, Sec. 4, Para. 1). A person of ordinary skill in the art would look to Kaczmarski’s scheme in order to utilize an efficient method for processing a large amount of data and yield the benefits purported by Kaczmarski.
Lo in view of Kaczmarski are silent with disclosing a pipeline.
Diamantopoulos teaches a pipeline (Fig. 16, 103 pipeline/dataflow structure; Col. 14, lines 40-57).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify with Diamantopoulos’ pipeline implementation because they are in the claimed invention’s same field of endeavor of neural network apparatuses (Col. 2, lines 7-28). It would have been obvious to one of ordinary skill in the art to implement a pipelined implementation as pipelining is a known technique in the art (Col. 13, lines 22-33). A person of ordinary skill in the art would look to Diamantopoulos’ implementation in order to optimize the Lo in view of Kaczmarski system’s performance by improved processing of parallel communications and of higher-level networks tasks (Col. 13, lines 22-33).
Regarding claim 2, the rejection of claim 1 is incorporated and in addition to the teachings of claim 1, Lo the computer system wherein:
the fixed length keys are compressed representations (Fig. 8, 840, [0118]; Fig. 14, 1430, [0136-0137]) of the variable length weights (Fig. 9, 920, [0124]; Fig. 10, 1020, [0125]; Fig. 11, 1120, [0126]; Fig. 12, 1220, [0127]; [0043], [0117]).
The modification using weights instead of activation values provided with respect to claim 1 equally applies.
Lo is silent with teaching fixed length keys.
Kaczmarski teaches fixed length keys (Pg. 5, Section Tree nodes creation steps 10; Pg. 6, Fig. 4 description).
The motivation to combine provided with respect to claim 1 equally applies.
Regarding claim 5, the rejection of claim 1 is incorporated and in addition to the teachings of claim 1, Lo the computer system wherein:
the bit values are bit accurate representations ([0112] uniform mantissa values, as described by example of original converting in first decoder hardware in Fig. 9, 910, [0124]; Fig. 10, 1010, [0125]; Fig. 11, 1110, [0126]; Fig. 12, 1210, [0127]) of the fixed length keys.
Lo is silent with teaching fixed length keys.
Kaczmarski teaches fixed length keys (Pg. 6, Fig. 4 description; Pg. 5, Section Tree nodes creation steps 10).
The motivation to combine provided with respect to claim 1 equally applies.
Regarding claim 6, the rejection of claim 1 is incorporated and in addition to the teachings of claim 1, Lo the computer system wherein:
the fixed length keys are converted (Fig. 14, 1450, [0138] dequantizing) to the bit values (Fig. 9, 920, [0124]; Fig. 10, 1020, [0125]; Fig. 11, 1120, [0126]; Fig. 12, 1220, [0127]; [0043], [0117]) based on one or more dictionaries.
Lo is silent with teaching fixed length keys and basing on one or more dictionaries.
Kaczmarski teaches fixed length keys (Pg. 6, Fig. 4 description; Pg. 5, Section Tree nodes creation steps 10) and basing on one or more dictionaries (Fig. 4, R-Trie; Pg. 2, 1.1; Pg. 3, 2.1).
The motivation to combine provided with respect to claim 1 equally applies.
Regarding claim 7, the rejection of claim 1 is incorporated and in addition to the teachings of claim 1, Lo the computer system further including:
one or more block random access memory (BRAM) banks (Fig. 7, 770, [0111] off-chip DRAM, network accessible RAM); and
a matrix vector multiplication unit wherein the second decoder hardware (Fig. 7, 780, [0112]) is to retrieve the fixed length keys from the one or more BRAM banks ([0112] decompressor 780 reads compressed activation value from 770) and send (Fig. 7, 780 dashed arrow output, [0112] output by dashed line) the bit values ([0112] uniform mantissa values, as described by example of original converting in first decoder hardware in Fig. 9, 910, [0124]; Fig. 10, 1010, [0125]; Fig. 11, 1110, [0126]; Fig. 12, 1210, [0127]) to the matrix vector multiplication unit.
Lo is silent with teaching fixed length keys, a matrix vector multiplication unit, and more than one BRAM bank.
Kaczmarski teaches fixed length keys (Pg. 6, Fig. 4 description; Pg. 5, Section Tree nodes creation steps 10).
The motivation to combine provided with respect to claim 1 equally applies. Lo in view of Kaczmarski are silent with disclosing a matrix vector multiplication unit and more than one BRAM bank.
Diamantopoulos teaches more than one BRAM bank (Fig. 4, 34; Col. 8, lines 1-7, 57-67, Col. 9, lines 1-4) and the matrix vector multiplication unit (Fig. 15, 90; Col. 14, lines 1-12).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify with Diamantopoulos’ BRAM bank and matrix vector multiplication unit features because they are in the claimed invention’s same field of endeavor of neural network apparatuses (Col. 2, lines 7-28). It would have been obvious to one of ordinary skill in the art to implement these features as using a BRAM presents advantageous benefits (Col. 11, lines 12-48) and a matrix vector multiplication unit which performs matrix-vector computations is a known feature in the art for neurons in neural networks (Col. 7, lines 18-31, 44-48). A person of ordinary skill in the art would look to Diamantopoulos’ matrix vector multiplication unit as it is a common feature in the art and making the modification would yield predictable results. Further, a person of ordinary skill in the art would modify with Diamantopoulos’ BRAM bank as it would enable the Lo in view of Kaczmarski system’s memory to be supported for parallel computations, thus improving computational speeds (Col. 11, lines 24-48).
Claims 9-10 and 13-15 are directed to an apparatus that recite similar limitations to claims 1-2 and 5-7. The claims 1-2 and 5-7 analysis equally applies, and claims 9-10 and 13-15 are similarly rejected.
Claims 17-18 and 21-23 are directed to a method that would be practiced by claims 1-2 and 5-7. The claims 1-2 and 5-7 analysis equally applies, and claims 17-18 and 21-23 are similarly rejected.
Claims 3, 8, 11, 16, 19, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Lo in view of Kaczmarski in view of Diamantopoulos in view of Patterson, David A., and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface (5th Edition). Morgan Kaufmann, 2013. (hereinafter “Patterson”).
Regarding claim 3, the rejection of claim 1 is incorporated and in addition to the teachings of claim 1, Lo the computer system further including:
a dynamic random access memory (DRAM) (Fig. 7, 710, [0111] SRAM, eDRAM, block RAM); and
one or more block random access memory (BRAM) banks (Fig. 7, 770, [0111] off-chip DRAM, network accessible RAM), wherein the first decoder hardware (Fig. 7, 760, [0108]; Fig. 8, 760, [0117]) is further to retrieve the variable length weights (Fig. 8, 830, [0117]) from the DRAM (Fig. 7, 710, [0111]; Fig. 7, value from 710 pulled to 724 and inputs to be quantized in 760 with respect to Fig. 8, 820, [0116] receive from local memory) and store the fixed length keys to the one or more BRAM banks (Fig. 14, [0137], (further) compressed activation value, [0120]).
The modification using weights instead of activation values provided with respect to claim 1 equally applies.
Lo is silent with teaching fixed length keys, a dynamic RAM, and more than one BRAM bank.
Kaczmarski teaches fixed length keys (Pg. 6, Fig. 4 description; Pg. 5, Section Tree nodes creation steps 10).
The motivation to combine provided with respect to claim 1 equally applies. Lo in view of Kaczmarski are silent with disclosing a dynamic RAM, and more than one BRAM bank.
Diamantopoulos teaches more than one BRAM bank (Fig. 4, 34; Col. 8, lines 1-7, 57-67, Col. 9, lines 1-4).
The motivation to combine provided with respect to claim 7 equally applies.
Patterson teaches a dynamic RAM (Pg. 378, Para. 1, DRAM; Pg. 379, DRAM Technology).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify with Patterson’s DRAM because they are in the claimed invention’s same field of endeavor of computing systems (Pg. 374, 5.1 Introduction, Para. 1-3). It would have been obvious to one of ordinary skill in the art to implement the DRAM in place of Lo’s random access memory because DRAM is a known feature in the art and a type of random access memory (Pg. 379, DRAM Technology Section, Para. 1-3). A person of ordinary skill in the art would look to Patterson’s DRAM as it is a common computing component in the art, in addition to being less costly than other types of random access memory, such as a SRAM (Pg. 378, 5.2 Memory Technologies, Para. 1), and doing so would yield predictable results.
Regarding claim 8, the rejection of claim 1 is incorporated and in addition to the teachings of claim 1, Lo the computer system wherein:
the second decoder hardware (Fig. 7, 780, [0112]) includes a plurality of fixed length decoders.
Lo is silent with teaching a plurality of fixed length decoders.
Kaczmarski teaches fixed length values (Pg. 6, Fig. 4 description; Pg. 5, Section Tree nodes creation steps 10).
The motivation to combine provided with respect to claim 1 equally applies.
Although Kaczmarski discloses the particular type of data used in the decoder, Lo in view of Kaczmarski are silent with disclosing a plurality of decoders.
Lo in view of Kaczmarski in view of Diamantopoulos are silent with disclosing a plurality of decoders.
Patterson teaches a plurality of decoders (Pg. B-9, Decoders section, Para. 1).
Patterson discloses the decoder except for a plurality of them.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to form a plurality of decoders, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify with Patterson’s decoders because they are in the claimed invention’s same field of endeavor of computing systems (Pg. B-4, B.2, Para. 1-2). It would have been obvious to one of ordinary skill in the art to implement the decoder because they are a known logic block in the art (Pg. B-9, Decoders section, Para. 1). A person of ordinary skill in the art would look to Patterson’s decoder as it is a common computing component in the art, even described a building block used for building larger components, to improve the decoding performance of the Lo in view of Kaczmarski in view of Diamantopoulos’ system as only one output is asserted per each input combination (Pg. B-9, Decoders section, Para. 1).
Claims 11 and 16 are directed to an apparatus that recite similar limitations to claims 3 and 8. The claims 3 and 8 analysis equally applies, and claims 11 and 16 are similarly rejected.
Claims 19 and 24 are directed to a method that would be practiced by claims 3 and 8. The claims 3 and 8 analysis equally applies, and claims 19 and 24 are similarly rejected.
Claims 4, 12, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lo in view of Kaczmarski in view of Diamantopoulos in view of Patterson in view of US 5576765 A Cheney et al. (hereinafter “Cheney”).
Regarding claim 4, the rejection of claim 3 is incorporated and in addition to the teachings of claim 3, Lo the computer system wherein:
the first decoder hardware (Fig. 7, 760, [0108]; Fig. 8, 760, [0117]) includes a first plurality of variable length decompression units (Fig. 7, “Additional Compression, Fig. 8, 840, [0118]) coupled ([0120]) to a first BRAM and a second plurality of decompression units coupled to a second BRAM.
Lo discloses the first variable length decompression unit except for a plurality of them.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to form a plurality of these units, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Lo is silent with disclosing the first decoder hardware including a first BRAM and a second plurality of decompression units coupled to a second BRAM.
Lo in view of Kaczmarski are silent with disclosing the first decoder hardware including a first BRAM and a second plurality of decompression units coupled to a second BRAM.
Diamantopoulos teaches a first and second BRAM (Fig. 4, 34; Col. 8, lines 1-7, 57-67, Col. 9, lines 1-4).
The motivation to combine provided with respect to claim 7 equally applies.
Lo in view of Kaczmarski in view of Diamantopoulos are silent with disclosing a second plurality of decompression units.
Lo in view of Kaczmarski in view of Diamantopoulos in view of Patterson are silent with disclosing a second plurality of decompression units.
Cheney discloses a second plurality of decompression units (Fig. 5, 311; Fig. 8, 311; Col. 7, lines 38-44, 55-65; Col. 12, lines 4-21).
Cheney discloses the second variable length decompression unit except for a plurality of them.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to form a plurality of these units, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify with Cheney’s decompression units because they are in the claimed invention’s same field of endeavor of computing systems (Col. 1, lines 5-18). It would have been obvious to one of ordinary skill in the art to implement the second decompression units because these units functionally perform variable length coding algorithm. The variable length coding algorithm codes so that only a small number of bits are needed in the most common case (Col. 2, lines 59-65), and generates symbols based on probability occurrences, so that higher probability occurrences are assigned shorter codewords and lower probability occurrences are assigned higher codewords (Col. 8, lines 1-22), thus providing an efficient coding method with the units. A person of ordinary skill in the art would recognize these benefits of the algorithm with the units and look to Cheney’s decompression unit to modify to improve the coding performance of the Lo in view of Kaczmarski in view of Diamantopoulos in view of Patterson’s system.
Claim 12 is directed to an apparatus that recite similar limitations to claim 4. The claims 4 analysis equally applies, and claim 12 is similarly rejected.
Claim 20 is directed to a method that would be practiced by claim 4. The claim 4 analysis equally applies, and claim 20 are similarly rejected.
Response to Arguments
Abstract. Applicant respectfully submits that there is no requirement that an abstract does not refer to merits. For example, there is nothing in 37 CFR 1.72 that makes this requirement. Applicant reminds the Office that whatever the MPEP "requires" the MPEP is not law and Applicant is free to not follow the MPEP and only follow the law and the USPTO is similarly required to follow the law (Remarks p. 1).
Examiner respectfully disagrees. The MPEP has provided guidelines for the preparation of abstracts, and it would ordinarily be preferable that the applicant make the necessary changes to the abstract to bring it into compliance with the guidelines.
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
35 USC 103. Applicant argues the following in substance:
Applicant asserts that, the combination does not at least describe "a decompression pipeline coupled to the network controller, the decompression pipeline including: first decoder hardware to convert variable length weights to fixed length keys, wherein the variable length weights are non-uniform quantization values." The Office Action cites Lo as the primary reference. As an initial observation, Applicant is unsure as to why the Office continually cites the compressor 760 for something that is to be in the "decompression pipeline." There is an actual decompressor 780 which would seem more relevant to decompressing as compression and decompression are definitively different operations (Remarks p. 6 ⁋ 1).
Examiner respectfully disagrees. Applicant claims a decompression pipeline including a first decoder hardware and a second decoder hardware. Lo is relied upon to disclose these claim elements, respectively, a computing environment 1530, a compressor 760, and a decompressor 780. For clarity of record, in Applicant’s specification [0024] the first decoder hardware “converts the Huffman compressed weights to fixed compressed representations of the true values”. In [0023], the second decoder hardware “converts the fixed length keys to bit values” and further in [0029] describes an example of the second decoder hardware “decompressing”. It is unclear how Applicant’s “observation” with respect to the claims, and in light of the specification, are invoking a claim interpretation that is more stringently limiting than what is presently recited.
Applicant asserts that, Lo does not describe variable length weights. For example, in the cited paragraph Lo always goes from 10-bit to 8-bit. While the format of the 8-bit value may differ it is always 8 bits. The Office Action appears to assert that it would be obvious "to try to modify with weight values," but Applicant has no idea what that is supposed to mean. First, there is not a finite number of possible values of sizes of weights. Second, the cited paragraph note that other types of sizes have been used in the past, but how that equates to anything variable in length is lost on Applicant. Rather, the Office is making a bald statement without any sort of technical rationale. If the Office is saying you replace weights with activation values, that is even more problematic as there is a zero percent chance a PHOSITA would consider those interchangeable and this is a fundamental misunderstanding of ML. Applicant believes that it may be necessary to discuss with examiner's SPE fundamentals of ML if this is what the Office believes a PHOSITA would actually do (Remarks p. 6 ⁋ 2).
Examiner respectfully disagrees. First, Lo teaches variable length weights (Fig. 8 , 830, [0117]) as represented in the second block floating-point format possessing a non-uniform 3-bit mantissa (which can represent 8 values) and can be converted to a lossy mantissa. Second, Lo teaches variable length weights are non-uniform quantization values (Fig. 9, 920, [0124]; Fig. 10, 1020, [0125]; Fig. 11, 1120, [0126]; Fig. 12, 1220, [0127]; [0043], [0117]) as non-uniform mantissas where in Fig. 9 the length of a 3-bit mantissa is mapped to a set of values in a non-uniform four-value lossy fashion, in Fig. 10 the length of a 3-bit mantissa is mapped to a set of values in an non-uniform three-value lossy fashion, in Fig. 11 the length of a 3-bit mantissa is mapped to a set of values in a non-uniform two-value lossy fashion, and in Fig. 12 the length of a 3-bit mantissa is mapped to a set of values in a non-uniform five-value lossy fashion.
As discussed in the Non-Final Office Action filed 10/01/2025, p. 4-5, Lo discloses these variable lengths as related to the activation values (
y
i
) and is silent with disclosing them as weights. Lo discloses NNs have been trained and deployed using single-precision floating-point formats used to represent activation values and weights. Lower precision formats can be utilized for inferences with minimal loss in accuracy. Thus, numbers represented in floating-point formats (16-bit, 32-bit, 64-bit, 80-bit) can be converted to quantized-precision format numbers to achieve this purported benefit. Lo explicitly states both NN weights and activation values can be represented in this new precision ([0030-0031]). Therefore, although Lo does not explicitly describe the variable length limitation as weights, it would have been obvious to try applying this conversion to weights given the finite practicality of numbers applicable to undergo this conversion (the choice between NN weights and activation values).
Applicant asserts that, with respect to fixed-length keys, yes, Kaczmarski describes the use of fixed length keys. However, finding "fixed length keys" in a search is no reason to combine. Moreover, simply being in the same field of endeavor has never been a legal rationale. MPEP 2143, however, provides several exemplary rationales. Moreover, Lo's compressor already produces a fixed length output and the output is not a key and there is no use for a key in Lo's system (Remarks p. 6 ⁋ 3).
Examiner notes the rationale provided in MPEP 2143 and further notes that the rationale utilized in this combination is (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results. Note that the list of rationales provided is not intended to be an all-inclusive list. Other rationales to support a conclusion of obviousness may be relied upon by Office personnel. See MPEP 2143(I).
Kaczmarski modifies Lo with its teachings of fixed length keys that are used in a specified data structure, a dictionary. Although Applicant claims fixed length keys, the claims do not recite a corresponding dictionary structure. Thus, the broadest reasonable interpretation of the fixed length keys limitation is given its plain meaning. See MPEP 2111.01. Therefore, the interpretation of this limitation, in light of the claims, is a way of limiting the data type of the values. The modification of Lo in view Kaczmarski incorporates the data type of fixed length keys and utilizing this specific data type for use in a particular dictionary scheme, by nature of incorporation, that yields improved lookup speeds for quicker data access.
Applicant asserts that, the combination does not at least describe "a decompression pipeline coupled to the network controller, the decompression pipeline including: ... second decoder hardware to convert the fixed length keys to bit values." For example, there are no keys in the combination. Moreover, again, what the Office cites out of Lo is an 8-bit value (Remarks p. 6 ⁋ 4).
Examiner respectfully disagrees. The combination of Lo in view of Kaczmarski in view of Diamantopoulos is relied upon to teach the entirety of the claim limitation cited in the above argument. “Keys” specifically is disclosed by the Kaczmarski and the motivation to combine is discussed in the response to Argument 3.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151