DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to amendments filed on December 12, 2025.
Claims 1-35 are pending.
Claims 1-10, 19, 28 and 34-35 have been amended.
Response to Amendment
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 10, 19 and 28 recites the limitation "without the optimizations" in lines 6, 5, 6 and 6 respectively. There is insufficient antecedent basis for this limitation in the claim. In the interest of compact prosecution, the Examiner subsequently interprets this limitation as reading “without optimizations based on access to the non-overlapping memory locations” for the purpose of further examination.
Claims 2-9, 11-18, 20-27 and 29-35 depend on the rejected claims and do not resolve the deficiencies and thus, are rejected for at least the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6, 8, 10, 16, 18-19, 25, 28 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Chou (US 2007/0226722) in view of Hikaru Takayashiki et al. (“Register Flush-free Runahead Execution for Modern Vector Processors, 2021).
With respect to Claim 1, Chou discloses:
circuitry to: (see Figure 1; memory includes compiler which is coupled to a processor through a bridge (circuitry), Paragraph 22)
precompile a plurality of versions of program code, (see Figure 2; compiler produces differently optimized version of executable code, Paragraph 28), wherein a first version of the plurality of versions is compiled (compiler 116 can generate different versions of executable code for either an entire program or for specific functions that are frequently executed, wherein each version is optimized (first version) in accordance with a different optimization criterion, Paragraph 31) to comprise code optimized (for example, a first code version is optimized for the condition of a light core utilization (code optimized a first way), Paragraph 40) and a second version of the plurality of versions is compiled to comprise code without the optimizations; (second code version is optimized for the condition of a heavy core utilization (code optimized without the first way (light core utilization) and in a second way (heavy core utilization)), Paragraph 40)
select the first version of the plurality of precompiled versions of program code based, at least in part, on a determination at runtime; (The processor subsequently selects a version of executable code to execute based on the evaluation result, wherein the selected version of the executable code (first version) is optimized for the runtime state of the processor and/or the processor type (determination), Paragraph 34; at runtime, the processor evaluates core utilization through the branch instruction. In one embodiment of the present invention, if the processor detects more than half of the available threads on the core are utilized, the second code version is executed. Otherwise, the first code version is executed (determination/selection at runtime), Paragraph 40)
and cause the first version of the plurality of precompiled versions of program code to be performed. (subsequently executing a specific version (first version) of the executable code based on the outcome of the evaluation (determination), so that the execution is optimized for the test condition, Paragraph 9)
Chou do not disclose:
wherein a first version of the plurality of versions is compiled to comprise code optimized based on access to non-overlapping memory locations;
a determination that a performance of the program will not cause overlapping memory locations to be accessed;
However, Hikaru Takayashiki et al. disclose:
wherein a first version of the plurality of versions is compiled to comprise code optimized based on access to non-overlapping memory locations; (compiling a vectorized program assuming no overlapping memory using optimization flags (e.g. the “restrict” modifier in the C/C++ language), Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
a determination that a performance of the program will not cause overlapping memory locations to be accessed; (optimization for vectorization requires that there is no memory aliasing. In other words, vectorized programs are usually optimized (determination) by assuming no overlapping by adding some optimization flags, e.g., the ” restrict” modifier in the C/C++ language. Thus, this paper assumes that the statically unanalyzable memory disambiguation does not occur for these applications., Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hikaru Takayashiki et al. into the teaching of Chou to include wherein a first version of the plurality of versions is compiled to comprise code optimized based on access to non-overlapping memory locations and a determination that a performance of the program will not cause overlapping memory locations to be accessed in order to help optimization of vectorized programs. (Hikaru Takayashiki et al., Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
With respect to Claim 5, all the limitations of Claim 1 have been addressed above; and Chou further disclose:
wherein at least one of the plurality of precompiled versions is an optimized version of the program code. (compiler 116 can generate different versions of executable code for either an entire program (precompiled) or for specific functions that are frequently executed, wherein each version is optimized in accordance with a different optimization criterion, Paragraph 31)
With respect to Claim 6, all the limitations of Claim 1 have been addressed above; and Chou further disclose:
wherein at least one of the plurality of precompiled versions is version of the program code targeted to one or more processor architectures. (Note that compiler 116 can generate different versions of executable code for either an entire program or for specific functions that are frequently executed, wherein each version is optimized in accordance with a different optimization criterion. These optimization criteria can include, but are not limited to: degree of speculation, performance portability (i.e. runs well across processor types) (one or more processor architectures), system resource utilization, and low power-consumption., Paragraph 31)
With respect to Claim 8, all the limitations of Claim 1 have been addressed above; and Chou do not explicitly disclose:
wherein the plurality of compiled versions of program code are generated based, at least in part, on one or more directives in the program code.
However, Hikaru Takayashiki et al. disclose:
wherein the plurality of compiled versions of program code are generated based, at least in part, on one or more directives in the program code. (compiling a vectorized program assuming no overlapping memory using optimization flags (e.g. the “restrict” modifier (one or more directives) in the C/C++ language), Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hikaru Takayashiki et al. into the teaching of Chou to include wherein the plurality of compiled versions of program code are generated based, at least in part, on one or more directives in the program code in order to help optimization of vectorized programs. (Hikaru Takayashiki et al., Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
With respect to Claim 10, Chou discloses:
precompiling a plurality of versions of program code (see Figure 2; compiler produces differently optimized version of executable code, Paragraph 28), wherein a first version of the plurality of versions is compiled (compiler 116 can generate different versions of executable code for either an entire program or for specific functions that are frequently executed, wherein each version is optimized (first version) in accordance with a different optimization criterion, Paragraph 31) to comprise code optimized (for example, a first code version is optimized for the condition of a light core utilization (code optimized a first way), Paragraph 40) and a second version of the plurality of versions is compiled to comprise code without the optimizations; (second code version is optimized for the condition of a heavy core utilization (code optimized without the first way (light core utilization) and in a second way (heavy core utilization)), Paragraph 40)
selecting the first version of the plurality of precompiled versions of program code based, at least in part, on a determination at runtime; (The processor subsequently selects a version of executable code to execute based on the evaluation result, wherein the selected version of the executable code (first version) is optimized for the runtime state of the processor and/or the processor type (determination), Paragraph 34; at runtime, the processor evaluates core utilization through the branch instruction. In one embodiment of the present invention, if the processor detects more than half of the available threads on the core are utilized, the second code version is executed. Otherwise, the first code version is executed (determination/selection at runtime), Paragraph 40)
and cause the first version of the plurality of precompiled versions of program code to be performed. (subsequently executing a specific version of the executable code based on the outcome of the evaluation (determination), so that the execution is optimized for the test condition, Paragraph 9)
Chou do not disclose:
wherein a first version of the plurality of versions is compiled to comprise code optimized based on access to non-overlapping memory locations;
a determination that a performance of the program will not cause overlapping memory locations to be accessed;
However, Hikaru Takayashiki et al. disclose:
wherein a first version of the plurality of versions is compiled to comprise code optimized based on access to non-overlapping memory locations; (compiling a vectorized program assuming no overlapping memory using optimization flags (e.g. the “restrict” modifier in the C/C++ language), Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
a determination that a performance of the program will not cause overlapping memory locations to be accessed; (optimization for vectorization requires that there is no memory aliasing. In other words, vectorized programs are usually optimized (determination) by assuming no overlapping by adding some optimization flags, e.g., the ” restrict” modifier in the C/C++ language. Thus, this paper assumes that the statically unanalyzable memory disambiguation does not occur for these applications., Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hikaru Takayashiki et al. into the teaching of Chou to include wherein a first version of the plurality of versions is compiled to comprise code optimized based on access to non-overlapping memory locations and a determination that a performance of the program will not cause overlapping memory locations to be accessed in order to help optimization of vectorized programs. (Hikaru Takayashiki et al., Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
With respect to Claim 16, all the limitations of Claim 10 have been addressed above; and Chou do not explicitly disclose:
further comprising:
generating the plurality of compiled versions of program code based, at least in part, on one or more compiler directives added to the program code.
However, Hikaru Takayashiki et al. disclose:
generating the plurality of compiled versions of program code based, at least in part, on one or more compiler directives added to the program code. (compiling a vectorized program assuming no overlapping memory using optimization flags (e.g. the “restrict” modifier (one or more directives) in the C/C++ language), Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hikaru Takayashiki et al. into the teaching of Chou to include generating the plurality of compiled versions of program code based, at least in part, on one or more compiler directives added to the program code in order to help optimization of vectorized programs. (Hikaru Takayashiki et al., Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
With respect to Claim 18, all the limitations of Claim 10 have been addressed above; and Chou further disclose:
further comprising:
performing the first version of the plurality of precompiled versions of program code to select based [a determination]. (subsequently executing (performing) a specific version of the executable code based on the outcome of the evaluation (determination), so that the execution is optimized for the test condition, Paragraph 9)
Chou do not disclose:
[a determination] is based, at least in part, on whether or not the program code is to access the overlapping memory locations.
However, Hikaru Takayashiki et al. disclose:
[a determination] is based, at least in part, on whether or not the program code is to access the overlapping memory locations. (optimization for vectorization requires that there is no memory aliasing. In other words, vectorized programs are usually optimized (determination) by assuming no overlapping by adding some optimization flags, e.g., the ” restrict” modifier in the C/C++ language. Thus, this paper assumes that the statically unanalyzable memory disambiguation does not occur for these applications., Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hikaru Takayashiki et al. into the teaching of Chou to include [a determination] is based, at least in part, on whether or not the program code is to access the overlapping memory locations in order to help optimization of vectorized programs. (Hikaru Takayashiki et al., Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
With respect to Claim 19, Chou discloses:
one or more processors and memory storing executable instructions that, if performed by the one or more processors, (see Figure 1; memory includes compiler which is coupled to a processor through a bridge (one or more circuits), Paragraph 22)
precompile a plurality of versions of program code (see Figure 2; compiler produces differently optimized version of executable code, Paragraph 28), wherein a first version of the plurality of versions is compiled (compiler 116 can generate different versions of executable code for either an entire program or for specific functions that are frequently executed, wherein each version is optimized (first version) in accordance with a different optimization criterion, Paragraph 31) to comprise code optimized (for example, a first code version is optimized for the condition of a light core utilization (code optimized a first way), Paragraph 40) and a second version of the plurality of versions is compiled to comprise code without the optimizations; (second code version is optimized for the condition of a heavy core utilization (code optimized without the first way (light core utilization) and in a second way (heavy core utilization)), Paragraph 40)
select the first version of the plurality of precompiled versions of program code based, at least in part, on a determination at runtime; (The processor subsequently selects a version of executable code to execute based on the evaluation result, wherein the selected version of the executable code (first version) is optimized for the runtime state of the processor and/or the processor type (determination), Paragraph 34; at runtime, the processor evaluates core utilization through the branch instruction. In one embodiment of the present invention, if the processor detects more than half of the available threads on the core are utilized, the second code version is executed. Otherwise, the first code version is executed (determination/selection at runtime), Paragraph 40)
and cause the first version of the plurality of precompiled versions of program code to be performed. (subsequently executing a specific version of the executable code based on the outcome of the evaluation (determination), so that the execution is optimized for the test condition, Paragraph 9)
Chou do not disclose:
wherein a first version of the plurality of versions is compiled to comprise code optimized based on access to non-overlapping memory locations;
a determination that a performance of the program will not cause overlapping memory locations to be accessed;
However, Hikaru Takayashiki et al. disclose:
wherein a first version of the plurality of versions is compiled to comprise code optimized based on access to non-overlapping memory locations; (compiling a vectorized program assuming no overlapping memory using optimization flags (e.g. the “restrict” modifier in the C/C++ language), Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
a determination that a performance of the program will not cause overlapping memory locations to be accessed; (optimization for vectorization requires that there is no memory aliasing. In other words, vectorized programs are usually optimized (determination) by assuming no overlapping by adding some optimization flags, e.g., the ” restrict” modifier in the C/C++ language. Thus, this paper assumes that the statically unanalyzable memory disambiguation does not occur for these applications., Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hikaru Takayashiki et al. into the teaching of Chou to include wherein a first version of the plurality of versions is compiled to comprise code optimized based on access to non-overlapping memory locations and a determination that a performance of the program will not cause overlapping memory locations to be accessed in order to help optimization of vectorized programs. (Hikaru Takayashiki et al., Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
With respect to Claim 25, all the limitations of Claim 19 have been addressed above; and Chou further disclose:
wherein at least one of the plurality of precompiled versions is an optimized version of the program code. (compiler 116 can generate different versions of executable code for either an entire program (precompiled) or for specific functions that are frequently executed, wherein each version is optimized in accordance with a different optimization criterion, Paragraph 31)
With respect to Claim 28, Chou discloses:
precompile a plurality of versions of program code (see Figure 2; compiler produces differently optimized version of executable code, Paragraph 28), wherein a first version of the plurality of versions is compiled (compiler 116 can generate different versions of executable code for either an entire program or for specific functions that are frequently executed, wherein each version is optimized (first version) in accordance with a different optimization criterion, Paragraph 31) to comprise code optimized (for example, a first code version is optimized for the condition of a light core utilization (code optimized a first way), Paragraph 40) and a second version of the plurality of versions is compiled to comprise code without the optimizations; (second code version is optimized for the condition of a heavy core utilization (code optimized without the first way (light core utilization) and in a second way (heavy core utilization)), Paragraph 40)
select the first version of the plurality of precompiled versions of program code based, at least in part, on a determination at runtime; (The processor subsequently selects a version of executable code to execute based on the evaluation result, wherein the selected version of the executable code (first version) is optimized for the runtime state of the processor and/or the processor type (determination), Paragraph 34; at runtime, the processor evaluates core utilization through the branch instruction. In one embodiment of the present invention, if the processor detects more than half of the available threads on the core are utilized, the second code version is executed. Otherwise, the first code version is executed (determination/selection at runtime), Paragraph 40)
and cause the first version of the plurality of precompiled versions of program code to be performed. (subsequently executing a specific version of the executable code based on the outcome of the evaluation (determination), so that the execution is optimized for the test condition, Paragraph 9)
Chou do not disclose:
wherein a first version of the plurality of versions is compiled to comprise code optimized based on access to non-overlapping memory locations;
a determination that a performance of the program will not cause overlapping memory locations to be accessed;
However, Hikaru Takayashiki et al. disclose:
wherein a first version of the plurality of versions is compiled to comprise code optimized based on access to non-overlapping memory locations; (compiling a vectorized program assuming no overlapping memory using optimization flags (e.g. the “restrict” modifier in the C/C++ language), Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
a determination that a performance of the program will not cause overlapping memory locations to be accessed; (optimization for vectorization requires that there is no memory aliasing. In other words, vectorized programs are usually optimized (determination) by assuming no overlapping by adding some optimization flags, e.g., the ” restrict” modifier in the C/C++ language. Thus, this paper assumes that the statically unanalyzable memory disambiguation does not occur for these applications., Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hikaru Takayashiki et al. into the teaching of Chou to include wherein a first version of the plurality of versions is compiled to comprise code optimized based on access to non-overlapping memory locations and a determination that a performance of the program will not cause overlapping memory locations to be accessed in order to help optimization of vectorized programs. (Hikaru Takayashiki et al., Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
With respect to Claim 33, all the limitations of Claim 28 have been addressed above; and Chou do not explicitly disclose:
wherein the plurality of compiled versions of program code are generated based, at least in part, on one or more processor directives in the program code.
However, Hikaru Takayashiki et al. disclose:
wherein the plurality of compiled versions of program code are generated based, at least in part, on one or more directives in the program code. (compiling a vectorized program assuming no overlapping memory using optimization flags (e.g. the “restrict” modifier (one or more processor directives) in the C/C++ language), Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hikaru Takayashiki et al. into the teaching of Chou to include wherein the plurality of compiled versions of program code are generated based, at least in part, on one or more directives in the program code in order to help optimization of vectorized programs. (Hikaru Takayashiki et al., Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15)
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chou (US 2007/0226722) in view of Hikaru Takayashiki et al. (“Register Flush-free Runahead Execution for Modern Vector Processors, 2021) and in further view of Bourd et al. (US 2013/0222399).
With respect to Claim 2, all the limitations of Claim 1 have been addressed above; and Chou and Hikaru Takayashiki et al. do not disclose:
wherein at least one of the plurality of precompiled versions of program code is a software kernel.
However, Bourd et al. disclose:
wherein at least one of the plurality of precompiled versions of program code is a software kernel. (global memory may store precompiled source code of kernels 14A-14C, Paragraph 78)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Bourd et al. into the teaching of Chou and Hikaru Takayashiki et al. to include wherein at least one of the plurality of versions of program code is a software kernel in order to quickly execute/obtain object code of a software kernel when needed without requiring recompilation each time.
Claims 3, 9, 11, 17, 21, 30 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Chou (US 2007/0226722) in view of Hikaru Takayashiki et al. (“Register Flush-free Runahead Execution for Modern Vector Processors, 2021) and in further view of Kao (US 2019/0384706).
With respect to Claim 3, all the limitations of Claim 1 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose:
wherein the circuitry is to identify which of the plurality of precompiled versions of program code are to [perform]. (Chou, subsequently executing a specific version of the executable code based on the outcome of the evaluation (identify), so that the execution is optimized for the test condition, Paragraph 9)
Chou and Hikaru Takayashiki et al. do not disclose:
identify program code are to access overlapping memory locations is based, at least in part, on entries of a present table.
However, Kao discloses:
identify program code are to access overlapping memory locations is based, at least in part, on entries of a present table. (overlapped ranges of entries in mapping tables (present table), Paragraph 77; see Figure 4; searching a mapping table to help determine overlapped ranges, Abstract)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kao into the teaching of Chou and Hikaru Takayashiki et al. to include identify program code are to access overlapping memory locations is based, at least in part, on entries of a present table in order to help determine/identify what memory locations/ranges that overlap.
With respect to Claim 9, all the limitations of Claim 1 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose:
wherein the circuitry is to identify which of the plurality of precompiled versions of program code are to [perform]. (Chou, subsequently executing a specific version of the executable code based on the outcome of the evaluation (identify), so that the execution is optimized for the test condition, Paragraph 9)
Chou and Hikaru Takayashiki et al. do not disclose:
identify program code are to access overlapping memory locations is based, at least in part, on entries of a memory table on a first device that includes one or more identifiers of one or more memory regions on a second device.
However, Kao discloses:
identify program code are to access overlapping memory locations is based, at least in part, on entries of a memory table on a first device that includes one or more identifiers of one or more memory regions on a second device. (overlapped ranges of entries in mapping tables (memory table) wherein the memory table manages logical to physical address mapping (identifiers), Paragraph 77; see Figure 4; searching a mapping table to help determine overlapped ranges on a device (logical to physical mapping (first device to second device), Abstract)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kao into the teaching of Chou and Hikaru Takayashiki et al. to include identify program code are to access overlapping memory locations is based, at least in part, on entries of a memory table on a first device that includes one or more identifiers of one or more memory regions on a second device in order to help determine/identify what memory locations/ranges that overlap.
With respect to Claim 11, all the limitations of Claim 10 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose:
further comprising:
identifying which of the plurality of precompiled versions of program code are to [perform]. (Chou, subsequently executing a specific version of the executable code based on the outcome of the evaluation (identify), so that the execution is optimized for the test condition, Paragraph 9)
Chou and Hikaru Takayashiki et al. do not disclose:
identifying program code are to access overlapping memory locations is based, at least in part, on entries of a memory table.
However, Kao discloses:
identifying program code are to access overlapping memory locations is based, at least in part, on entries of a memory table. (overlapped ranges of entries in mapping tables (present table), Paragraph 77; see Figure 4; searching a mapping table to help determine overlapped ranges, Abstract)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kao into the teaching of Chou and Hikaru Takayashiki et al. to include identifying program code are to access overlapping memory locations is based, at least in part, on entries of a memory table in order to help determine/identify what memory locations/ranges that overlap.
With respect to Claim 17, all the limitations of Claim 10 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose:
further comprising:
identifying which of the plurality of precompiled versions of program code are to [perform]. (Chou, subsequently executing a specific version of the executable code based on the outcome of the evaluation (identify), so that the execution is optimized for the test condition, Paragraph 9)
Chou and Hikaru Takayashiki et al. do not disclose:
identifying program code are to access overlapping memory locations is based, at least in part, on entries of a memory table on a first device that includes one or more identifiers of one or more memory regions on a second device.
However, Kao discloses:
identifying program code are to access overlapping memory locations is based, at least in part, on entries of a memory table on a first device that includes one or more identifiers of one or more memory regions on a second device. (overlapped ranges of entries in mapping tables (memory table) wherein the memory table manages logical to physical address mapping (identifiers), Paragraph 77; see Figure 4; searching a mapping table to help determine overlapped ranges on a device (logical to physical mapping (first device to second device), Abstract)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kao into the teaching of Chou and Hikaru Takayashiki et al. to include identifying program code are to access overlapping memory locations is based, at least in part, on entries of a memory table on a first device that includes one or more identifiers of one or more memory regions on a second device in order to help determine/identify what memory locations/ranges that overlap.
With respect to Claim 21, all the limitations of Claim 19 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose:
wherein the one or more processors are to identify which of the plurality of precompiled versions of program code are to [perform]. (Chou, subsequently executing a specific version of the executable code based on the outcome of the evaluation (identify), so that the execution is optimized for the test condition, Paragraph 9)
Chou and Hikaru Takayashiki et al. do not disclose:
identify program code are to access overlapping memory locations is based, at least in part, on a memory table lookup.
However, Kao discloses:
identify program code are to access overlapping memory locations is based, at least in part, on a memory table lookup. (overlapped ranges of entries in mapping tables (present table), Paragraph 77; see Figure 4; searching a mapping table to help determine overlapped ranges (memory table lookup), Abstract)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kao into the teaching of Chou and Hikaru Takayashiki et al. to identify program code are to access overlapping memory locations is based, at least in part, on a memory table lookup in order to help determine/identify what memory locations/ranges that overlap.
With respect to Claim 30, all the limitations of Claim 28 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose:
wherein the set of instructions include instructions which are to identify which of the plurality of precompiled versions of program code are to [perform]. (Chou, subsequently executing a specific version of the executable code based on the outcome of the evaluation (identify), so that the execution is optimized for the test condition, Paragraph 9)
Chou and Hikaru Takayashiki et al. do not disclose:
identify program code are to access overlapping memory locations is based, at least in part, on entries on a present table.
However, Kao discloses:
identify program code are to access overlapping memory locations is based, at least in part, on entries on a present table. (overlapped ranges of entries in mapping tables (present table), Paragraph 77; see Figure 4; searching a mapping table to help determine overlapped ranges, Abstract)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kao into the teaching of Chou and Hikaru Takayashiki et al. to include identify program code are to access overlapping memory locations is based, at least in part, on entries on a present table in order to help determine/identify what memory locations/ranges that overlap.
With respect to Claim 34, all the limitations of Claim 28 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose:
the set of instructions include instructions which are to identify which of the plurality of precompiled versions of program code are to [perform]. (Chou, subsequently executing a specific version of the executable code based on the outcome of the evaluation (identify), so that the execution is optimized for the test condition, Paragraph 9)
Chou and Hikaru Takayashiki et al. do not disclose:
identify program code are to access overlapping memory locations is based, at least in part, on entries of a memory table on a first processor of the one or more processors and the memory table includes one or more identifiers of one or more memory regions of a second processor of the one or more processors.
However, Kao discloses:
identify program code are to access overlapping memory locations is based, at least in part, on entries of a memory table on a first processor of the one or more processors and the memory table includes one or more identifiers of one or more memory regions of a second processor of the one or more processors. (overlapped ranges of entries in mapping tables (memory table) wherein the memory table manages logical to physical address mapping (identifiers), Paragraph 77; see Figure 4; searching a mapping table to help determine overlapped ranges on a device (logical to physical mapping (first processor to second processor), Abstract)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kao into the teaching of Chou and Hikaru Takayashiki et al. to include identify program code are to access overlapping memory locations is based, at least in part, on entries of a memory table on a first processor of the one or more processors and the memory table includes one or more identifiers of one or more memory regions of a second processor of the one or more processors in order to help determine/identify what memory locations/ranges that overlap.
Claims 4, 12, 22 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Chou (US 2007/0226722) in view of Hikaru Takayashiki et al. (“Register Flush-free Runahead Execution for Modern Vector Processors, 2021) and in further view of Falloon et al. (US 2019/0286327).
With respect to Claim 4, all the limitations of Claim 1 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose::
wherein the circuitry is to identify which of the plurality of precompiled versions of program code are to [perform]. (Chou, subsequently executing a specific version of the executable code based on the outcome of the evaluation (identify), so that the execution is optimized for the test condition, Paragraph 9)
Chou and Hikaru Takayashiki et al. do not disclose:
identify program code are to access overlapping memory locations is based, at least in part, a reference count of memory locations.
However, Falloon et al. disclose:
identify program code are to access overlapping memory locations is based, at least in part, a reference count of memory locations. (ensuring that the memory pool slices/memory objects are isolated from each other (non-overlapping/overlapping memory ranges) by keeping track of reference counts for objects, Paragraphs 6 and 70)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Falloon et al. into the teaching of Chou and Hikaru Takayashiki et al. to include identify program code are to access overlapping memory locations is based, at least in part, a reference count of memory locations in order to ensure the protection of address spaces of different programs. (Falloon et al., Paragraph 6, lines 3-11)
With respect to Claim 12, all the limitations of Claim 10 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose::
further comprising:
identifying which of the plurality of precompiled versions of program code are to [perform]. (Chou, subsequently executing a specific version of the executable code based on the outcome of the evaluation (identify), so that the execution is optimized for the test condition, Paragraph 9)
Chou and Hikaru Takayashiki et al. do not disclose:
identifying program code are to access overlapping memory locations is based, at least in part, a present count of memory locations.
However, Falloon et al. disclose:
identifying program code are to access overlapping memory locations is based, at least in part, a present count of memory locations. (ensuring that the memory pool slices/memory objects are isolated from each other (non-overlapping/overlapping memory ranges) by keeping track of reference counts for objects, Paragraphs 6 and 70)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Falloon et al. into the teaching of Chou and Hikaru Takayashiki et al. to include identifying program code are to access overlapping memory locations is based, at least in part, a present count of memory locations in order to ensure the protection of address spaces of different programs. (Falloon et al., Paragraph 6, lines 3-11)
With respect to Claim 22, all the limitations of Claim 19 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose::
wherein the one or more circuits are to identify which of the plurality of precompiled versions of program code are to [perform]. (Chou, subsequently executing a specific version of the executable code based on the outcome of the evaluation (identify), so that the execution is optimized for the test condition, Paragraph 9)
Chou and Hikaru Takayashiki et al. do not disclose:
identify program code are to access overlapping memory locations is based, at least in part, on a present count and a memory address retrieved from a memory lookup table.
However, Falloon et al. disclose:
identify program code are to access overlapping memory locations is based, at least in part, on a present count and a memory address retrieved from a memory lookup table. (ensuring that the memory pool slices/memory objects are isolated from each other (non-overlapping/overlapping memory ranges) by keeping track of reference counts for objects and page table(s) (memory lookup table), Paragraphs 6, 30 and 70)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Falloon et al. into the teaching of Chou and Hikaru Takayashiki et al. to include identify program code are to access overlapping memory locations is based, at least in part, on a present count and a memory address retrieved from a memory lookup table in order to ensure the protection of address spaces of different programs. (Falloon et al., Paragraph 6, lines 3-11)
With respect to Claim 31, all the limitations of Claim 28 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose::
wherein the set of instructions include instructions which are to identify which of the plurality of precompiled versions of program code are to [perform]. (Chou, subsequently executing a specific version of the executable code based on the outcome of the evaluation (identify), so that the execution is optimized for the test condition, Paragraph 9)
Chou and Hikaru Takayashiki et al. do not disclose:
identify program code are to access overlapping memory locations is based, at least in part, on a present count and a memory address.
However, Falloon et al. disclose:
identify program code are to access overlapping memory locations is based, at least in part, on a present count and a memory address. (ensuring that the memory pool slices/memory objects are isolated from each other (non-overlapping/overlapping memory ranges) by keeping track of reference counts for objects and page table(s) (memory address), Paragraphs 6, 30 and 70)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Falloon et al. into the teaching of Chou and Hikaru Takayashiki et al. to include identify program code are to access overlapping memory locations is based, at least in part, on a present count and a memory address in order to ensure the protection of address spaces of different programs. (Falloon et al., Paragraph 6, lines 3-11)
Claims 7, 13-15, 20, 26-27, 29, 32 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Chou (US 2007/0226722) in view of Hikaru Takayashiki et al. (“Register Flush-free Runahead Execution for Modern Vector Processors, 2021) and in further view of Lim et al. (US 2015/0286472).
With respect to Claim 7, all the limitations of Claim 1 have been addressed above; and Chou and Hikaru Takayashiki et al. do not disclose:
wherein the first version of the plurality of precompiled version is to be selected using a graphics processing unit (GPU).
However, Lim et al. disclose:
wherein the first version of the plurality of precompiled version is to be selected using a graphics processing unit (GPU). (kernel is to execute (selected) on a CPU and/or GPU, Paragraph 32, lines 3-13)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Lim et al. into the teaching of Chou and Hikaru Takayashiki et al. to include wherein the first version of the plurality of precompiled version is to be selected using a graphics processing unit (GPU) in order to compile a program/kernel for a variety or specific type of processor such as a CPU (Central Processing Unit), GPU (Graphics Processing Unit) and/or FPGA (Field Programmable Gate Array). (Lim et al., Paragraph 2)
With respect to Claim 13, all the limitations of Claim 10 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose:
wherein at least one of the plurality of precompiled versions is an [optimized] version of the program code. (Chou, compiler 116 can generate different versions of executable code for either an entire program (precompiled) or for specific functions that are frequently executed, wherein each version is optimized in accordance with a different optimization criterion, Paragraph 31)
Chou and Hikaru Takayashiki et al. do not explicitly disclose:
[optimized] version is a parallelized version
However, Lim et al. disclose:
[optimized] version is a parallelized version (compiler may perform various techniques such as code reordering and/or vectorization which is a form of parallelization, Paragraphs 23 and 25)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Lim et al. into the teaching of Chou and Hikaru Takayashiki et al. to include performing vectorization on code in order to improve performance relative to a scalar implementation of the same code. (Lim et al., Paragraph 25)
With respect to Claim 14, all the limitations of Claim 10 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose:
wherein at least one of the plurality of precompiled versions is an [optimized] version of the program code. (Chou, compiler 116 can generate different versions of executable code for either an entire program (precompiled) or for specific functions that are frequently executed, wherein each version is optimized in accordance with a different optimization criterion, Paragraph 31)
Chou and Hikaru Takayashiki et al. do not explicitly disclose:
[optimized] version is a sequential version
However, Lim et al. disclose:
[optimized] version is a sequential version (compiler may perform optimization such as loop unrolling (sequential), Paragraphs 23 and 24)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Lim et al. into the teaching of Chou and Hikaru Takayashiki et al. to include performing loop unrolling in order to improve cache performance when executing the loop. (Lim et al., Paragraph 24)
With respect to Claim 15, all the limitations of Claim 10 have been addressed above; and Chou and Hikaru Takayashiki et al. do not disclose:
wherein the first version of the plurality of precompiled version is to be selected using a graphics accelerator.
However, Lim et al. disclose:
wherein the first version of the plurality of precompiled version is to be selected using a graphics accelerator. (kernel is to execute (selected) on a CPU and/or GPU, Paragraph 32, lines 3-13; GPU may be specialized hardware that includes integrated and/or discrete logic circuitry that provides GPU with massive parallel processing capabilities suitable for graphics processing (graphics accelerator), Paragraph 42)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Lim et al. into the teaching of Chou and Hikaru Takayashiki et al. to include wherein the first version of the plurality of precompiled version is to be selected using a graphics accelerator in order to compile a program/kernel for a variety or specific type of processor such as a CPU (Central Processing Unit), GPU (Graphics Processing Unit) and/or FPGA (Field Programmable Gate Array). (Lim et al., Paragraph 2)
With respect to Claim 20, all the limitations of Claim 19 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose:
wherein at least one of the plurality of precompiled versions is [optimized code]. (Chou, compiler 116 can generate different versions of executable code for either an entire program (precompiled) or for specific functions that are frequently executed, wherein each version is optimized in accordance with a different optimization criterion, Paragraph 31)
Chou and Hikaru Takayashiki et al. do not explicitly disclose:
[optimized code] is a graphics processing unit (GPU) kernel.
However, Lim et al. disclose:
[optimized code] is a graphics processing unit (GPU) kernel. (kernel is to execute on a CPU and/or GPU (GPU kernel), Paragraph 32, lines 3-13)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Lim et al. into the teaching of Chou and Hikaru Takayashiki et al. to include [optimized code] is a graphics processing unit (GPU) kernel in order to compile a program/kernel for a variety or specific type of processor such as a CPU (Central Processing Unit), GPU (Graphics Processing Unit), FPGA (Field Programmable Gate Array). (Lim et al., Paragraph 2)
With respect to Claim 26, all the limitations of Claim 19 have been addressed above; and Chou and Hikaru Takayashiki et al. do not disclose:
wherein the first version of the plurality of precompiled version is to be selected using a graphics processing unit (GPU).
However, Lim et al. disclose:
wherein the first version of the plurality of precompiled version is to be selected using a graphics processing unit (GPU). (kernel is to execute (selected) on a CPU and/or GPU, Paragraph 32, lines 3-13)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Lim et al. into the teaching of Chou and Hikaru Takayashiki et al. to include wherein the first version of the plurality of precompiled version is to be selected using a graphics processing unit (GPU) in order to compile a program/kernel for a variety or specific type of processor such as a CPU (Central Processing Unit), GPU (Graphics Processing Unit) and/or FPGA (Field Programmable Gate Array). (Lim et al., Paragraph 2)
With respect to Claim 27, all the limitations of Claim 19 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose:
wherein the one or more processors are to identify which of the plurality of precompiled versions of program code are to [perform]. (Chou, subsequently executing a specific version of the executable code based on the outcome of the evaluation (identify), so that the execution is optimized for the test condition, Paragraph 9)
Chou and Hikaru Takayashiki et al. do not disclose:
identify program code are to access overlapping memory locations is based, at least in part, on one or more identifiers of one or more memory regions of a GPU. (the driver/runtime generates metadata indicating a relationship (e.g., whether the memory region of the first memory reference and the second memory reference overlap, to what extent, etc.) between the first memory reference and the second memory reference, Paragraph 3-4; target processor is a GPU, Paragraph 32)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Lim et al. into the teaching of Chou and Hikaru Takayashiki et al. to include identify program code are to access overlapping memory locations is based, at least in part, on one or more identifiers of one or more memory regions of a GPU in order to determine when more aggressive compilation techniques can be performed on code. (Lim et al., Paragraph 4)
With respect to Claim 29, all the limitations of Claim 28 have been addressed above; and Chou and Hikaru Takayashiki et al. do not disclose:
wherein at least one of the plurality of precompiled version is to be executed using a graphics accelerator.
However, Lim et al. disclose:
wherein at least one of the plurality of precompiled version is to be executed using a graphics accelerator. (kernel is to execute on a CPU and/or GPU, Paragraph 32, lines 3-13; GPU may be specialized hardware that includes integrated and/or discrete logic circuitry that provides GPU with massive parallel processing capabilities suitable for graphics processing (graphics accelerator), Paragraph 42)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Lim et al. into the teaching of Chou and Hikaru Takayashiki et al. to include wherein at least one of the plurality of precompiled version is to be executed using a graphics accelerator in order to be able to execute a program/kernel on a specific type of processor such as a CPU (Central Processing Unit), GPU (Graphics Processing Unit) and/or FPGA (Field Programmable Gate Array). (Lim et al., Paragraph 2)
With respect to Claim 32, all the limitations of Claim 28 have been addressed above; and Chou and Hikaru Takayashiki et al. do not explicitly disclose:
wherein at least one of the plurality of precompiled versions is to be performed by a plurality of threads.
However, Lim et al. disclose:
wherein at least one of the plurality of precompiled versions is to be performed by a plurality of threads. (compiler may perform various techniques such as code reordering and/or vectorization which is a form of parallelization (plurality of threads), Paragraphs 23 and 25; schedule of GPU creates threads which performs the basic unit of work associated with the kernel (precompiled version), Paragraph 49)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Lim et al. into the teaching of Chou and Hikaru Takayashiki et al. to include wherein at least one of the plurality of precompiled versions is to be performed by a plurality of threads in order to improve performance relative to a scalar implementation of the same code. (Lim et al., Paragraph 25)
With respect to Claim 35, all the limitations of Claim 28 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose:
wherein the first version of the plurality of precompiled versions of program code to be selected is to be performed based, at least in part, on which of the plurality of versions of program code are to [a test condition] (Chou, subsequently executing (performing) a specific version of the executable code based on the outcome of the evaluation (determination), so that the execution is optimized for the test condition, Paragraph 9)
Chou and Hikaru Takayashiki et al. do not disclose:
[a test condition] to access the overlapping memory locations.
However, Lim et al. disclose:
[a test condition] to access the overlapping memory locations. (the driver/runtime generates metadata indicating a relationship (e.g., whether the memory region of the first memory reference and the second memory reference overlap, to what extent, etc.) between the first memory reference and the second memory reference, Paragraph 3-4; target processor is a GPU, Paragraph 32)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Lim et al. into the teaching of Chou and Hikaru Takayashiki et al. to include [a test condition] to access the overlapping memory locations in order to determine when more aggressive compilation techniques can be performed on code. (Lim et al., Paragraph 4)
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Chou (US 2007/0226722) in view of Hikaru Takayashiki et al. (“Register Flush-free Runahead Execution for Modern Vector Processors, 2021) in view of Kao (US 2019/0384706) and in further view of Logan (5,146,571).
With respect to Claim 23, all the limitations of Claim 19 have been addressed above; and Chou and Hikaru Takayashiki et al. further disclose:
wherein the one or more processors are to identify which of the plurality of precompiled versions of program code are to [perform]. (Chou, subsequently executing a specific version of the executable code based on the outcome of the evaluation (identify), so that the execution is optimized for the test condition, Paragraph 9)
Chou and Hikaru Takayashiki et al. do not disclose:
identify program code are to access overlapping memory locations is based, at least in part, present data obtained from a balanced tree structure.
However, Kao discloses:
identify program code are to access overlapping memory locations is based, at least in part, present data obtained from [a memory table]. (overlapped ranges of entries in mapping tables (present table), Paragraph 77; see Figure 4; searching a mapping table to help determine overlapped ranges, Abstract)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kao into the teaching of Chou and Hikaru Takayashiki et al. to include identify program code are to access overlapping memory locations is based, at least in part, present data obtained from [a memory table] in order to help determine/identify what memory locations/ranges that overlap.
Chou, Hikaru Takayashiki et al. and Kao do not disclose:
[memory table] is a balanced tree structure;
However, Logan discloses:
[memory table] is a balanced tree structure; (memory table organized as a tree structure, Column 6, lines 58-67)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Logan into the teaching of Chou, Hikaru Takayashiki et al. and Kao to include [memory table] as a balanced tree structure for reasons of design choice of the developer or to permit mapping of addresses in real time with minimal degradation of system performance. (Logan, Column 2, lines 44-48)
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chou (US 2007/0226722) in view of Hikaru Takayashiki et al. (“Register Flush-free Runahead Execution for Modern Vector Processors, 2021) and in further view of Michaud et al. (US 9,104,436).
With respect to Claim 24, all the limitations of Claim 19 have been addressed above; and Chou and Hikaru Takayashiki et al. do not disclose:
wherein at least one of the plurality of precompiled versions of program code is a non-optimized version of the program code.
However, Michaud et al. disclose:
wherein at least one of the plurality of precompiled versions of program code is a non-optimized version of the program code. (machine code (precompiled code) is non-optimized, Column 6, lines 48-49)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Michaud et al. into the teaching of Chou and Hikaru Takayashiki et al. to include wherein at least one of the plurality of precompiled versions of program code is a non-optimized version of the program code in order to be able to compare performance of an optimized and non-optimized version of program code.
Response to Arguments
Applicant’s arguments, see Pages 10-11, filed December 12, 2025, with respect to §101 and §112(b) rejections have been fully considered and are persuasive. The §101 and §112(b) rejections of claims 1-35 have been withdrawn. However, a new §112(b) rejection of claims 1-35 has been issued in light of the amendments.
Applicant's arguments filed December 12, 2025 with respect to the §103 rejections have been fully considered but they are not persuasive.
In the Remarks, Applicant argues:
The Office Action asserts that Chou discloses a system that precompiles multiple versions of program code, selects a version based on runtime conditions, and executes the selected version. See Office Action, pp. 18-19. The Office Action then concedes that Chou does not disclose the first version is compiled to comprise code to access non-overlapping memory locations; and a determination that performance of the program will not cause overlapping memory locations to be accessed. The Office Action instead relies on Takayashiki to teach these features. Specifically, the Office Action asserts that Takayashiki teaches compiling program code with optimization flags (e.g., the "restrict" modifier in C/C++) to indicate that the code will not access overlapping memory locations. See Office Action, pp. 18-20, citing Takayashiki, p. 121, Section B. Applicant
respectfully disagrees for the following reasons:
Chou discloses a system that precompiles multiple versions of executable code optimized for different runtime conditions, such as processor type, core utilization, and temperature. See Chou at [0033]-[0035]. However, Chou does not teach or suggest compiling a version of program code specifically optimized to avoid overlapping memory locations. The optimization criteria described in Chou are unrelated to memory overlap and focus instead on runtime conditions that affect processor performance. The absence of any discussion of memory overlap determination in Chou indicates that this feature is not within the scope of its teachings.
Furthermore, while Chou describes selecting a version of executable code based on runtime evaluations, id. at [0034], these evaluations are limited to processor-specific conditions and do not involve determining at runtime whether overlapping memory locations will be accessed.
Examiner’s Response:
The Examiner respectfully disagrees. Applicant argues that Chou “does not teach or suggest compiling a version of program code specifically optimized to avoid overlapping memory locations.” As can be seen in the updated §103 rejection above, the Examiner has not relied upon Chou to disclose this limitation. This limitation is instead taught by Takayashiki. Specifically, Takayashiki discloses compiling a vectorized program assuming no overlapping memory using optimization flags (e.g. the “restrict” modifier in the C/C++ language) (see Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15). This citation can be reasonably interpreted as the Applicant’s “optimized to avoid overlapping memory locations”.
Further, Applicant argues that Chou “do[es] not involve determining at runtime whether overlapping memory locations will be accessed.” As can be seen in the updated §103 rejection above, the Examiner has not relied upon Chou to disclose this limitation. Chou was used to disclose that a “determination” is made “at runtime” (see Paragraphs 34 and 40). Takayashiki was used to modify this determination. Specifically, Takayashiki discloses making a determination to optimize for vectorization which requires that there is no memory aliasing (program code will not cause overlapping memory locations) (see Page 121, B. Limitations and assumptions, Paragraph 1, lines 3-15).
Therefore, for at least the reasons set forth above, the rejection made under 35 U.S.C. §103 with respect to claim 1 is proper and thus, maintained.
In the Remarks, Applicant argues:
Takayashiki describes the use of optimization flags, such as the "restrict" modifier in C/C++, to compile code under the assumption that memory aliasing does not occur. See Takayashiki at p. 121, Section B. While this may suggest a static compilation technique for optimizing code based on non-overlapping memory assumptions, Takayashiki does not teach or suggest dynamically selecting between versions of code based on a runtime determination of memory overlap. The optimization flags described in Takayashiki are applied during compilation and do not involve any runtime decision-making process.
In contrast, claim 1 recites "wherein a first version of the plurality of versions is compiled to comprise code optimized based on access to non-overlapping memory locations and a second version of the plurality of versions is compiled to comprise code without the optimizations" and "select the first version of the plurality of precompiled versions of program code based, at least in part, on a determination at runtime that a performance of the program code will not cause overlapping memory locations to be accessed." Takayashiki does not teach selecting a version of precompiled program code during runtime based on a determination of memory overlap.
Examiner’s Response:
The Examiner respectfully disagrees. Applicant argues that Takayashiki “does not teach or suggest dynamically selecting between versions of code based on a runtime determination of memory overlap.” As can be seen in the updated §103 rejection above, the Examiner has not relied solely upon Takayashiki to disclose this limitation. It is through the combination of Chou and Takayashiki that disclose this limitation as explained in the previous response to arguments above.
Therefore, for at least the reasons set forth above, the rejection made under 35 U.S.C. §103 with respect to claim 1 is proper and thus, maintained.
In the Remarks, Applicant argues:
Moreover, the combination of Chou and Takayashiki would not have been obvious. The teachings of Takayashiki are limited to static compilation techniques and do not suggest any dynamic runtime selection mechanism. Furthermore, the use of the "restrict" modifier in Takayashiki does not imply that it would be appropriate to select code compiled with this modifier instead of code compiled without it, or vice versa. As such, it would not have been obvious to modify Chou in view of Takayashiki to arrive at claim 1.
Examiner’s Response:
The Examiner respectfully disagrees. Applicant argues that “Takayashiki are limited to static compilation techniques and do not suggest any dynamic runtime selection mechanism”. As stated above, Takayashiki was not used to disclose a dynamic runtime selection mechanism. Chou discloses the “dynamic runtime selection mechanism” as shown above in the updated §103 rejection. Takayashiki was used to modify Chou’s teaching of a “dynamic runtime selection mechanism” to include source code that has been optimized based on access to non-overlapping memory locations.
Further, it is the Examiner’s position that the combination of Chou and Takayashiki would have been obvious to one of ordinary skill in the art. Specifically, Chou discloses selectively executing an optimized version of executable code based on a test condition/criteria. Chou is silent that the specific code optimization comprises code optimized based on access to non-overlapping memory locations. Takayashiki was used to modify the specific type of optimization as well as the condition/criteria of when to execute a specific optimized version of executable code such as optimizing for vectorization which requires no memory aliasing (determination/criteria) thus the non-overlapping memory locations would be selected.
Therefore, for at least the reasons set forth above, the rejection made under 35 U.S.C. §103 with respect to claim 1 is proper and thus, maintained.
In the Remarks, Applicant argues:
Applicant respectfully submits that claims 10, 19, and 28 are allowable at least for reasons including some of those discussed above in connection with claim 1. For example, claim 10 recites "wherein a first version of the plurality of versions is compiled to comprise code optimized based on access to non-overlapping memory locations and a second version of the plurality of versions is compiled to comprise code without the optimizations." Claims 19 and 28 also include recitations which are similar, though not necessarily identical, to those of claim 1.
For at least the reasons discussed above, Applicant respectfully submits that the proposed combination of Chou, Takayashiki, and any other cited references does not teach or suggest such subject matter as recited in claims 10, 19, and 28. Therefore, Applicant respectfully submits that claims 10, 19, and 28 are allowable under 35 U.S.C. § 103 over Chou in view of Takayashiki and any other cited references. Withdrawal of the pending rejection under 35 U.S.C. § 103 is, therefore, respectfully requested.
Examiner’s Response:
The Examiner respectfully disagrees. Please see response to arguments above with respect to claim 1.
In the Remarks, Applicant argues:
Claims 2-9, 11-18, 20-27, and 29-35 each depend from one of claims 1, 10, 19, and 28 described above. Accordingly, Applicant respectfully submits that claims 2-9, 11-18, 20-27, and 29-35 are allowable at least for depending from an allowable independent claim.
In addition, Applicant respectfully submits that at least some of claims 2-9, 11-18, 20-27, 29-35 additionally recite patentable subject matter not taught or otherwise rendered obvious by Chou, Takayashiki, and other references, individually or in combination.
For example:
Claim 2: The rejection relies on Bourd, et al. to disclose that at least one of the precompiled versions is a software kernel. However, Bourd, et al. does not teach or suggest the specific runtime selection mechanism recited in the claims.
Claims 3, 9, 11, 17, 21, 30, and 34: The rejection relies on Kao to disclose identifying overlapping memory locations based on entries in a memory table. However, Kao does not teach or suggest the claimed combination of features, including the runtime determination of memory overlap and selection of precompiled versions.
Claims 4, 12, 22, and 31: The rejection relies on Falloon to disclose identifying overlapping memory locations based on reference counts or memory lookup tables. However, Falloon, et al. does not teach or suggest the claimed combination of features, including the specific use of memory tables and runtime selection mechanisms.
Claims 7, 13-15, 20, 26-27, 29, 32, and 35: The rejection relies on Lim to disclose the use of GPUs or graphics accelerators for selecting or executing precompiled versions. However, Lim, et al. does not teach or suggest the claimed combination of features, including the runtime determination of memory overlap and selection of precompiled versions.
For at least the reasons discussed above, Applicant respectfully submits that claims 2-9, 11-18, 20-27, 29-35 are allowable under 35 U.S.C. § 103 over Chou, Takayashiki and the additional references cited in the rejections. Withdrawal of the pending rejections of these claims is, therefore, respectfully requested.
For at least reasons discussed above, Applicant respectfully submits that claims 1-35 are allowable under 35 U.S.C. § 103. Withdrawal of the pending rejections of these claims is, therefore, respectfully requested.
Examiner’s Response:
The Examiner respectfully disagrees. Please see response to arguments above with respect to claim 1. Further, for claim 2, prior art Bourd was not used to disclose “the specific runtime selection mechanism”. Further still, for claim 3, 9, 11, 17, 21, 30, and 34, prior art Kao was not used to disclose “runtime determination of memory overlap and selection of precompiled versions”. Further still, for claims 4, 12, 22, and 31, prior art Falloon was not used to disclose “runtime selection mechanisms” and/or the current claim language does not include any “specific use of memory tables”. Further still, claims 7, 13-15, 20, 26-27, 29, 32, and 35, prior art Lim was not used to disclose “runtime determination of memory overlap and selection of precompiled versions”. The claim limitations of “runtime determination of memory overlap” and “selection of precompiled versions”, as stated above, are disclosed though the combination of Chou and Takayashiki.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LANNY N UNG/Examiner, Art Unit 2197