DETAILED ACTION
This Office action is in response to the RCE filed 2 June 2026. Claims 1-5, 7-18 are currently pending; claims 10-17 stand withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 19 May 2026 has been entered.
Drawings
It is noted that the drawing objections as set forth in the Non-Final Office action mailed 9 October 2025 were overcome by the amendments to the claims filed 8 January 2026; thus, the drawing objections are withdrawn.
Response to Arguments
Applicant's arguments filed 19 May 2026 have been fully considered but they are not persuasive; the rejections of the claims have been modified in response to Applicant's amendments to the claims. The amended limitations are addressed by the modified rejections below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0352727 A1 to Cheng et al. (hereinafter “Cheng”).
Regarding independent claim 1, Cheng (Figs. 11A-C; figures are understood to illustrate a representative subsection of the substrate, as is customary in the art) discloses a semiconductor device, comprising:
a plurality of fins 302 (¶ 0054; Fig. 11A) grouped in a fin array, the plurality of fins including a pair of edge fins 302 (Fig. 11C), wherein:
a first symmetrical cross-sectional profile of an upper portion (Figs. 11B, 11C - “top portion of fins”) of each of the plurality of fins 302 located above a top surface of a shallow trench isolation layer 802 (¶ 0055) is substantially similar (Figs. 11B-11C);
a second symmetrical cross-sectional profile of a bottom portion (portion of 302 below the top surface of 802) of one or more inner fins 302 (Fig. 11B) in the fin array located below the top surface of the shallow trench isolation layer 802 is different than a third profile of the bottom portion (Fig. 11C - portion of 302 below top surface of 802) of the edge fins 302 (Fig. 11C) in the fin array located below the top surface of the shallow trench isolation layer 802; and
a smallest lateral width of the bottom portion of the edge fins 302 (Fig. 11C) in the fin array located below the top surface of the shallow trench isolation layer 802 is greater than a largest lateral width of the bottom portion of the one or more inner fins 302 (Fig. 11B) in the fin array located below the top surface of the shallow trench isolation layer 802.
Cheng does not expressly disclose the feature “the one or more inner fins located between the pair of edge fins”, however, one of skill in the art would understand the figures of Cheng to illustrate a representative subsection of the substrate, and the substrate would comprise repeated sections such as those illustrated in Fig. 11A. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a fin configuration including one or more inner fins located between the pair of edge fins for the purpose of forming logic devices requiring multiple fins and different source and drain epitaxy configurations while maintaining consistent fin pitch (Cheng, ¶¶ 0002-06).
Regarding claim 2, Cheng (Figs. 11A-C) discloses the semiconductor device of claim 1, wherein the first symmetrical cross-sectional profile of the upper portion (Figs. 11B, 11C - “top portion of fins”) of each of the plurality of fins 302 located above the top surface of the shallow trench isolation layer 802 comprise a symmetrical cross-sectional profile selected from the group consisting of a linear tapered profile, a parabolic tapered profile, an exponential tapered profile, and a non-tapered profile having a constant width (Figs. 11B, 11C - non-tapered profile having a constant width).
Regarding claim 3, Cheng (Figs. 11A-C) discloses the semiconductor device of claim 1, wherein the one or more inner fins 302 (Fig. 11B) in the fin array comprise a symmetrical cross-sectional profile selected from the group consisting of a linear tapered profile, a parabolic tapered profile, an exponential tapered profile, and a non-tapered profile having a constant width (Fig. 11 - non-tapered profile having a constant width).
Regarding claim 5, Cheng (Figs. 11A-C) discloses the semiconductor device of claim 1, wherein: a smallest lateral width of the upper portion (Fig. 11C - “top portion of fins”) of the edge fins 302 (Fig. 11C) in the fin array located above the top surface of the shallow trench isolation layer 802 is substantially similar to a smallest lateral width of the upper portion (Fig. 11B - “top portion of fins”) of the one or more inner fins 302 (Fig. 11B) in the fin array located above the top surface of the shallow trench isolation layer 802; and a largest lateral width of the upper portion (Fig. 11C - “top portion of fins”) of the edge fins 302 (Fig. 11C) in the fin array located above the top surface of the shallow trench isolation layer 802 is substantially similar to a largest lateral width of the upper portion (Fig. 11B - “top portion of fins”) of the one or more inner fins 302 (Fig. 11B) in the fin array located above the top surface of the shallow trench isolation layer 802.
Regarding claim 7, Cheng (Figs. 11A-C) discloses the semiconductor device of claim 1, wherein the shallow trench isolation layer 802 is formed from at least one material selected from the group consisting of silicon dioxide (SiO.sub.2), silicon oxide (SiO), a nitride, an undoped polysilicon, and combinations thereof (¶ 0050 - silicon dioxide).
Regarding claim 8, Cheng (Figs. 11A-C) discloses the semiconductor device of claim 1, wherein the plurality of fins in the fin array are formed from at least one of silicon, gallium arsenide, germanium, or a nano sheet stack (¶ 0040).
Regarding claim 9, Cheng (Figs. 11A-C) discloses the semiconductor device of claim 1, wherein the fin array is formed as part of a FinFET or a Nanosheet FET (¶ 0038).
Claims 4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claim 1 above, and further in view of US 2021/0366776 A1 to Sung et al. (hereinafter “Sung”).
Regarding claim 4, Cheng (Figs. 11A-C) discloses the semiconductor device of claim 1, wherein the one or more inner fins 302 (Fig. 11B) in the fin array have a symmetrical cross-sectional profile.
Cheng fails to expressly disclose: the edge fins in the fin array have an asymmetrical cross-sectional profile. In the same field of endeavor, Sung (Fig. 10) discloses a semiconductor device including fins 204 (¶ 0056) having an asymmetrical cross-sectional profile (¶ 0057). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the edge fins of Cheng to include an asymmetrical cross-sectional profile as disclosed by Sung for the purpose of providing enhanced electrical properties while decreasing drain induced barrier lowering (DIBL) (¶ 0057).
Regarding claim 18, Cheng (Figs. 11A-C) discloses the semiconductor device of claim 1, however fails to expressly disclose: wherein the upper portion of the edge fins located above the top surface of the shallow trench isolation layer is laterally offset from a centerline of the bottom portion of the edge fins in the fin array located below the top surface of the shallow trench isolation layer. In the same field of endeavor, Sung (Fig. 10) discloses a semiconductor device including fins 204 (¶ 0056) having an upper portion 225 (¶ 0056) located above a top surface 264 (¶ 0055) of a shallow trench isolation layer 255 (¶ 0051) that is laterally offset from a centerline CL2 (¶ 0055) of the bottom portion of the fins (Fig. 10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the edge fins of Cheng to the recited fin shape as disclosed by Sung for the purpose of providing enhanced electrical properties while decreasing drain induced barrier lowering (DIBL) (¶ 0057).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
CANDICE Y. CHAN
Examiner
Art Unit 2813
18 June 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights