DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-30 are pending.
The U.S.C. 112 rejections, other than those stated below, have been corrected and the rejections are withdrawn.
Claim Interpretation
Based on broadest reasonable interpretation a processor can be interpreted as a CPU, a GPU, DSP, an accelerator, a core, a group of cores, or a group of processors because all of these devices process information.
Based on broadest reasonable interpretation a cluster of processors can be interpreted as two or more processors. For example, multiple CPUs, multiple GPUs or at least one CPU and at least one GPU.
Based on broadest reasonable interpretation a same operation may be a same task, job, workload, instruction, sequence of commands, or application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 23-24 and 27-28 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 23 recites “the processor in the cluster of processors” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the processor in the cluster of processors” will be read as “a processor in the cluster of processors”.
Claim 24 recites “the processor in the cluster of processors” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the processor in the cluster of processors” will be read as “a processor in the cluster of processors”.
Claim 27 recites “the processor in the cluster of processors” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the processor in the cluster of processors” will be read as “a processor in the cluster of processors”.
Claim 28 recites “the processor in the cluster of processors” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the processor in the cluster of processors” will be read as “a processor in the cluster of processors”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 8-12, 15-16, 21-22, 24, and 26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Masters et al. (US 20230093426).
Regarding claim 1, Masters teaches
One or more processors comprising: processing circuitry to coordinate multiple processors (Fig. 2 (210-1 to 210-N)) in a cluster of processors (Fig. 2 (202-1)) within a power budget of the cluster based, at least in part, on at least two of a variety of measured processor metrics for respective processors of the multiple processors in the cluster. (Figs. 2-6, [0057], “The system controller 204 manages systemwide performance and power consumption by assigning a respective power allocation 404 to each of the plurality of the processing clusters 202. For each processing cluster 202, the respective power allocation 404 is sometimes called a power budget, and specifies a maximum amount of power that a given processing cluster may consume.”, [0063], “For each processor 210, the performance information 302 includes one or more of: one or more activity levels 504, energy consumption 506, a temperature 508, one or more performance breach counts 510, one or more performance breach limits 512, a peak power throttling setting 514, and DVFS settings 516. An activity level 504 is defined as a number of instructions executed by the respective processor 210 during each clock cycle. A count of performance limit breach 510 is defined as a number of times a respective performance breach limit is reached within a respective time period, e.g., a number of times the respective processor 210 breaches an overcurrent limit).” [0046], “In accordance with the performance information 302 collected from different processors 210, the power management processor 216 executes first instructions 304-1 to transition a first processor 210-1 of the plurality of processors 210 from a first performance state PS1 to a second performance state PS2 …The second performance state PS2 is different from the first performance state PS1. … the performance state of other processors 210 may be changed in coordination with changing the performance state of the first processor 210-1 to optimize performance states across the plurality of processors 210, for example to satisfy an overall power allocation for the first processing cluster 202-1” where the at least two of a variety of measured processor metrics is interpreted the performance information including activity levels, energy consumption, temperature, and/or performance breach limits)
Regarding claim 2, Masters teaches wherein the increase of a first operating frequency of the processor in the cluster of processors and a decrease of a second operating frequency of another processor in the cluster of processors is based, at least in part, on a power limitation. (Figs. 2-6, [0046], “In accordance with the performance information 302 collected from different processors 210, the power management processor 216 executes first instructions 304-1 to transition a first processor 210-1 of the plurality of processors 210 from a first performance state PS1 to a second performance state PS2 …The second performance state PS2 is different from the first performance state PS1. … the performance state of other processors 210 may be changed in coordination with changing the performance state of the first processor 210-1 to optimize performance states across the plurality of processors 210, for example to satisfy an overall power allocation for the first processing cluster 202-1” and [0047], “ in accordance with the performance information indicating a drop in a temperature of the first processor 210-1 (e.g., the temperature is lower than the same or a lower predefined temperature threshold), the power management processor 216 increases power consumption of the first processor 210-1 by enabling the second performance state PS2 that is associated with a higher clock frequency 308-1 and/or a higher supply voltage 306-1 than the first performance state PS1.”)
Regarding claim 3, Masters teaches wherein an increase of the first operating frequency of the processor in the cluster of processors and a decrease of the second operating frequency of another processor in the cluster of processors is based, at least in part, on an activity value. (Figs. 2-6, [0046], “In accordance with the performance information 302 collected from different processors 210, the power management processor 216 executes first instructions 304-1 to transition a first processor 210-1 of the plurality of processors 210 from a first performance state PS1 to a second performance state PS2 …The second performance state PS2 is different from the first performance state PS1. … the performance state of other processors 210 may be changed in coordination with changing the performance state of the first processor 210-1 to optimize performance states across the plurality of processors 210, for example to satisfy an overall power allocation for the first processing cluster 202-1” and [0048], “in accordance with the performance information 302 indicating the respective number of performance limit breaches in the respective time period that drops below the same or a distinct threshold number of performance limit breaches for the respective time period, the second performance state PS2 is a state that is associated with higher power consumption than the first performance state PS1. For example, if it is determined that the count of current limit breach drops below a second overcurrent limit (e.g., 5% of all samples) within a minute, the power management processor 216 increases power consumption of the first processor 210-1 by enabling the second performance state PS2 that is associated with a higher clock frequency 308-1 and/or a higher supply voltage 306-1 than the first performance state PS1.”)
Regarding claim 4, Masters teaches wherein an increase of the first operating frequency of the processor in the cluster of processors and a decrease of the second operating frequency of another processor in the cluster of processors is based, at least in part, on a temperature value. (Figs. 2-6, [0046], “In accordance with the performance information 302 collected from different processors 210, the power management processor 216 executes first instructions 304-1 to transition a first processor 210-1 of the plurality of processors 210 from a first performance state PS1 to a second performance state PS2 …The second performance state PS2 is different from the first performance state PS1. … the performance state of other processors 210 may be changed in coordination with changing the performance state of the first processor 210-1 to optimize performance states across the plurality of processors 210, for example to satisfy an overall power allocation for the first processing cluster 202-1” and [0047], “ in accordance with the performance information indicating a drop in a temperature of the first processor 210-1 (e.g., the temperature is lower than the same or a lower predefined temperature threshold), the power management processor 216 increases power consumption of the first processor 210-1 by enabling the second performance state PS2 that is associated with a higher clock frequency 308-1 and/or a higher supply voltage 306-1 than the first performance state PS1.”)
Regarding claim 6, Masters teaches wherein an increase of the first operating frequency of the processor in the cluster of processors and a decrease of the second operating frequency of another processor in the cluster of processors is based, at least in part, on voltage values reported by the one or more other processors in the cluster of processors. ([0004], “For each cluster of processors, the respective power management processor is coupled to each processor in the respective cluster, and configured to control respective performance states (e.g., voltage and/or frequency), and/or perform debugging, of the processors of the cluster.” And [0047], “in accordance with the performance information indicating a drop in a temperature of the first processor 210-1 (e.g., the temperature is lower than the same or a lower predefined temperature threshold), the power management processor 216 increases power consumption of the first processor 210-1 by enabling the second performance state PS2 that is associated with a higher clock frequency 308-1 and/or a higher supply voltage 306-1 than the first performance state PS1.”)
Regarding claim 12, Masters teaches wherein increasing a first operating frequency of the processor in the cluster of processors is based, at least in part, on the decrease of a second operating frequency of another processor in the cluster of processors. (Figs. 2-6, [0046], “In accordance with the performance information 302 collected from different processors 210, the power management processor 216 executes first instructions 304-1 to transition a first processor 210-1 of the plurality of processors 210 from a first performance state PS1 to a second performance state PS2 …The second performance state PS2 is different from the first performance state PS1. … the performance state of other processors 210 may be changed in coordination with changing the performance state of the first processor 210-1 to optimize performance states across the plurality of processors 210, for example to satisfy an overall power allocation for the first processing cluster 202-1” and [0047], “Stated another way, at a current time, the temperature of the first processor 210-1 is measured to be higher than a temperature of the first processor 210-1 previously received, be higher than a predefined temperature threshold, or increase at a rate faster than a predefined temperature increase rate. In response, the power management processor 216 controls the first processor 210-1 to transition to the second performance state PS2 that is associated with lower power consumption than the first performance state PS1. In an example, the second performance state PS2 is associated with a lower clock frequency 308-1 and/or a lower supply voltage 306-1.”)
Regarding claim 21, Masters teaches wherein of one of the two or more processors and are members of a processor group. ([0057], “the plurality of the processing clusters 202, cache 206, and memory 104 are grouped to a plurality of power domains, and the system controller 204 assigns a respective power allocation to each of the plurality of power domain.”).
As to claims 8, 15, 16, and 22, Masters teaches these claims according to the reasoning provided in claim 1.
As to claim 9, Masters teaches this claim according to the reasoning provided in claim 2.
As to claims 10 and 26, Masters teaches these claims according to the reasoning provided in claim 3.
As to claim 11, Masters teaches this claim according to the reasoning provided in claim 4.
As to claim 24, Masters teaches this claim according to the reasoning provided in claim 6.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 19, 23, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masters in view of Gendler et al. (US 20150169365)
Regarding claim 5, Masters teaches increasing a first operating frequency of the processor in the cluster of processors and decreasing a second operating frequency of another processor in the cluster of processor but does not specifically teach that the change in frequencies is related to a number of processing cores.
Gendler teaches wherein the first operating frequency of the processor in the cluster of processors is to be increased and a second operating frequency of another processor in the cluster of processors is to be decreased based, at least in part, on a number of processing cores. (Fig. 2, [0035], “the processing logic calculates an aggregate power value based on the monitored at least one power attribute. For example, when the processing logic monitors power of multiple functional units in a hybrid configuration, the processing logic can calculate a power for each of the functional units. In implementations, the processing logic can calculate a frequency ratio for the functional units using the following methodology. For purposes of illustration and for simplicity, two functional units (unit A and unit B) are described, but it should be noted that any number and configuration of different functional units is contemplated. Assuming that the performance of the two functional units A and B should be equal, as in:” and [0048], “unit B is to handle fewer instructions per cycle than unit A. When calculating the different frequency for each of the units at block 220, the processing logic can calculate a maximum frequency for unit B. Once the maximum frequency of unit B is known, the processing logic can calculate a frequency for unit A.” where the aggregate power value is determined by the number of cores and therefore the frequencies are determined based on the number of cores.)
Masters and Gendler are analogous art. Gendler is cited to teach a similar concept of power management. Gendler teaches increasing a frequency of a first core while decreasing the frequency of a second core. Masters teach increasing a frequency of a first processor while decreasing the frequency of second processor. Gendler additionally teaches that the determination of frequency changes can be based on the number of cores in the processor where one of ordinary skill in the art at the time the invention was filed would understand that using this known technique on similar devices would yield predictable results.. Based on Gendler and the KSR rationale of the use of known technique to improve similar devices (methods, or products) in the same way, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Masters to consider the number of cores when changing frequencies of the processors.
Regarding claim 19, Masters teaches increasing a first operating frequency of one of the processors and decreasing a second operating frequency of a second processor but does not specifically teach that it is based on measured power consumption.
Gendler teaches wherein an increase of the first operating frequency of the processor in the cluster of processors and a decrease of the second operating frequency of another processor in the cluster of processors is based, at least in part, on one or more measured power consumption values of the two or more processors. ([0034], “For example, the processing logic can measure a maximum power consumption of a functional unit or a cumulative energy consumption of a functional unit.”)
Masters and Gendler are analogous art. Gendler is cited to teach a similar concept of power management. Gendler teaches increasing a frequency of a first core while decreasing the frequency of a second core. Masters teach increasing a frequency of a first processor while decreasing the frequency of a second processor. Gendler additionally teaches that the determination of frequency changes can be based on the measured power where one of ordinary skill in the art at the time the invention was filed would understand that using this known technique on similar devices would yield predictable results.. Based on Gendler and the KSR rationale of the use of known technique to improve similar devices (methods, or products) in the same way, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Masters to measure the power when changing frequencies of the processors.
Regarding claim 23, Masters teaches increasing a first operating frequency of one of the processors and decreasing a second operating frequency of a second processor but does not specifically teach that it is based on capacitance
Gendler teaches wherein a modification of an operating frequency of the processor in the cluster of processors is based, at least in part, on a capacitance value of the one or more other processors in the cluster of processors. (Where the power calculations which determine the frequencies of operation are based on capacitance. ([0040-41], “Next, the aggregate power value for each core can be calculated using the equation: P=C.times.f.times.V.sup.2, where P=power, C=capacitance, f=frequency and V=voltage.”)
Masters and Gendler are analogous art. Gendler is cited to teach a similar concept of power management. Gendler teaches increasing a frequency of a first core while decreasing the frequency of a second core. Masters teach increasing a frequency of a first processor while decreasing the frequency of a second processor. Gendler additionally teaches that the determination of frequency changes can be based on the capacitance, where one of ordinary skill in the art at the time the invention was filed would understand that using this known technique on similar devices would yield predictable results. Based on Gendler and the KSR rationale of the use of known technique to improve similar devices (methods, or products) in the same way, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Masters to use capacitance when changing frequencies of the cores.
As to claim 25, Masters and Gendler teach this claim according to the reasoning provided in claims 16 and 19.
Claim(s) 7 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masters in view of Halverson et al. (US 20190004585)
Regarding claim 7, Masters teaches increasing a first operating frequency of one of the processors and decreasing a second operating frequency of a second processor but does not specifically teach using a target frequency.
Halverson teaches wherein an increase of a first operating frequency of the processor in the cluster of processors and a decrease of a second operating frequency of another processor in the cluster of processors is based, at least in part, on target operating frequencies calculated by one or more other processors in the cluster of processors. (Fig. 12, [0104], “As 612, control calculates an effective utilization based on the ratio of A to the sum of A and B. At 616, if the effective utilization exceeds the threshold, control transfers to 620; otherwise, control transfers to 624. If the effective utilization is above a threshold, that may indicate overutilization of the core—in other words, that the frequency of the core should be increased to accommodate the load. As 620, control increases the target frequency by a specified offset. The offset may vary based on the target frequency.”)
Masters and Halverson are analogous art. Halverson is cited to teach a similar concept of power management. Halverson teaches detecting the overutilization of a processor and increasing the frequency of the processor to a target frequency when the processor is overutilized. Based on Halverson, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Masters to use a target frequency determine the frequencies of the processors. Furthermore, using a target frequency to set processor frequencies improves on Masters by being able to optimize core usage by addressing overutilization. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification to optimize performance and power and prevent overutilization of the processor.
As to claim 28, Halverson and Masters teach this claim according to the reasoning provided in claims 7 and 14.
Claim(s) 13-14, 17-18, and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masters in view of Schluessler et al. (US 20120324348)
Regarding claim 13, Masters teaches increasing a first operating frequency of one of the processors and decreasing a second operating frequency of a second processor but does not specifically teach that it is to increase performance.
Schluessler teaches wherein increasing a first clock frequency of the processor in the cluster of processors and decreasing a second clock frequency of another processor in the cluster of processors is to increase performance of an application. ([0034], “device that is determined to be a bottleneck for performance, such as throughput performance as viewed from the perspective of an application, is allocated more current/frequency, while the other competing device is capped/limited to ensure the power limit is still met.”)
Masters and Schluessler are analogous art. Schluessler is cited to teach a similar concept of power management. Based on Schluessler, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Masters to increase the performance of an application running on one core by decreasing the power/frequency to another core and reallocation that power to the first core. Furthermore, being able to increase the performance of an application improves on Masters by being able to balance power and performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification to balance power and performance to provide user satisfaction.
Regarding claim 14, Masters teaches increasing a first operating frequency of one of the processors and decreasing a second operating frequency of a second processor but does not specifically teach that it is based on a function performed by another processor.
Schluessler teaches wherein increasing a first operating frequency of the processor in the cluster of processors is based, at least in part, on a function performed by the one processor or more in the cluster of processors, and decreasing a second operating frequency of another processor in the cluster of processors is based, at least in part, on a function performed by another of the one or more processor of the cluster of processors. (Fig. 7 [0035], “Cores 101, 102 receive and process instructions; some of which are offloaded to graphics processor 180 for processing (e.g. CPU cores 101, 102 send a pixel to GPU 180 to be textured, GPU 180 calculates a texture of the pixel to obtain a texel). Therefore, if the CPU cores 101, 102 are overworking (i.e. producing too much work for the GPU 180 to handle at its current performance level), then overall performance from a maximum potential is degraded (the extra performance that the CPU cores 101-102 are utilizing to overproduce could have been allocated to GPU 180. Note that this overproducing scenario potentially occurs even when CPU cores 101, 102 are operating at the same or lower frequency than GPU 180. And inversely, if CPU cores 101, 102 are under-producing (i.e. not generating enough work to keep GPU 180 busy), then once again the maximum potential performance is likely not being achieved. Moreover, the producer-consumer relations may also be view from the other perspective, where CPU cores 101, 102 are to consume graphics output from producer 180 before CPU cores 101, 102 can make further forward progress.”)
Masters and Schluessler are analogous art. Schluessler is cited to teach a similar concept of power management. Based on Schluessler, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Masters based on functions running on the cores by increasing frequency on one core while decreasing it on another core. Based on Schluessler and the KSR rationale of the use of known technique to improve similar devices (methods, or products) in the same way, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Masters to use the functions run on the cores with to determine when to change the frequencies of the cores.
Regarding claim 18, Masters teaches increasing a first operating frequency of one of the processors and decreasing a second operating frequency of a second processor but does not specifically teach that it is based on a workload factor.
Schluessler teaches wherein an increase of the first operating frequency of one of the two or more processors and a decrease of the second operating frequency of another of the two or more processors is based, at least in part, on a workload factor. (claim 5, “increase frequency for the first core and decrease frequency for the second core in response to the first workload being greater than the second workload” where a workload factor is interpreted as one workload being greater than another workload.)
Masters and Schluessler are analogous art. Schluessler is cited to teach a similar concept of power management. Based on Schluessler, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Masters based on workloads running on the cores by increasing frequency on one core while decreasing it on another core. Furthermore, being able to increase the frequency of operation for the larger workload improves on Masters by being able to balance power and performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification to balance power and performance to provide user satisfaction.
Regarding claim 29, Masters teaches increasing a first operating frequency of one of the processors and decreasing a second operating frequency of a second processor but does not specifically teach where two processors concurrently perform a same application.
Schluessler teaches wherein the two or more processors concurrently perform a same application. ([0041], “assume cores 505 and 510 are both CPU cores and are executing related threads (e.g. producer and consumer related threads, such as a main thread of a single application executing on core 505 and a run-ahead helper thread for the single application execution on core 510, where the run-ahead helper thread produces information to be consumed by the main thread).”)
Masters and Schluessler are analogous art. Schluessler is cited to teach a similar concept of power management. Based on Schluessler, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Masters to concurrently run the same application on multiple processors. Furthermore, being able to concurrently run the same application on multiple processors improves on Masters by being able to balance power and performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification to balance power and performance to provide user satisfaction.
As to claim 17, Masters and Schluessler teach this claim according to the reasoning provided in claim 13.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masters in view of Rotem et al. (US 20210018971)
Regarding claim 20, Masters teaches increasing a first operating frequency of one of the processors and decreasing a second operating frequency of a second processor but does not specifically teach using the junction temperature to help to determine the operating frequencies.
Rotem teaches wherein an increase of the first operating frequency of the processor in the cluster of processors and a decrease of the second operating frequency of another processor in the cluster of processors is based, at least in part, on one or more thermal junction temperature values measured on one or more processor in the cluster of processors. ([0028], “As well as controlling power drawn by platform components so that it does not exceed P.sub.SYS, the platform-wide power control unit 110 may ensure proper thermal management of the processing platform 100 to maintain conformity with any power dissipation and junction temperature operating condition limits associated with processing units”)
Masters and Rotem are analogous art. Rotem is cited to teach a similar concept of power management. Masters teaches increasing a frequency of a first core while decreasing the frequency of a second core. Masters teach increasing a frequency of first processor while decreasing the frequency of a second processor. Rotem additionally teaches that the determination of frequency changes can be based on the junction temperature and where one of ordinary skill in the art at the time the invention was filed would understand that using this known technique on similar devices would yield predictable results. Based on Rotem and the KSR rationale of the use of known technique to improve similar devices (methods, or products) in the same way, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Schluessler to use the junction temperature to determine when to change the frequencies of the cores.
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masters in view of Schluessler and Margetts et al. (US 20190065086)
Regarding claim 27, Masters does not teach but Schluessler teaches wherein an increase of a first operating frequency of the processor in the cluster of processors is based, at least in part, on an average total graphics power set by a user for another of the one or more processors in the cluster of processors. ([0058-59], “Although any power or energy limit may be encountered, often a power limit based on electrical and thermal limits for a package including the GPU and CPU (i.e. TDP limit for the package) is utilized. … if a limit has been encountered, then the power and/or performance is balanced to alleviate as much of a bottleneck as possible. Therefore, in flow 725 it's determined if the loaded GPU workload is greater than a workload/activity threshold. If the GPU workload is above the threshold, then in flow 730 a performance limit is imposed on the CPU. In other words, the GPU is being overworked and the CPU's production is capped. As can be seen, one way to alleviate the GPUs workload is to cap CPU production. However, to further alleviate the bottleneck, GPU performance, such as frequency is increased.”)
Masters and Schluessler are analogous art. Schluessler is cited to teach a similar concept of power management. Based on Schluessler, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Masters to increase the performance of an application running on one core by decreasing the power/frequency to another core and reallocation that power to the first core based on graphics power. Furthermore, being able to increase the performance of an application improves on Masters by being able to balance power and performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification to balance power and performance to provide user satisfaction.
Masters and Schluessler teaches increasing a first operating frequency and decreasing a second operating frequency but does not specifically teach but does not teach that it is based on average power consumption set by the user.
Margetts teaches wherein an increase of the first operating frequency of processor in the cluster of processors, at least in part, on an average total graphics power set by a user for another of the one or more processor in the cluster of processors. ([0030], “The average power consumption budget, for example measured as a fixed number of Joules per second (1 J/s=1 Watt), can be set by a user”)
Masters, Schluessler and Margetts are analogous art. Schluessler and Margetts are cited to teach a similar concept of power management. Schluessler teaches increasing a frequency of a GPU while decreasing the frequency of CPU (i.e. using graphics power. Margetts teaches that the average power budget can be set by a user and used by a processor (i.e. the GPU taught by Schluessler) where one of ordinary skill in the art at the time the invention was filed would understand that using this known technique on similar devices would yield predictable results. Based on Margetts and the KSR rationale of the use of known technique to improve similar devices (methods, or products) in the same way, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Masters and Schluessler to use average power set by a user when changing frequencies of the GPU/CPU.
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masters in view of Kumar et al. (US 20160313785)
Regarding claim 30, Masters teaches two or more processors operating at various frequencies but does not specifically mention the two or more processors operating at the same frequency.
Kumar teaches wherein at least one processor and another processor of the two or more processors, operate at the same operating frequency. ([0020], “it may be determined whether an increase in performance is requested. That is, the request may be an identification of a higher performance level (e.g., corresponding to a lower than current P-state such as a request to enter the P0 state from the P1 state). Note also that this determination may also confirm that it is possible to change P-state from the current state. If so, control passes to block 230. At block 230, a determination may be made as to a selection of one or more cores to increase its voltage independently of at least another core (block 230). As examples of this decision, the PCU may determine to increase voltage and associated frequency”, where the cores that increase their frequencies to a P0 state are operating substantially the same frequency, since the frequency and voltage of P0 state are fixed as defined in the ACPI table and would be the same.
Kumar and Masters are analogous art. Kumar is cited to teach a similar concept of power management. Kumar teaches using P-states to control power/performance of the system as well as keeping multiple processors operating at the same level. Based on Kumar, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Masters operate processors at the same frequency in certain situations. Furthermore, being able to increase the frequency of operation for the larger workload improves on Masters by being able to balance power and performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification to balance power and performance to provide user satisfaction.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-30 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHERI L. HARRINGTON whose telephone number is (571)270-0468. The examiner can normally be reached Generally, M-F, 7:30a-4p.
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/CHERI L HARRINGTON/Examiner, Art Unit 2176 April 29, 2026
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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