Prosecution Insights
Last updated: July 17, 2026
Application No. 17/837,732

TECHNOLOGIES FOR THIN FILM RESISTORS IN VIAS

Non-Final OA §103§112
Filed
Jun 10, 2022
Examiner
VALENZUELA, PATRICIA D
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Non-Final)
90%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
647 granted / 717 resolved
+22.2% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
63 currently pending
Career history
794
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
86.7%
+46.7% vs TC avg
§102
4.8%
-35.2% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 717 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claim limitations identified below have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because it uses/they use a generic placeholder “means for” coupled with functional language without reciting sufficient structure to achieve the function. Furthermore, the generic placeholder is not preceded by a structural modifier. Claim 20 claims a device. The claim 20 (and dependent claims 21-23) recite means for means for connecting the first layer to the second layer, wherein the means for connecting the first layer to the second layer has a resistivity that according to the instant application may be implemented in various devices to perform a function. Thus the language “means for" invoke 112(f). Since the claim limitation(s) invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, claim(s) 20-23 have been interpreted to cover the corresponding structure described in the specification [0128-0131] that achieves the claimed function, and equivalents thereof. If applicant does not intend to have the claim limitation(s) treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112 , sixth paragraph, applicant may amend the claim(s) so that it/they will clearly not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, or present a sufficient showing that the claim recites/recite sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-23, 26, 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bartley(USPGPUB DOCUMENT: 20190239358, hereinafter Bartley) in view of Taylor (USPGPUB DOCUMENT: 2005/0266651, hereinafter Taylor). Re claim 1 Bartley discloses in Fig 16/17 a device comprising: a substrate(10) comprising: a first layer(85a/b/c/d/e); a second layer(85a/b/c/d/e); and one or more vias(20) that extend from the first layer(85a/b/c/d/e) to the second layer(85a/b/c/d/e), wherein, for individual vias(20) of the one or more vias(20), a resistor(84) is defined in the corresponding via. Bartley does not disclose a thin-film resistor Taylor disclose a thin-film resistor[0001] It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Taylor to the teachings of Bartley in order to fashioned the resistor for a desired resistance value by manipulating physical properties of the resistor [0001, Taylor]. Re claim 2 Bartley and Taylor disclose the device of claim 1, wherein individual vias(20) of the one or more vias(20) have a height/diameter ratio of at least 8. Re claim 3 Bartley and Taylor disclose the device of claim 1, wherein, for individual vias(20) of the one or more vias(20), the thin-film resistor(84) has a thickness between 20 and 100 nanometers. Re claim 4 Bartley and Taylor disclose the device of claim 1, further comprising a trace on the first layer(85a/b/c/d/e), the trace connecting the thin-film resistor(84)s of two of the one or more vias(20). Re claim 5 Bartley and Taylor disclose the device of claim 1, further comprising: a circuit board coupled to the one or more vias(20) on the first layer(85a/b/c/d/e); and an integrated circuit component coupled to the one or more vias(20) on the second layer(85a/b/c/d/e). Re claim 6 Bartley and Taylor disclose the device of claim 5, wherein the integrated circuit component is a processor. Re claim 7 Bartley and Taylor disclose the device of claim 1, wherein, for individual vias(20) of the one or more vias(20), the thin-film resistor(84) comprises titanium and nitrogen. Re claim 8 Bartley and Taylor disclose the device of claim 1, wherein, for individual vias(20) of the one or more vias(20), the thin-film resistor(84) comprises tantalum and nitrogen. Re claim 9 Bartley and Taylor disclose the device of claim 1, wherein, for individual vias(20) of the one or more vias(20), the thin-film resistor(84) comprises ruthenium and oxygen. Re claim 10 Bartley and Taylor disclose the device of claim 1, wherein, for individual vias(20) of the one or more vias(20), the thin-film resistor(84) comprises aluminum and oxygen. Re claim 11 Bartley and Taylor disclose the device of claim 1, wherein the substrate(10) comprises silicon and oxygen. Re claim 12 Bartley and Taylor disclose the device of claim 1, wherein the substrate(10) comprises silicon. Re claim 13 Bartley discloses in Fig 16/17 a device comprising: a substrate(10) comprising: a first layer(85a/b/c/d/e);a second layer(85a/b/c/d/e); and one or more vias(20) that extend from the first layer(85a/b/c/d/e) to the second layer(85a/b/c/d/e), wherein, for individual vias(20) of the one or more vias(20), a resistive layer(85a/b/c/d/e) is defined in the corresponding via. Bartley does not disclose a resistive layer(85a/b/c/d/e) having a resistivity between 1 and 1,000 microohm-centimeters Taylor disclose a resistive layer having a resistivity[0001] It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Taylor to the teachings of Bartley in order to fashioned the resistor for a desired resistance value by manipulating physical properties of the resistor [0001, Taylor]. Bartley and Taylor do not disclose a resistive layer(85a/b/c/d/e) having a resistivity between 1 and 1,000 microohm-centimeters Although the combination of Bartley and Taylor do not disclose a resistive layer(85a/b/c/d/e) having a resistivity between 1 and 1,000 microohm-centimeters, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to disclose a resistive layer(85a/b/c/d/e) having a resistivity between 1 and 1,000 microohm-centimeters as the result effective variable meet the claims as varied through routine experimentation in order to optimize the functionality of the device and when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art to optimize the properties of the resistor [0001, Taylor]. See MPEP 2144.05. Further, the specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) Re claim 14 Bartley and Taylor disclose the device of claim 13, wherein individual vias(20) of the one or more vias(20) have a height/diameter ratio of at least 8. Re claim 15 Bartley and Taylor disclose the device of claim 13, wherein, for individual vias(20) of the one or more vias(20), the resistive layer(85a/b/c/d/e) has a thickness between 20 and 100 nanometers. Re claim 16 Bartley and Taylor disclose the device of claim 13, further comprising: a circuit board coupled to the one or more vias(20) on the first layer(85a/b/c/d/e); and an integrated circuit component coupled to the one or more vias(20) on the second layer(85a/b/c/d/e). Re claim 17 Bartley and Taylor disclose the device of claim 13, wherein, for individual vias(20) of the one or more vias(20), the resistive layer(85a/b/c/d/e) comprises titanium and nitrogen. Re claim 18 Bartley and Taylor disclose the device of claim 13, wherein, for individual vias(20) of the one or more vias(20), the resistive layer(85a/b/c/d/e) comprises tantalum and nitrogen. Re claim 19 Bartley and Taylor disclose the device of claim 13, wherein the substrate(10) comprises silicon and oxygen. Re claim 20 Bartley discloses in Fig 16/17 a device comprising: a substrate(10) comprising: a first layer(85a/b/c/d/e);a second layer(85a/b/c/d/e); and means for(20) connecting the first layer(85a/b/c/d/e) to the second layer(85a/b/c/d/e), wherein the means for(20) connecting the first layer(85a/b/c/d/e) to the second layer(85a/b/c/d/e) has a resistivity. Bartley does not disclose wherein the means for(20) connecting the first layer(85a/b/c/d/e) to the second layer(85a/b/c/d/e) has a resistivity between 1 and 1,000 microohm- centimeters Taylor disclose wherein the means for(20) connecting the first layer(85a/b/c/d/e) to the second layer(85a/b/c/d/e) has a resistivity [0001] It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Taylor to the teachings of Bartley in order to fashioned the resistor for a desired resistance value by manipulating physical properties of the resistor [0001, Taylor]. Bartley and Taylor do not disclose wherein the means for(20) connecting the first layer(85a/b/c/d/e) to the second layer(85a/b/c/d/e) has a resistivity between 1 and 1,000 microohm- centimeters Although the combination of Bartley and Taylor do not disclose wherein the means for(20) connecting the first layer(85a/b/c/d/e) to the second layer(85a/b/c/d/e) has a resistivity between 1 and 1,000 microohm- centimeters, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to disclose wherein the means for(20) connecting the first layer(85a/b/c/d/e) to the second layer(85a/b/c/d/e) has a resistivity between 1 and 1,000 microohm- centimeters as the result effective variable meet the claims as varied through routine experimentation in order to optimize the functionality of the device and when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art to optimize the properties of the resistor [0001, Taylor]. See MPEP 2144.05. Further, the specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) Re claim 21 Bartley and Taylor disclose the device of claim 20, wherein the means for(20) connecting the first layer(85a/b/c/d/e) to the second layer(85a/b/c/d/e) has a height/diameter ratio of at least 8. Re claim 22 Bartley and Taylor disclose the device of claim 20, wherein the means for(20) connecting the first layer(85a/b/c/d/e) to the second layer(85a/b/c/d/e) has a thickness between 20 and 100 nanometers. Re claim 23 Bartley and Taylor disclose the device of claim 20, further comprising a trace on the first layer(85a/b/c/d/e), the trace connecting the means for(20) connecting the first layer(85a/b/c/d/e) to the second layer(85a/b/c/d/e). Re claim 26 Bartley and Taylor disclose the device of claim 1, wherein the substrate(10) comprises a glass interposer, wherein the one or more vias(20) comprise one or more through-glass vias(20). Re claim 27 Bartley and Taylor disclose the device of claim 1, wherein, for individual vias(20) of the one or more vias(20), the corresponding via further comprises a dielectric plug filler positioned within the corresponding via inward of the thin-film resistor(84). Response to Arguments Applicant’s arguments with respect to 103 rejections of claim(s) 1 -23 & 26, 27 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Jun 10, 2022
Application Filed
Feb 10, 2023
Response after Non-Final Action
Oct 08, 2025
Non-Final Rejection mailed — §103, §112
Dec 23, 2025
Interview Requested
Jan 07, 2026
Applicant Interview (Telephonic)
Jan 08, 2026
Response Filed
Mar 04, 2026
Examiner Interview Summary
Apr 08, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

2-3
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.1%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 717 resolved cases by this examiner. Grant probability derived from career allowance rate.

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