DETAILED ACTION
Response to Arguments
Applicant's arguments filed 6/30/25 regarding the rejection of amended claims 1 and 10 to incorporate the limitations of cancelled claims 18 and 20 are moot due to the new grounds of rejection presented in this Office action.
However, regarding the statements on p. 12 of the Remarks, regarding asserted unexpected technical advantages, statements regarding unexpected results must be supported by evidence in the record. See MPEP 716.01(c) II.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5-11, 13-15, 17, 19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Noble (U.S. PGPub 2005/0048714) in view of Park (U.S. PGPub 2022/0223604) and Karda (U.S. PGPub 2014/0247674).
Regarding claim 1, Noble teaches a semiconductor device (Fig. 2) comprising a substrate (60, [0039]), a semiconductor pillar including a first sidewall and a second sidewall facing each other (70/72/74, [0039]), a bit line coupled to a lower portion of the semiconductor pillar (50, [0040]), a capacitor coupled to an upper portion of the semiconductor pillar (44, [0039]), a body line coupled to the first sidewall of the semiconductor pillar (76, [0040]) and a vertical word line disposed over the second sidewall of the semiconductor pillar (48, [0040]), wherein the vertical word line and the body line extend in a second direction perpendicular to a first direction, in which the bit line extends (Fig. 2).
Noble does not explicitly teach wherein the bit line is disposed between the substrate and the semiconductor pillar.
Park teaches a semiconductor device (Fig. 22) comprising a substrate (210, [0163]), a semiconductor pillar including a first sidewall and a second sidewall facing each other (230, [0163], [0166]); a bit line coupled to a lower portion of the semiconductor pillar (220, [[0164]); a capacitor coupled to an upper portion of the semiconductor pillar (280, [0176]-[0177]); and a word line coupled to the sidewall of the semiconductor pillar (240A, 242A, [0170]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Park with Noble such that the bit line is disposed between the substrate and the semiconductor pillar for the purpose of avoiding body threshold voltage instabilities in a memory structure with the bit line disposed between the substrate and the semiconductor pillar (Noble, [0040]) because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art the time of the invention. See MPEP 2143(I)A.
The combination of Noble and Park does not explicitly teach wherein a width of the vertical word line is greater than a width of the body line in the first direction.
Karda teaches wherein the thickness of the word lines affects the electrical and mechanical properties of the word lines ([0042]) and wherein the thickness of the body lines affects the resistance and mechanical properties of the body lines ([0042]). Therefore, the thickness (width) of the word lines and the body lines are result effective variables. Mere optimization of a result effective variable is prima facie obvious. See MPEP 2144.05IIB. Additionally, there is no teaching in the specification regarding the width of the word line or the width of the body line or the relative widths other than the depiction in the figures.
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Karda with Noble and Park such that a width of the vertical word line is greater than a width of the body line in the first direction for the purpose of controlling the electrical and mechanical properties of the word line and body line (Karda, [0042]).
Regarding claim 2, the combination of Noble and Park teaches wherein the vertical word line and the body line extend while facing each other with the semiconductor pillar interposed therebetween (Noble, Fig. 2). It would have been obvious to a person of ordinary skill to further combine the teachings of Noble, Park, and Karda for the reasons set forth in the rejection of claim 1.
Regarding claim 3, the combination of Noble, Park, and Karda teaches wherein the body line includes a semiconductor material (Noble, [0040]). It would have been obvious to a person of ordinary skill to further combine the teachings of Noble, Park, and Karda for the reasons set forth in the rejection of claim 1.
Regarding claim 5, the combination of Noble, Park, and Karda teaches wherein the vertical word line has a greater height than the body line (Noble, Fig. 2). It would have been obvious to a person of ordinary skill to further combine the teachings of Noble, Park, and Karda for the reasons set forth in the rejection of claim 1.
Regarding claim 6, the combination of Noble, Park, and Karda teaches a gate dielectric layer between the semiconductor pillar and the vertical word line (Noble, 132, [0040]; Park, 250A, [0183]). It would have been obvious to a person of ordinary skill to further combine the teachings of Noble, Park, and Karda for the reasons set forth in the rejection of claim 1.
Regarding claim 7, the combination of Noble, Park, and Karda teaches a dielectric layer between the bit line and the vertical word line (Noble, Fig. 2, Fig. 25, 134, [0057]). It would have been obvious to a person of ordinary skill to further combine the teachings of Noble, Park, and Karda for the reasons set forth in the rejection of claim 1.
Regarding claim 8, the combination of Noble, Park, and Karda teaches wherein the semiconductor pillar includes monocrystalline silicon (Abstract). It would have been obvious to a person of ordinary skill to further combine the teachings of Noble, Park, and Karda for the reasons set forth in the rejection of claim 1.
Regarding claim 9, the combination of Noble, Park, and Karda teaches wherein a plurality of the semiconductor pillars are disposed in a direction that the bit line extends, the body line is coupled to each of the first sidewalls of the semiconductor pillars, and the vertical word line is disposed over each of the second sidewalls of the semiconductor pillars located (Noble, [0040], Fig. 2), wherein the semiconductor pillars further include a protective layer between the body lines and the vertical word lines (Noble, Fig. 25, 134, [0057]; 126, [0053]). It would have been obvious to a person of ordinary skill to further combine the teachings of Noble, Park, and Karda for the reasons set forth in the rejection of claim 1.
Regarding claim 19, the combination of Noble, Park, and Karda teaches a buffer layer, including a dielectric material, directly contacted to the substrate and the bit line (Park, Fig. 22, 210/212/220, [0164]). It would have been obvious to a person of ordinary skill to further combine the teachings of Noble, Park, and Karda for the reasons set forth in the rejection of claim 1.
Regarding claim 10, Noble teaches a semiconductor device (Fig. 2) comprising a substrate (60, [0039]), a memory cell array including a bit line, a transistor, and a capacitor that are vertically stacked with respect to the peripheral circuit portion (Fig. 2, 50, 46, 44, [0039]-[0040]), wherein the transistor includes a semiconductor pillar disposed between the bit line and the capacitor (70/72/74, [0039]), a body line coupled to a first sidewall of the semiconductor pillar (76, [0040]), and a vertical word line disposed over a second sidewall of the semiconductor pillar (48, [0040]), wherein the vertical word line and the body line extend in a second direction perpendicular to a first direction, in which the bit line extends (Fig. 2).
Noble does not explicitly teach wherein the bit line is disposed between the substrate and the semiconductor pillar.
Park teaches a semiconductor device (Fig. 22) comprising a substrate (210, [0163]), a semiconductor pillar including a first sidewall and a second sidewall facing each other (230, [0163], [0166]); a bit line coupled to a lower portion of the semiconductor pillar (220, [[0164]); a capacitor coupled to an upper portion of the semiconductor pillar (280, [0176]-[0177]); and a word line coupled to the sidewall of the semiconductor pillar (240A, 242A, [0170]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Park with Noble such that the bit line is disposed between the substrate and the semiconductor pillar for the purpose of avoiding body threshold voltage instabilities in a memory structure with the bit line disposed between the substrate and the semiconductor pillar (Noble, [0040]) because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art the time of the invention. See MPEP 2143(I)A.
The combination of Noble and Park does not explicitly teach wherein a width of the vertical word line is greater than a width of the body line in the first direction.
Karda teaches wherein the thickness of the word lines affects the electrical and mechanical properties of the word lines ([0042]) and wherein the thickness of the body lines affects the resistance and mechanical properties of the body lines ([0042]). Therefore, the thickness (width) of the word lines and the body lines are result effective variables. Mere optimization of a result effective variable is prima facie obvious. See MPEP 2144.05IIB. Additionally, there is no teaching in the specification regarding the width of the word line or the width of the body line or the relative widths other than the depiction in the figures.
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Karda with Noble and Park such that a width of the vertical word line is greater than a width of the body line in the first direction for the purpose of controlling the electrical and mechanical properties of the word line and body line (Karda, [0042]).
Regarding claim 11, the combination of Noble, Park, and Karda teaches wherein the vertical word line and the body line extend while facing each other with the semiconductor pillar interposed therebetween (Noble, Fig. 2). It would have been obvious to a person of ordinary skill to further combine the teachings of Noble, Park, and Karda for the reasons set forth in the rejection of claim 10.
Regarding claim 13, the combination of Noble, Park, and Karda teaches wherein the vertical word line has a greater height than the body line (Noble, Fig. 2). It would have been obvious to a person of ordinary skill to further combine the teachings of Noble, Park, and Karda for the reasons set forth in the rejection of claim 10.
Regarding claim 14, the combination of Noble, Park, and Karda teaches a gate dielectric layer between the semiconductor pillar and the vertical word line (Noble, 132, [0040]; Park, 250A, [0183]). It would have been obvious to a person of ordinary skill to further combine the teachings of Noble, Park, and Karda for the reasons set forth in the rejection of claim 10.
Regarding claim 15, the combination of Noble, Park, and Karda teaches wherein the semiconductor pillar includes monocrystalline silicon (Noble, Abstract). It would have been obvious to a person of ordinary skill to further combine the teachings of Noble, Park, and Karda for the reasons set forth in the rejection of claim 10.
Regarding claim 17, the combination of Noble, Park, and Karda teaches wherein a plurality of the semiconductor pillars are disposed in a direction that the bit line extends, the body line is coupled to each of the first sidewalls of the semiconductor pillars, and the vertical word line is disposed over each of the second sidewalls of the semiconductor pillars located (Noble, [0040], Fig. 2), wherein the semiconductor pillars further include a protective layer between the body lines and the vertical word lines (Noble, Fig. 25, 134, [0057]; 126, [0053]). It would have been obvious to a person of ordinary skill to further combine the teachings of Noble, Park, and Karda for the reasons set forth in the rejection of claim 10.
Regarding claim 21, the combination of Noble, Park, and Karda teaches a buffer layer, including a dielectric material, directly contacted to the substrate and the bit line (Park, Fig. 22, 210/212/220, [0164]). It would have been obvious to a person of ordinary skill to further combine the teachings of Noble and Park for the reasons set forth in the rejection of claim 10.
Claims 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Noble (U.S. PGPub 2005/0048714), Park (U.S. PGPub 2022/0223604), and Karda (U.S. PGPub 2014/0247674) and further in view of Liu (U.S. PGPub 2020/0388712).
Regarding claims 4 and 12, the combination of Noble, Park, and Karda does not explicitly teach wherein the body line includes silicon germanium.
Liu teaches a semiconductor device (Fig. 2) comprising a semiconductor pillar (213-1, [0034]), a body line coupled to a sidewall of the pillar ([0035], 211, Fig. 1), where the body line may include silicon germanium ([0036]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Liu with Noble, Park and Karda such that the body line includes silicon germanium because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art the time of the invention. See MPEP 2143(I)A.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Noble (U.S. PGPub 2005/0048714) and Park (U.S. PGPub 2022/0223604) and Karda (U.S. PGPub 2014/0247674) and further in view of Tang (U.S. PGPub 2020/0295008).
Regarding claim 16, the combination of Noble, Park, and Karda does not explicitly teach wherein the peripheral circuit portion is disposed at a lower level than the memory cell array or disposed at a higher level than the memory cell array. Noble teaches forming contacts and wiring to connect the device array to peripheral circuits ([0058]).
Tang teaches connecting a substrate comprising a memory array with peripheral circuitry, wherein the peripheral circuit is disposed at a lower level than the memory cell array (Fig. 36, [0153]-[0154]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Tang with Noble, Park, and Karda such that wherein the peripheral circuit portion is disposed at a lower level than the memory cell array or disposed at a higher level than the memory cell array for the purpose of connecting the device array to the peripheral circuits (Tang, [[0153]).
Conclusion
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/ALIA SABUR/Primary Examiner, Art Unit 2812