Last updated: May 29, 2026

Application No. 17/838,637

DUAL METAL SILICIDE FOR STACKED TRANSISTOR DEVICES

Final Rejection

Filed

Jun 13, 2022

Examiner

MENZ, LAURA MARY

Art Unit

2813

Tech Center

2800 — Semiconductors & Electrical Systems

Assignee

Intel Corporation

OA Round

2 (Final)

Interview Optional

— +8.2% interview lift. Interview already conducted in this application's prosecution history. This examiner has a 87% grant rate with +8.2% interview lift. Since an interview has already been tried, recommend written response with narrowed claims based on precedent claim evolution patterns.

Based on 928 resolved cases, 2023–2026

Examiner Intelligence

MENZ, LAURA MARY View full profile →

Grants 87% — above average

Career Allowance Rate

811 granted / 928 resolved

+19.4% vs TC avg

Moderate +8% lift

Without

With

+8.2%

Interview Lift

resolved cases with interview

Typical timeline

2y 5m

Avg Prosecution

21 currently pending

Career history

964

Total Applications

across all art units

Statute-Specific Performance

§101

2.1%

-37.9% vs TC avg

§103

41.8%

+1.8% vs TC avg

§102

28.2%

-11.8% vs TC avg

§112

2.5%

-37.5% vs TC avg

Black line = Tech Center average estimate • Based on career data from 928 resolved cases

Prosecution Timeline

Show 1 earlier event

Feb 10, 2023

Response after Non-Final Action

Nov 30, 2025

Non-Final Rejection (signed)

Jan 20, 2026

Non-Final Rejection mailed

Mar 30, 2026

Interview Requested

Apr 08, 2026

Examiner Interview Summary

Apr 08, 2026

Applicant Interview (Telephonic)

Apr 15, 2026

Response Filed

May 26, 2026

Final Rejection mailed (current)

Precedent Cases

Applications granted by this same examiner with similar technology

17/708,417

Patent 12642071

SCALABLE ARCHITECTURE FOR MULTI-DIE SEMICONDUCTOR PACKAGES

4y 1m to grant Granted May 26, 2026

18/080,729

Patent 12642137

MULTI-LAYER CHIP ARCHITECTURE AND FABRICATION

3y 5m to grant Granted May 26, 2026

18/096,516

Patent 12642138

Three Dimensional Application-Specific Integrated Circuit Architecture

3y 4m to grant Granted May 26, 2026

18/327,252

Patent 12642144

Multi-Bump Connection to Interconnect Structure and Manufacturing Method Thereof

2y 12m to grant Granted May 26, 2026

18/092,081

Patent 12635579

CHIP PACKAGE STRUCTURES, MANUFACTURING METHODS THEREOF AND ELECTRONIC DEVICES

3y 4m to grant Granted May 19, 2026

Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.

Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4

Expected OA Rounds

87%

Grant Probability

96%

With Interview (+8.2%)

2y 5m (~0m remaining)

Median Time to Grant

Moderate

PTA Risk

Based on 928 resolved cases by this examiner. Grant probability derived from career allowance rate.