DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 1 in the reply filed on 9/16/25 is acknowledged. The traversal is on the ground(s) that all claims read upon Species 1 and it would not be burdensome to examine the additional claims/species. This is not found persuasive because an exhaustive search has been conducted and the most relevant prior art identified; the additional species would require numerous additional burdensome searches to identify the best prior art pertaining to the separate species. However, Applicant is reminded that should future prosecution identify allowable subject matter and such subject matter be properly incorporated into the claims; rejoinder may be possible.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 12-13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al (US 2023/0307296).
1. (Original) An integrated circuit structure, comprising:
a first device (Fig.5N see annotated drawing below (first device) and [0012-0015]) comprising (i) a first source or drain region (Fig.5N (441b/a) and [0032]), (ii) a first source or drain contact (Fig.5N see annotated drawing below (533-Shared Lower S/D contact/ 541-Lower S/D contact) and [0040]) coupled to the first source or drain region (Fig.5N (441b/a) and [0032]), and (iii) a first layer (Fig.5N see annotated drawing below (533-Shared Lower S/D contact / 541-Lower S/D contact-) and [0040]) comprising a first metal [0040- metal adhesion or metal fill] and first one or more semiconductor materials [0040- semiconductor is the silicide liner] between at least a section of the first source or drain region (Fig.5N (441b/a) and [0032]) and the first source or drain contact (Fig.5N see annotated drawing below (533-Shared Lower S/D contact / 541-Lower S/D contact) and [0040- describes the silicide liner, metal adhesion and metal fill but is depicted as a single layer (533) in drawing 5N]); and
a second device (Fig.5N see annotated drawing below (second device) and [0012-0015]) stacked vertically above the first device (Fig.5N see annotated drawing below (first device) and [0012-0015]),
the second device (Fig.5N see annotated drawing below (first device) and [0012-0015]) comprising (i) a second source or drain region (Fig.5N (443b/a) and [0033]), (ii) a second source or drain contact (Fig.5N see annotated drawing below (533- Shared Upper S/D Contact/561- Upper S/D contact ) and [0040]) coupled to the second source or drain region (Fig.5N (443b/a) and [0033]), and (iii) a second layer comprising a second metal [0040- metal adhesion or metal fill] and second one or more semiconductor materials [0040- semiconductor is the silicide liner] between at least a section of the second source or drain region (Fig.5N (443b/a) and [0033]) and the second source or drain contact (Fig.5N see annotated drawing below (533- Shared Upper S/D Contact or 561-Upper S/D contact) and [0040]), wherein the first metal and the second metal are elementally different [0040- teaches the metal adhesion layer (TiN) is of different metals from the metal fill layer (W, Co, Ru)].
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2. (Original) The integrated circuit of claim 1, wherein the second source or drain region (Fig.5N (443b/a) and [0033]) is above the first source or drain region (Fig.5N (441b/a) and [0032]), and wherein the integrated circuit further comprises an isolation region (Figh.5N (442a/b) and [0032-0033] comprising non-conductive material [0032-dielectric] between the second source or drain region (Fig.5N (443b/a) and [0033]) and the first source or drain region (Fig.5N (441b/a) and [0032]).
3. (Original) The integrated circuit of claim 2, wherein the first source or drain contact (Fig.5N(533- Shared Lower S/D contact) and [0040]) and the second source or drain contact (Fig.5N(533- Shared Upper S/D contact) and [0040]) form a continuous contact extending through the isolation region (Fig,5N (533) and [0040]).
4. (Original) The integrated circuit of claim 1, wherein the first one or more semiconductor materials comprise one or both of silicon and germanium, and wherein the second one or more semiconductor materials comprise one or both of silicon and germanium [0040- silicide from silicon].
5. (Original) The integrated circuit of claim 1, wherein the first layer comprises silicide, germanide, and/or germanosilicide of the first metal, and wherein the second layer comprises silicide, germanide, and/or germanosilicide of the second metal [0040- silicide].
12. (Original) The integrated circuit of claim 1, wherein the work function of the first metal is greater than the work function of the second metal [0040-WF of TiN =8.04; W=4.5].
13. (Original) The integrated circuit of claim 1, wherein the first source or drain contact (Fig.5N see annotated drawing below (533-Shared Lower S/D contact/ 541-Lower S/D contact) and [0040]) is above and at least in part aligned with the second source or drain contact (Fig.5N see annotated drawing below (533- Shared Upper S/D Contact/561- Upper S/D contact ), such that an imaginary vertical line passes through both the first source or drain contact (Fig.5N see annotated drawing below (533-Shared Lower S/D contact/ 541-Lower S/D contact) and [0040]) and the second source or drain contact (Fig.5N see annotated drawing below (533- Shared Upper S/D Contact/561- Upper S/D contact) [an imaginary line would pass through].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Xie et al (12142526; 2023/0130305); Lilak et al (US 20200294998); Rachmady et al (US 20230395718; US 20230402513; US 20230402507); Dewey et al (US 20230197569 US 20230197777) teach similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
11/26/25