CTFR 17/838,637 CTFR 74721 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25 AIA Applicant's election with traverse of Species 1 in the reply filed on 9/16/25 is acknowledged. The traversal is on the ground(s) that all claims read upon Species 1 and it would not be burdensome to examine the additional claims/species . This is not found persuasive because an exhaustive search has been conducted and the most relevant prior art identified; the additional species would require numerous additional burdensome searches to identify the best prior art pertaining to the separate species. However, Applicant is reminded that should future prosecution identify allowable subject matter and such subject matter be properly incorporated into the claims; rejoinder may be possible . The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim(s) 1-5, 12-13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al (US 2023/0307296) . 1. (Original) An integrated circuit structure, comprising: a first device (Fig.5N see annotated drawing below (first device) and [0012-0015]) comprising (i) a first source or drain region (Fig.5N (441b/a) and [0032]), (ii) a first source or drain contact (Fig.5N see annotated drawing below (533-Shared Lower S/D contact/ 541-Lower S/D contact) and [0040]) coupled to the first source or drain region (Fig.5N (441b/a) and [0032]), and (iii) a first layer (Fig.5N see annotated drawing below (533-Shared Lower S/D contact / 541-Lower S/D contact-) and [0040]) comprising a first metal [0040- metal adhesion or metal fill] and first one or more semiconductor materials [0040- semiconductor is the silicide liner] between at least a section of the first source or drain region (Fig.5N (441b/a) and [0032]) and the first source or drain contact (Fig.5N see annotated drawing below (533-Shared Lower S/D contact / 541-Lower S/D contact) and [0040- describes the silicide liner, metal adhesion and metal fill but is depicted as a single layer (533) in drawing 5N]); and a second device (Fig.5N see annotated drawing below (second device) and [0012-0015]) stacked vertically above the first device (Fig.5N see annotated drawing below (first device) and [0012-0015]), the second device (Fig.5N see annotated drawing below (first device) and [0012-0015]) comprising (i) a second source or drain region (Fig.5N (443b/a) and [0033]), (ii) a second source or drain contact (Fig.5N see annotated drawing below (533- Shared Upper S/D Contact/561- Upper S/D contact ) and [0040]) coupled to the second source or drain region (Fig.5N (443b/a) and [0033]), and (iii) a second layer comprising a second metal [0040- metal adhesion or metal fill] and second one or more semiconductor materials [0040- semiconductor is the silicide liner] between at least a section of the second source or drain region (Fig.5N (443b/a) and [0033]) and the second source or drain contact (Fig.5N see annotated drawing below (533- Shared Upper S/D Contact or 561-Upper S/D contact) and [0040]), wherein the first metal and the second metal are elementally different [0040- teaches the metal adhesion layer (TiN) is of different metals from the metal fill layer (W, Co, Ru)]. PNG media_image1.png 609 783 media_image1.png Greyscale 2. (Original) The integrated circuit of claim 1, wherein the second source or drain region (Fig.5N (443b/a) and [0033]) is above the first source or drain region (Fig.5N (441b/a) and [0032]), and wherein the integrated circuit further comprises an isolation region (Figh.5N (442a/b) and [0032-0033] comprising non-conductive material [0032-dielectric] between the second source or drain region (Fig.5N (443b/a) and [0033]) and the first source or drain region (Fig.5N (441b/a) and [0032]). 3. (Original) The integrated circuit of claim 2, wherein the first source or drain contact (Fig.5N(533- Shared Lower S/D contact) and [0040]) and the second source or drain contact (Fig.5N(533- Shared Upper S/D contact) and [0040]) form a continuous contact extending through the isolation region (Fig,5N (533) and [0040]). 4. (Original) The integrated circuit of claim 1, wherein the first one or more semiconductor materials comprise one or both of silicon and germanium, and wherein the second one or more semiconductor materials comprise one or both of silicon and germanium [0040- silicide from silicon]. 5. (Original) The integrated circuit of claim 1, wherein the first layer comprises silicide, germanide, and/or germanosilicide of the first metal, and wherein the second layer comprises silicide, germanide, and/or germanosilicide of the second metal [0040- silicide]. 12. (Original) The integrated circuit of claim 1, wherein the work function of the first metal is greater than the work function of the second metal [0040-WF of TiN =8.04; W=4.5]. 13. (Original) The integrated circuit of claim 1, wherein the first source or drain contact (Fig.5N see annotated drawing below (533-Shared Lower S/D contact/ 541-Lower S/D contact) and [0040]) is above and at least in part aligned with the second source or drain contact (Fig.5N see annotated drawing below (533- Shared Upper S/D Contact/561- Upper S/D contact ), such that an imaginary vertical line passes through both the first source or drain contact (Fig.5N see annotated drawing below (533-Shared Lower S/D contact/ 541-Lower S/D contact) and [0040]) and the second source or drain contact (Fig.5N see annotated drawing below (533- Shared Upper S/D Contact/561- Upper S/D contact) [an imaginary line would pass through] . Response to Arguments 07-37 AIA Applicant's arguments filed 4/15/26 have been fully considered but they are not persuasive. Starting with the substance of the rejection- the arguments state, page 9 (bolded for emphasis): “As discussed during the Interview, Xie does not disclose or reasonably suggest having the claimed "first layer comprising a first metal and first one or more semiconductor materials" and the claimed "second layer comprising a second metal and second one or more semiconductor materials" where "the first metal and the second metal are elementally different ." Using different metals f or the claimed first and second layers of the stacked first and second devices, for example, facilitates in reducing contact resistance between the source or drain contact and the corresponding source or drain regions of different types of devices (see [0011] of the instant specification). Furthermore, it is not trivial to arrange the claimed first and second layers for stacked devices. Indeed, Xie includes stacked transistor devices, and performs a contact metallization process to form a source/drain contact (531) for both the stacked devices (see [0040] and Figure 5H of Xie). However, Xie merely states that "the metal deposition includes a silicide liner, such as Ti, Ni, NiPt..." (Id). The silicide liner in Xie would be the same across both devices - Xie does not disclose or suggest using liners having different metals for the top and bottom de vices. This statement is true- Xie does not teach that the top silicide liner has a different metal for the top and bottom devices as the arguments state- however Applicant is reminded that the “name of the game is the claim”. The claim language requires (iii) a first layer comprising a first metal and first one or more semiconductor materials between at least a section of the first source or drain region and the first source or drain contact and " second layer comprising a second metal and second one or more semiconductor materials ". There is no recitation of a first and second silicide layer. The arguments misconstrue the Examiner’s rejection. The Examiner pointed out that both the top and bottom devices include a silicide liner which is relied upon to teach (semiconductor material portion of the claim- this also contains a metal ) but the Examiner also cited in the rejection a metal adhesion layer/ fill layer of Xie which is relied upon also to teach (the first/ second metal portion of the claim) . See the rejection of claim 1 made below: 1. (Original) An integrated circuit structure, comprising: a first device (Fig.5N see annotated drawing below (first device) and [0012-0015]) comprising (i) a first source or drain region (Fig.5N (441b/a) and [0032]), (ii) a first source or drain contact (Fig.5N see annotated drawing below (533-Shared Lower S/D contact/ 541-Lower S/D contact) and [0040]) coupled to the first source or drain region (Fig.5N (441b/a) and [0032]), and (iii) a first layer (Fig.5N see annotated drawing below (533-Shared Lower S/D contact / 541-Lower S/D contact-) and [0040]) comprising a first metal [0040- metal adhesion or metal fill] and first one or more semiconductor materials [0040- semiconductor is the silicide liner] between at least a section of the first source or drain region (Fig.5N (441b/a) and [0032]) and the first source or drain contact (Fig.5N see annotated drawing below (533-Shared Lower S/D contact / 541-Lower S/D contact) and [0040- describes the silicide liner, metal adhesion and metal fill but is depicted as a single layer (533) in drawing 5N]); and a second device (Fig.5N see annotated drawing below (second device) and [0012-0015]) stacked vertically above the first device (Fig.5N see annotated drawing below (first device) and [0012-0015]), the second device (Fig.5N see annotated drawing below (first device) and [0012-0015]) comprising (i) a second source or drain region (Fig.5N (443b/a) and [0033]), (ii) a second source or drain contact (Fig.5N see annotated drawing below (533- Shared Upper S/D Contact/561- Upper S/D contact ) and [0040]) coupled to the second source or drain region (Fig.5N (443b/a) and [0033]), and (iii) a second layer comprising a second metal [0040- metal adhesion or metal fill] and second one or more semiconductor materials [0040- semiconductor is the silicide liner] between at least a section of the second source or drain region (Fig.5N (443b/a) and [0033]) and the second source or drain contact (Fig.5N see annotated drawing below (533- Shared Upper S/D Contact or 561-Upper S/D contact) and [0040]), wherein the first metal and the second metal are elementally different [0040- teaches the metal adhesion layer (TiN) is of different metals from the metal fill layer (W, Co, Ru)]. Xie teaches the silicide layer includes Ni and NiPt [0040]. Xie teaches the metal adhesion comprises TiN [0040] Xie teaches the metal fill comprises W, Co Ru [0040] All of these metal elements are different from each other. The claims do not require the “first and second metals” to be the metal component of a silicide layer . The claim language itself does not require an upper and lower silicide layer having different elemental metals from each other as the arguments purport. The language is broader- it does not require a silicide layer at all. It requires a first and second metal and a first and second semiconductor layer- not explicitly a silicide layer. The Examiner’s rejection relied upon the metal adhesion layer (or fill material) which has a different metal element from that of the silicide layer (TiN-adhesion versus Ni or NiPt- silicide) OR alternatively the silicide layer – Ni/Ni Pt is different from the metal fill (W, Co, Ru)- as the Examiner’s rejection clearly points this out. Xie teaches the silicide layer includes Ni and NiPt [0040]. Xie teaches the metal adhesion comprises TiN [0040] Xie teaches the metal fill comprises W, Co Ru [0040] These are all different metals. Therefore the claim language is fully anticipated. In summary the Examiner does not rely upon the metal component of the silicide liner to the be the only metal element The Examiner interprets the metal and semiconductor layer of Xie to be the metal adhesion OR fill layer and the silicide layer together. There are different elemental metals from the adhesion and fill and silicide layer. This is in harmony with the Applicant’s claim language; Applicant’s arguments are not in such harmony. The Examiner understands what the Applicant is attempting to argue- but such arguments ignore the actual language and breadth of the claim language itself. Moreover, the arguments show the misunderstanding of the election of species requirement. The arguments purport that there is no distinctness between the elected and withdrawn species because the Applicant infers that claim 1 requires a bottom and top silicide layer each with a different metal. This is simply not the case. The claim language requires a first (and second) layer comprising a first metal and first one or more semiconductor materials between at least a section of the first source or drain region and the first source or drain contact. The Examiner understands the search from a silicide/ gemanide layers to be of a separate species and fully stands behind the election of species requirement. The above arguments only further support the Examiner’s finding of distinctness and show how the claims are drawn to a different species requiring a burdensome and second search to address the species which requires a silicide or moreover an gemanide; addressing this different specie/s would require the application of different art. Should future prosecution be pursued- the Examiner suggests that the Applicant make a substantial amendment to the claims and withdrawn claims- should future prosecution identify allowable subject matter and subject matter is properly incorporated into the withdrawn claims rejoinder is likely . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Xie et al (12142526; 2023/0130305); Lilak et al (US 20200294998); Rachmady et al (US 20230395718; US 20230402513; US 20230402507); Dewey et al (US 20230197569 US 20230197777) teach similar structures . THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAURA M MENZ/Primary Examiner, Art Unit 2813 5/20/26 Application/Control Number: 17/838,637 Page 2 Art Unit: 2813 Application/Control Number: 17/838,637 Page 3 Art Unit: 2813 Application/Control Number: 17/838,637 Page 4 Art Unit: 2813 Application/Control Number: 17/838,637 Page 5 Art Unit: 2813 Application/Control Number: 17/838,637 Page 6 Art Unit: 2813 Application/Control Number: 17/838,637 Page 7 Art Unit: 2813 Application/Control Number: 17/838,637 Page 8 Art Unit: 2813 Application/Control Number: 17/838,637 Page 9 Art Unit: 2813
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