DETAILED ACTION
Claims 1-23 are pending in the current application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 1/8/26, with respect to the rejection of claim 1 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Burger et al. (Pub. No. US 2017/0083316 A1) [0037] lines 2-13, [0104] lines 1-12, [0105] lines 1-3, [0116] lines 15-21 and [0117] lines 1-5 which shows that with the full composition of the logical cores includes the assignment and mapping of physical processor cores/computer elements to logical and associated changes to register file mapping between physical and logical/virtual elements where the physical processor elements/computer elements are allocated to virtual/logical element based on criteria which can include a plurality of elements such as distance between physical and logical/virtual elements or assigned based on processor topology information, the information that makes up the organization and structure of the processor unit and viewed as including register file information seen as type of physical proximity as well thus during full configuration, allocation, mapping between physical and logical compute elements would take into account a physical proximity based on topology of physical compute elements and associated register file to perform register mapping where in light of the teachings of Chaitin Col. 4 lines 49-61 and Col. 8 lines 23-34 shows the specifics of mapping a number virtual registers to a physical registers files and thus together shows the specifics of mapping a number virtual registers to a physical registers files distributed wherein mapping is based on physical proximity of physical register file, within the plurality of physical register files, to compute elements that access the physical register file
Applicant's arguments filed 1/8/26 have been fully considered but they are not persuasive.
Applicant argues that the cited prior art does not disclose (Argument 1; Remarks pg. 10 lines 19-21) map a virtual register to at least two physical registers.
With respect to applicant’s argument examiner respectfully disagrees as the teachings of Udayakumaran [0022] lines 3-6 shows as part of register allocation/mapping being able to assign/map one or more/viewed as including two physical registers to a single vector virtual register thus having a single vector virtual register assigned/mapped/allocated to one or more vector physical registers thus being able to map/allocate/assign the virtual register to at least two physical registers.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7-10 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Patent No. US 8,949,806 B1) in view of Chaitin (Patent No. 4,571,678) and further in view of in view of Burger et al. (Pub. No. US 2017/0083316 A1).
As to claims 1 and 22, Lee discloses a processor-implemented method for task processing comprising: accessing a two-dimensional (2D) array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements (Lee Col. 4 lines 38-44, Col. 5 lines 10-17 and Col. 6 lines 6-11; which shows a two dimensional array made of tiles that can include processor/compute elements that are connect to each other/couple to its neighboring compute elements, where the tiles/processor/computer element are designated to be executed by a compiler and thus viewed as know to a compiler );
controlling the array of compute elements on a cycle-by-cycle basis, wherein the controlling is enabled by a stream of wide control words generated by the compiler (Lee Col. 1 line 62- Col. 2 line 2, Col. 4 lines 7-10, Col. 6 lines 6-11 and lines 25-28, Col. 7 line 66- Col. 8 line 3 and Col. 9 lines 1-21; which shows the compiler is able to generate and emit specific code sequence used to control the processor/compute elements of the array, where the processors/compute elements can execute the very long instruction words and thus viewed as wide words where the control of the processor/computer elements of the way can be fine grained done every cycle thus viewed as on a cycle by cycle basis);
executing operations contained in the control words, wherein the operations are enabled by at least one of the plurality of distributed physical register files (Lee Col. 5 lines 10-21 and Col. 9 lines 14-54; which shows to execute each execution unit, viewed as the instruction sequence including code word generated by the compiler, where the code resources including registers, where each tile includes its own register file thus viewed as distributed among the tiles, are pooled together to execute one execution unit at a time, thus viewed as executing the operations contained in the control words, enabled by at least one of the plurality of distributed physical register files).
Lee does not specifically disclose mapping a number of virtual registers to a plurality of physical register files distributed among one or more of the compute elements, wherein the mapping is performed by the compiler.
However, Chaitin discloses mapping a number of virtual registers to a plurality of physical register files distributed among one or more of the compute elements, wherein the mapping is performed by the compiler (Chaitin Col. 4 lines 49-61 and Col. 8 lines 23-34; which shows as part of a register allocation phase that is performed by a compiler, being able to map the plurality of virtual/symbolic registers to the plurality of physical/actual present registers).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chitin showing the specifics of the use of virtual registers to perform operations, into the execution of operations of Lee for the purpose of solving problems with register allocation tied to performing operations, as taught by Chaitin Col. Col. 3 lines 6-9 and Col. 4 lines 49-61.
Lee as modified by Chitin do not specifics disclose wherein the mapping is based on physical proximity of a physical register file, within the plurality of physical register files, to compute elements that access the physical register file.
However, Burger discloses wherein the mapping is based on physical proximity of a physical register file, within the plurality of physical register files, to compute elements that access the physical register file (Burger [0037] lines 2-13, [0104] lines 1-12, [0105] lines 1-3, [0116] lines 15-21 and [0117] lines 1-5; which shows that with the full composition of the logical core includes the assignment and mapping of physical processor cores/computer elements to logical and associated changes to register file mapping between physical and logical/virtual elements where the physical processor elements/compute elements are allocated to virtual/logical element based on criteria which can include a plurality of elements such as distance between physical and logical/virtual elements or assigned based on processor topology/relationship information, the information that makes up the organization and structure of the processor unit and viewed as including register file information seen as type of physical proximity as well thus during full configuration, allocation, mapping between physical and logical compute elements would take into account a physical proximity based on topology/relationship of physical compute elements and associated register file to perform register mapping and thus viewed as showing that mapping can be based on physical proximity of a physical register file, within the plurality of physical register files, to compute elements that access the physical register file)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Burger showing the specifics of taking addition processor topology criteria into account with assigning and mapping information between physical and logical elements, into the mapping of virtual register to physical registers of Lee as modified by Chitin for the purpose of increasing the adaptability of mapping to take into account addition context data when mapping between logical/virtual and physical elements, as taught by Burger [0117] lines 1-5.
As to claim 2, Lee does not specifically disclose, however, Chaitin discloses wherein the virtual registers are represented by the compiler (Chaitin Col. 4 lines 49-61 and Col. 8 lines 35-38; which shows the use of virtual/symbolic register as part of register allocation, where the compiler is used in the allocation and thus viewed as a form of the virtual register being represented by the compiler).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chitin showing the specifics of the use of virtual registers to perform operations, into the execution of operations of Lee for the purpose of solving problems with register allocation tied to performing operations, as taught by Chaitin Col. Col. 3 lines 6-9 and Col. 4 lines 49-61.
As to claim 7, Lee does not specifically disclose, however, Chaitin discloses wherein the number of virtual registers is greater than a number of physical registers (Chaitin Col. 4 lines 49-55; which shows the unlimited number of symbolic registers and thus being greater that the 32 physical/present registers).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chitin showing the specifics of the use of virtual registers to perform operations, into the execution of operations of Lee for the purpose of solving problems with register allocation tied to performing operations, as taught by Chaitin Col. Col. 3 lines 6-9 and Col. 4 lines 49-61.
As to claim 8 Lee does not specifically disclose, however, Chaitin discloses wherein the mapping of the virtual registers includes renaming by the compiler (Chaitin Col. 4 lines 49-61 and Col. 16 lines 14-60; which shows though its example code that as part of register mapping/allocation can include associated renaming actions, that can include the mapping/allocation of the virtual registers ).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chitin showing the specifics of the use of virtual registers to perform operations, into the execution of operations of Lee for the purpose of solving problems with register allocation tied to performing operations, as taught by Chaitin Col. Col. 3 lines 6-9 and Col. 4 lines 49-61.
As to claim 9, Lee discloses wherein the renaming by the compiler enables distributed execution of operations (Lee Col. 4 lines 7-11 and Col. 9 lines 25-36 and 55-58; which shows as part of the mapping operations performed being able to distribute/assign instructions to individual cores/elements where instructions are execute and the processor core of the tiled element).
As to claim 10, Lee discloses wherein the distributed execution of operations occurs in two or more compute elements within the array of compute elements (Lee Col. 4 lines 7-11, Col. 5 lines 10-22, and line 55- Col. 6 lines 1 and Col. 9 lines 25-36 and 55-58; which shows being able to distribute/assign instructions to individual cores/elements where instructions are execute and the processor core of the tiled element, viewed as distribute among the plurality/two or more of compute elements of the array).
As to claim 23, Lee discloses a computer system for task processing comprising: a memory which stores instructions; one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to (Lee Col. 5 lines 55-63)
The remaining limitation of the claim are comparable to claim 1 above and rejected under the same reasoning.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, Chaitin and Burger as applied to claim 2 above, and further in view of Goebel (Patent No. 5,987,259).
As to claim 3, Lee as modified by Chaitin and Burger do not specifically disclose wherein a number of physical registers is greater than the number of virtual registers.
However, Goebel disclose wherein a number of physical registers is greater than the number of virtual registers (Goebel Col. 1 lines 33-37; which shows the specific situations where the number of virtual registers is less than the number of physical registers).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Goebel showing the specifics of the use of the number of physical registers being greater than virtual registers, into the use of physical and virtual registers in Lee as modified by Chaitin and Burger for the purpose increasing the ease in determining how to assign the virtual registers to the physical registers, as taught by Goebel Col. 1 lines 33-37.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Chaitin, Burger and Goebel as applied to claim 3 above, and further in view of Udayakumaran et al. (Pub. No. US 2015/0193224 A1)
As to claim 4, Lee as modified by Chaitin, Burger and Goebel do not specifically disclose wherein at least one of the virtual registers is mapped to at least two physical registers.
However, Udayakumaran discloses wherein at least one of the virtual registers is mapped to at least two physical registers (Udayakumaran [0022] lines 3-6; which shows as part of register allocation/mapping being able to assign/map two or more physical registers to a virtual register).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Udayakumaran showing the specifics of the mapping of a virtual register to at least two physical registers, into the mapping of physical and virtual registers in Lee as modified by Chaitin, Burger and Goebel for the purpose improving register allocation to reduce spilling, as taught by Udayakumaran [0007] lines 7-10 and [0022] lines 3-6.
As to claim 5, Lee discloses wherein the at least two physical registers are implemented in separate compute elements within the array of compute elements (Lee Col. 5 lines 10-22; which shows that each tile in the array includes computer processor/computer element where each tile includes its own register thus viewed as having at least two registers implemented in separate compute elements within the array of compute elements and in light of the teachings of Udayakumaran above showing the specifics of the two physical registers would together show wherein the at least two physical registers are implemented in separate compute elements within the array of compute elements).
As to claim 6, Lee discloses wherein the implementation in separate compute elements enables parallel operation processing (Lee Col. 5 lines 10-22, and line 55- Col. 6 lines 1 and Col. 9 lines 1-5 and lines 25-36; which shows the implementation of the plurality of computer elements each with its own register and with the implementation shows is able to perform parallel operation processing ).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Chaitin and Burger as applied to claim 8 above, and further in view of Comparan et al. (Pub. No. US 2014/0281402 A1)
As to claim 11, Lee as modified by Chaitin and Burger do not specifically disclose wherein the renaming by the compilers is based on a table of register files.
However, Comparan discloses wherein the renaming by the compilers is based on a table of register files (Comparan [0066] lines 10-16 and [0069] lines 1-13; which shows that renaming of register is done by the compiler based on check a map tables of register files).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Comparan showing the specifics renaming registers, into the use of physical and virtual registers in Lee as modified by Chaitin and Burger for the purpose increasing consistency in renaming registers by additional checking and consulting of table for mapped names as part of renaming, as taught by Comparan [0069] lines 1-13.
As to claim 12, Lee as modified by Chaitin and Burger do not specifically disclose, however, Comparan discloses wherein the renaming enables the compiler to orchestrate execution of operations using the physical register files (Comparan [0066] lines 10-16 and [0069] lines 1-13; which shows the mapping of the logical/virtual registers to physical registers and their renaming to the physical register files and thus in light of the teachings of Lee above showing the execution of operations using the register files can together be viewed as showing wherein the renaming enables the compiler to orchestrate execution of operations using the physical register files).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Comparan showing the specifics renaming registers, into the use of physical and virtual registers in Lee as modified by Chaitin and Burger for the purpose increasing consistency in renaming registers by additional checking and consulting of table for mapped names as part of renaming, as taught by Comparan [0069] lines 1-13.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Chaitin and Burger as applied to claim 1 above, and further in view of Felch (Pub. No. US 2014/0281366 A1)
As to claim 13, Lee as modified by Chaitin and Burger do not specifically disclose wherein each of the physical register files comprises a memory element with two read ports and one write port (2R 1 W).
However, Felch discloses wherein each of the physical register files comprises a memory element with two read ports and one write port (2R 1 W) (Felch [0058] lines 1-11; which shows the specific of a register file having a memory element with two read ports and one write port, where the specifics of physical register files are seen disclosed in the teachings of Chaitin above).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Felch showing the specifics of register files with two read and one write port, into the register files of Lee as modified by Chaitin and Burger for the purpose of increasing the speed of processing by allowing for concurrent execution through the two read ports, as taught by Felch [0058] lines 1-11.
As to claim 14, Lee discloses wherein a plurality of 2R1W physical register files is distributed throughout the array (Lee Col. 5 lines 10-22; which shows that each tile in the array includes computer processor/computer element where each tile includes its own register thus viewed as having the register files distributed throughout the array, that in light of the teachings of Felch above can be viewed as including the specifics of the 2R1W physical register files).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, Chaitin, Burger and Felch as applied to claim 13 above, and further in view of Gschwind et al. (Pub. No. US 2017/0242796 A1)
As to claim 15, Lee as modified by Chaitin, Burger and Felch do not specifically disclose wherein the 2R1W physical register files effectively provide 256-bit reads and 128-bit writes per cycle.
However, Gschwind discloses wherein the 2R1W physical register files effectively provide 256-bit reads and 128-bit writes per cycle (Gschwind [0039] lines 1-6 and [0103] lines 1-4; which shows the specifics of the ports for a memory/cache being a 265 b/bit for read and 128 b/bit port for write thus viewed as being able to provide 256-bit reads and 128-bit writes per cycle where the specifics of the 2R1W physical register files with ports is seen disclosed in Felch above).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Gschwind showing the specifics of 256 bit read port and 128 bit write port, into the read and write port of register files of Lee as modified by Chaitin, Burger and Felch for the purpose of showing and substituting the type of read and write ports to ports that can provide as specific amount of data based on their size, as taught by Gschwind [0039] lines 1-6 and [0103] lines 1-4.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Chaitin and Burger as applied to claim 1 above, and further in view of Tao (Patent No. 10,606,603 B1)
As to claim 16, Lee as modified by Chaitin and Burger do not specifically disclose further comprising enabling a broadcast write operation to two or more of the physical register files.
However, Tao discloses further comprising enabling a broadcast write operation to two or more of the physical register files (Tao Col. 9 lines 13-18; which shows an instruction write back stage that broadcast the results generated by a unit to all structures waiting for the instruction results, viewed as a type of broadcast write operation including to register files, which in light of the teachings of Chaitin above can be viewed as to two or more physical register files).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Tao showing the specifics broadcasting instructions to register files, into the register files of Lee as modified by Chaitin and Burger for the purpose improving the efficiency of executing instructions by determining and controlling what elements are affected by data that is executed, as taught by Tao Col. 2 lines 18-23 and Col. 9 lines 13-18.
As to claim 17, Lee discloses wherein each of the two or more physical register files is distributed in a compute element of the array of compute elements (Lee Col. 5 lines 10-22; which shows that each tile in the array includes computer processor/computer element where each tile includes its own register thus viewed as having the register files distributed throughout the array, the specifics of the physical register files is seen specifically disclosed in the teachings of Chaitin above).
Claim 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Chaitin and Burger as applied to claim 1 above, and further in view of Huynh et al. (Patent No. US 11,232,016 B1)
As to claim 18, Lee as modified by Chaitin and Burger do no specifically disclose wherein the compiler maps machine learning functionality to the array of compute elements.
However, Huynh discloses wherein the compiler maps machine learning functionality to the array of compute elements (Huynh Col. 12 lines 49-52; which shows the compiler is able to assign/map operations/functions of the neural network, viewed as machine learning to various available processing engines/compute elements, that in light of the teachings of Lee above can be viewed as the specifics of the array of compute elements).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Huynh showing the specifics of the compiler assigning specific operations of a neural network to processing elements of a plurality of processing elements, into the array of computer elements of Lee as modified by Chaitin and Burger for the purpose of increasing the adaptability of the system be being able to determine and assign additional neural network operations to be performed by the processing/compute elements of the system, as taught by Huynh Col. 12 lines 49-52 .
As to claim 19, Lee as modified by Chaitin and Burger do not specifically disclose, however, Huynh discloses wherein the machine learning functionality includes a neural network implementation (Huynh Col. 12 lines 49-52; which shows the functionality/operations being assigned are for a neural network).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Huynh showing the specifics of the compiler assigning specific operations of a neural network to processing elements of a plurality of processing elements, into the array of computer elements of Lee as modified by Chaitin and Burger for the purpose of increasing the adaptability of the system be being able to determine and assign additional neural network operations to be performed by the processing/compute elements of the system, as taught by Huynh Col. 12 lines 49-52.
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Chaitin and Burger as applied to claim 1 above, and further in view of Rakib et al. (Pub. No. US 2010/0281192 A1)
As to claim 20, Lee as modified by Chaitin and Burger do not specifically disclose wherein the stream of wide control words comprises variable length control words generated by the compiler.
However, Rakib discloses wherein the stream of wide control words comprises variable length control words generated by the compiler (Rakib [0053] lines 7-15; which shows the specifics that variable long instruction/control words can be variable length, and thus in light of the teachings of Lee above showing the specifics of how the compiler is used to generate the stream of wide control words/VLIW, would together be viewed as showing wherein the stream of wide control words comprises variable length control words generated by the compiler).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Rakib showing the specifics a variable length very long instruction word, into the very long instruction word generation of Lee as modified by Chaitan and Burger for the purpose increasing efficiency of resource usage by having an adaptable length word thus saving resources/space when less length in needed, as taught by Rakib [0053] lines 7-15.
As to claim 21, Lee discloses wherein the stream of wide, variable length, control words generated by the compiler provides direct, fine-grained control of the 2D array of compute elements (Lee Col. 1 line 62- Col. 2 line 2, Col. 4 lines 7-10, Col. 6 lines 6-11 and lines 25-28, Col. 7 line 66- Col. 8 line 3 and Col. 9 lines 1-21; which shows the stream a very long control/instructions words allow for fine-grained/direct control in the multicore processor architectures, viewed as the 2D array of computer elements, where the specifics of variable length control words is seen specifically disclosed in the teachings of Rakib above).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADFORD F WHEATON whose telephone number is (571)270-1779. The examiner can normally be reached Monday-Friday 8:00-5:00 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chat Do can be reached at 571-272-3721. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRADFORD F WHEATON/Examiner, Art Unit 2193