Prosecution Insights
Prosecution Insights
10 pending office actions • 2 art units • 4 examiners • 0 of 10 (0%) have an AI response strategy ready • 4 patents granted in the last 365 days
Based on the USPTO statutory response window for each pending office action. 6 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 6 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 4 (40%) |
| Multi-statute (no §101) | 6 (60%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| HUISMAN, DAVID J | 6 | 57.9% | +33.7% |
| DOMAN, SHAWN | 2 | 64.9% | +26.5% |
| ALCANTARA-RAMOS, EMILIO | 1 | 50.0% | +100.0% |
| KIM, SISLEY NAHYUN | 1 | 89.0% | +15.8% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17526003 | HIGHLY PARALLEL PROCESSING ARCHITECTURE WITH COMPILER | KIM, SISLEY NAHYUN | 16d overdue |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 6 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18195407 | PARALLEL PROCESSING OF MULTIPLE LOOPS WITH LOADS AND STORES | HUISMAN, DAVID J | 8d overdue |
| 18239770 | PARALLEL PROCESSING ARCHITECTURE WITH MEMORY BLOCK TRANSFERS | HUISMAN, DAVID J | 3d overdue |
| 18388875 | PARALLEL PROCESSING WITH SWITCH BLOCK EXECUTION | HUISMAN, DAVID J | 14d |
| 19053495 | COMPILER GENERATED HYPERBLOCKS IN A PARALLEL ARCHITECTURE WITH COMPUTE SLICES | DOMAN, SHAWN | — |
| 18826260 | SEMANTIC ORDERING FOR PARALLEL ARCHITECTURE WITH COMPUTE SLICES | ALCANTARA-RAMOS, EMILIO | — |
| 17465949 | HIGHLY PARALLEL PROCESSING ARCHITECTURE WITH SHALLOW PIPELINE | HUISMAN, DAVID J | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18220331 | PARALLEL PROCESSING ARCHITECTURE WITH COUNTDOWN TAGGING | HUISMAN, DAVID J | 74d overdue |
| 18236442 | PARALLEL PROCESSING ARCHITECTURE WITH BIN PACKING | HUISMAN, DAVID J | 17d overdue |
| 17526003 | HIGHLY PARALLEL PROCESSING ARCHITECTURE WITH COMPILER | KIM, SISLEY NAHYUN | 16d overdue |
| 18195407 | PARALLEL PROCESSING OF MULTIPLE LOOPS WITH LOADS AND STORES | HUISMAN, DAVID J | 8d overdue |
| 18239770 | PARALLEL PROCESSING ARCHITECTURE WITH MEMORY BLOCK TRANSFERS | HUISMAN, DAVID J | 3d overdue |
| 18388875 | PARALLEL PROCESSING WITH SWITCH BLOCK EXECUTION | HUISMAN, DAVID J | 14d |
| 19053495 | COMPILER GENERATED HYPERBLOCKS IN A PARALLEL ARCHITECTURE WITH COMPUTE SLICES | DOMAN, SHAWN | — |
| 18826260 | SEMANTIC ORDERING FOR PARALLEL ARCHITECTURE WITH COMPUTE SLICES | ALCANTARA-RAMOS, EMILIO | — |
| Art Unit | Apps |
|---|---|
| 2183 | 8 |
| 2196 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 19053495 | COMPILER GENERATED HYPERBLOCKS IN A PARALLEL ARCHITECTURE WITH COMPUTE SLICES | DOMAN, SHAWN | — | §102§103§112 | Non-Final OA | — | Pending | Feb 14, 2025 |
| 18826260 | SEMANTIC ORDERING FOR PARALLEL ARCHITECTURE WITH COMPUTE SLICES | ALCANTARA-RAMOS, EMILIO | 2183 | §103§112 | Final Rejection | — | Pending | Sep 06, 2024 |
| 18388875 | PARALLEL PROCESSING WITH SWITCH BLOCK EXECUTION | HUISMAN, DAVID J | 2183 | §103§112 | Non-Final OA | 14d | Pending | Nov 13, 2023 |
| 18239770 | PARALLEL PROCESSING ARCHITECTURE WITH MEMORY BLOCK TRANSFERS | HUISMAN, DAVID J | 2183 | §102§103§112 | Non-Final OA | 3d overdue | Pending | Aug 30, 2023 |
| 18236442 | PARALLEL PROCESSING ARCHITECTURE WITH BIN PACKING | HUISMAN, DAVID J | 2183 | §103 | Non-Final OA | 17d overdue | Pending | Aug 22, 2023 |
| 18220331 | PARALLEL PROCESSING ARCHITECTURE WITH COUNTDOWN TAGGING | HUISMAN, DAVID J | 2183 | §103 | Final Rejection | 74d overdue | Pending | Jul 11, 2023 |
| 18195407 | PARALLEL PROCESSING OF MULTIPLE LOOPS WITH LOADS AND STORES | HUISMAN, DAVID J | 2183 | §103§112 | Non-Final OA | 8d overdue | Pending | May 10, 2023 |
| 17551276 | HIGHLY PARALLEL PROCESSING ARCHITECTURE USING DUAL BRANCH EXECUTION | DOMAN, SHAWN | 2183 | §103 | Non-Final OA | — | Pending | Dec 15, 2021 |
| 17526003 | HIGHLY PARALLEL PROCESSING ARCHITECTURE WITH COMPILER | KIM, SISLEY NAHYUN | 2196 | §103 | Non-Final OA | 16d overdue | Pending | Nov 15, 2021 |
| 17465949 | HIGHLY PARALLEL PROCESSING ARCHITECTURE WITH SHALLOW PIPELINE | HUISMAN, DAVID J | 2183 | §103§112 | Final Rejection | — | Pending | Sep 03, 2021 |
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