Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. In particular, claim 15 recites the feature: “wherein a top of the metal gate stack is formed to be wider than a top of the dummy gate stack.” However, the specification states in para. [0002] that “It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.” Therefore, the features of claim 15 are not shown in the drawings and must be shown to scale or the features canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang, et. al. (US 11043567 B2) as modified by Wu (US 20180151419 A1).
Regarding independent claim 1, Chiang teaches a method for forming a semiconductor device structure (Chiang, Abstract) comprising:
forming a dummy gate stack (120) (FIG. 1L) over a substrate (Chiang, col. 5; lines 43-61);
forming a dielectric layer (144) (FIG. 1L) laterally surrounding the dummy gate stack (Chiang, col. 5, lines 61-67; col. 6, lines 1-13);
removing the dummy gate stack to form a trench (138)(FIG. 1M) surrounded by the dielectric layer (Chiang, col. 5; lines 43-61) (fig 1M);
and forming a metal gate stack (150)(FIG. 1O) in the trench (Chiang, col. 6, lines 14-15).
Chiang fails to disclose introducing dopants into an upper portion of the dielectric layer.
Wu teaches introducing dopants into an upper portion of the dielectric layer (108; FIG. 1) (Wu, [0010]).
It would have been obvious to a person of ordinary skill in the art to combine the teachings of Chiang with the teachings of Wu to dope the dielectric layer to reduce a parasitic capacitance associated with the device structure by adjusting the dielectric constant associated with the dielectric layer (As noted in Wu, et al. para. [0012]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang, et. al. (US 11043567 B2) and Wu (US 20180151419 A1) as further modified by Lin (US 9691766 B1).
Regarding dependent claim 2, the combination of Chiang and Wu disclose the method for forming a semiconductor device structure as claimed in claim 1.
Chiang and Wu fail to disclose thermally annealing the dielectric layer after the dopants are introduced.
Lin teaches thermally annealing the dielectric layer (110)(FIG. 2C) after the dopants are introduced (Lin, col. 4; lines 40-52).
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (thermally annealing the dielectric layer was known [Lin, col. 4, lines 25-27]), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (thermally annealing the dielectric layer would form doped regions in the dielectric layer [Lin, col. 4, lines 27-29]).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang, et. al. (US 11043567 B2) as modified by Wu (US 20180151419 A1) and Lin (US 9691766 B1).
Regarding dependent claim 3, the combination of Chiang and Wu disclose the method for forming a semiconductor device structure as claimed in claim 1.
Chiang fails to disclose thermally annealing the dielectric layer after the dopants are introduced and before the dummy gate stack is removed.
In the same field of endeavor, Wu discloses thermally annealing the dielectric layer (108; FIG. 1) after the dopants are introduced and before the dummy gate stack (114a)(FIG. 1) is removed (Wu, [0033]).
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (thermally annealing the dielectric layer was known [Lin, col. 4, lines 25-27]), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (thermally annealing the dielectric layer would form doped regions in the dielectric layer [Lin, col. 4, lines 27-29]).
Regarding dependent claim 4, the combination of Chiang, and Wu disclose the method for forming a semiconductor device structure as claimed in claim 3.
However, Chiang fails to teach wherein the dielectric layer is thermally annealed using a micro-second annealing process.
Wu teaches wherein the dielectric layer (108; FIG. 1) is thermally annealed using a micro-second annealing process (Wu, [0034]).
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (thermally annealing the dielectric layer using a micro-second annealing process was known [Wu, [0034]]), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (thermally annealing the dielectric layer with a micro-second annealing process would drive dopants into the dielectric layer to form doped regions [Wu, [0034]]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang, et. al. (US 11043567 B2) and Wu (US 20180151419 A1) as further modified by Lin (US 9691766 B1).
Regarding dependent claim 5, the combination of Chiang and Wu disclose the method for forming a semiconductor device structure as claimed in claim 1.
However, Chiang and Wu do not explicitly disclose the dopants are introduced using an implantation process.
Lin discloses the dopants are introduced using an implantation process (Lin, Col. 4, lines 46-49).
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (implantation processes are known [Lin, col. 4; line 21]) and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (implanting dopants via an implantation process into the dielectric layer would result in the formation of doped regions [Lin, col. 4; lines 29-30]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang, et. al. (US 11043567 B2) and Wu (US 20180151419 A1) as modified by Lin (US 9691766 B1) and Nainani (US 20140004689 A1).
Regarding dependent claim 6, the combination of Chiang and Wu disclose the method for forming a semiconductor device structure as claimed in claim 1.
However, the combination of Chiang and Wu do not explicitly disclose wherein the dopants comprise nitrogen, argon, germanium, or a combination thereof.
In the same field of endeavor, Nainani and Lin disclose wherein the dopants comprise nitrogen, argon, germanium, or a combination thereof (Lin, col. 4; lines 10-32) (Nainani, [0009]).
It would have been obvious to a person of ordinary skill in the art to combine the teachings of Chiang and Wu with the dopants described in Nainani and Lin in order to alter the dielectric constant of the dielectric layer (as noted in Wu, para. [0012]).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang, et. al. (US 11043567 B2) and Wu (US 20180151419 A1) as modified by Gu (US 20200388693 A1).
Regarding dependent claim 7, the combination of Chiang and Wu as modified by Gu disclose the method for forming a semiconductor device structure as claimed in claim 1.
However, Chiang and Wu do not explicitly teach wherein a lower portion of the dielectric layer is free of the dopants.
In the same field of endeavor, Gu teaches wherein a lower portion of the dielectric layer is free of the dopants (Gu, para. [0030]).
It would have been obvious to a person of ordinary skill in the art to combine the teachings of Chiang and Wu with the teachings of Gu to block or diminish plasma damage (as noted in para. [0033] of Gu) to the underlying substrate during the manufacturing process.
Regarding dependent claim 8, the combination of Chiang and Wu disclose the method for forming a semiconductor device structure as claimed in claim 7.
However, Chiang and Wu do not explicitly disclose wherein the upper portion of the dielectric layer has an atomic concentration of the dopants, and the atomic concentration of the dopants gradually decreases from a top of the dielectric layer towards the lower portion of the dielectric layer.
Gu teaches wherein the upper portion of the dielectric layer has an atomic concentration of the dopants, and the atomic concentration of the dopants gradually decreases from a top of the dielectric layer towards the lower portion of the dielectric layer. (Gu, para. [0030]).
It would have been obvious to a person of ordinary skill in the art to combine the teachings of Chiang and Wu with the teachings of Gu (as noted in para. [0033] of Gu) to block or diminish plasma damage to the underlying substrate during the manufacturing process.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang, et. al. (US 11043567 B2) and Wu (US 20180151419 A1) as modified by Ponoth (US 20120248508 A1).
Regarding dependent claim 9, the combination of Chiang and Wu disclose the method for forming a semiconductor device structure as claimed in claim 8.
However, Chiang and Wu do not explicitly teach forming a conductive contact in the dielectric layer, wherein an upper portion of the conductive contact is surrounded by the upper portion of the dielectric layer, and a lower portion of the conductive contact is surrounded by the lower portion of the dielectric layer.
In the same field of endeavor, Ponoth teaches forming a conductive contact (1011, 1021) (FIG. 10A) in the dielectric layer (1113)(FIG. 10A), wherein an upper portion of the conductive contact is surrounded by the upper portion of the dielectric layer, and a lower portion of the conductive contact is surrounded by the lower portion of the dielectric layer. (Ponoth, FIG. 9, para. [0042]).
It would have been obvious to a person of ordinary skill in the art to combine the teachings of Chiang and Wu with the teachings of Ponoth to enable a transistor to function by connecting the source, drain, and/or gate of the transistor (as noted in para. [0003] of Ponoth).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang, et. al. (US 11043567 B2) and Wu (US 20180151419 A1) as modified by Khanna (US 20130224944 A1).
Regarding dependent claim 10, the combination of Chiang and Wu teach the method for forming a semiconductor device structure as claimed in claim 1.
However, Chiang and Wu do not explicitly disclose wherein an upper portion of the trench is wider than a lower portion of the trench.
Khanna teaches wherein an upper portion of the trench (59, FIG. 10) is wider than a lower portion of the trench (Khanna, FIG. 10; para. [0020]).
It would have been obvious to one skilled in the art to combine the teachings of Chiang and Wu with the chamfered sidewall profile of Khanna to funnel metal into the lower portion of the trench, thereby preventing voiding (as noted in para. [0020] of Khanna.)
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang, et. al. (US 11043567 B2) as modified by Wu (US 20180151419 A1).
Regarding independent claim 11, Chiang teaches a method for forming a semiconductor device structure (Chiang, Abstract) comprising:
forming a dummy gate stack (120) (FIG. 1L) over a substrate (Chiang, col. 5; lines 43-61);
forming a dielectric layer (144) (FIG. 1L) laterally surrounding the dummy gate stack (Chiang, col. 5, lines 61-67; col. 6, lines 1-13).
Chiang does not explicitly teach implanting elements into the dielectric layer; and replacing the dummy gate stack with a metal gate stack after the implanting of the elements.
Wu teaches implanting elements into the dielectric layer (Wu, [0010]); and
replacing the dummy gate stack (114a)(FIG. 1) with a metal gate stack after the implanting of the elements. (Wu, [0024], [0030])
It would have been obvious to one skilled in the art to combine the teachings of Chiang and Wu to reduce a parasitic capacitance associated with the device structure by adjusting the dielectric constant associated with the dielectric layer (as noted in Wu, para. [0012]).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang, et. al. (US 11043567 B2) as modified by Wu (US 9691766 B1).
Regarding dependent claim 12, the combination of Chiang and Wu disclose the method for forming a semiconductor device structure as claimed in claim 11.
Chiang fails to disclose thermally annealing the elements and the dielectric layer.
In the same field of endeavor, Wu discloses thermally annealing the dielectric layer (108, FIG. 1) (Wu, [0033]).
It would have been obvious to a person of ordinary skill in the art to combine the teachings of Chiang with the teachings of Wu to enabling the dopants to disperse throughout the dielectric layer (as noted in Wu, para. [0033]).
Regarding dependent claim 13, the combination of Chiang, and Wu disclose the method for forming a semiconductor device structure as claimed in claim 12.
However, Chiang fails to teach wherein the elements and the dielectric layer are thermally annealed using a micro-second annealing process.
Wu teaches wherein the elements and the dielectric layer (108, FIG. 1) are thermally annealed using a micro-second annealing process (Wu, [0034]).
It would have been obvious to a person of ordinary skill in the art to combine the teachings of Chiang with the micro-second annealing process described in Wu in order to enable dopants to disperse throughout the dielectric layer (as noted in Wu, [0034])
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang, et. al. (US 11043567 B2) and Wu (US 20180151419 A1) as modified by Zhu (US 20190304976 A1).
Regarding dependent claim 14, the combination of Chiang and Wu disclose the method for forming a semiconductor device structure as claimed in claim 11.
However, the combination of Chiang and Wu do not explicitly disclose recessing the metal gate stack and forming a protective structure over the metal gate stack.
Zhu teaches recessing the metal gate stack and forming a protective structure (1039)(FIG. 20) over the metal gate stack (Zhu, [0102].)
It would have been obvious to a person of ordinary skill in the art to combine the teachings of Chiang and Wu with the teachings of Zhu to protect the metal gate stack [Zhu, 102].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang, et. al. (US 11043567 B2) and Wu (US 20180151419 A1) as modified by Kim (US 20120088359 A1).
Regarding dependent claim 15, the combination of Chiang and Wu disclose the method for forming a semiconductor device structure as claimed in claim 11.
However, Chiang and Wu do not explicitly teach wherein a top of the metal gate stack is formed to be wider than a top of the dummy gate stack.
Kim teaches wherein a top of the metal gate stack is formed to be wider than a top of the dummy gate stack (Kim, [0011]).
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (forming a metal gate stack is known [Kim, [0018]]), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (forming a metal gate stack using certain embodiments of Kim would result in a metal gate stack having a width that flares outward with increased distance from the substrate [Kim, [0018]]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Amano (US 20210280686 A1) as modified by Gu (US 20200388693 A1).
Regarding independent claim 16, Amano discloses a semiconductor device structure comprising: a gate stack over a substrate; (Amano, [0087]) and a dielectric layer laterally surrounding the gate stack; (Amano [0087]).
However, Amano does not explicitly teach wherein an upper portion of the dielectric layer comprises dopants, and a lower portion of the dielectric layer is free of the dopants.
In the same field of endeavor, Gu teaches wherein an upper portion (120NU; FIG. 1C) of the dielectric layer comprises dopants, and a lower portion (120NL; FIG. 1L) of the dielectric layer is free of the dopants (Gu, [0030]-[0031]).
It would have been obvious to a person of ordinary skill in the art to combine the teachings of Amano with the dopant profiles of Gu to manufacture a dielectric layer having a doped upper portion that can mitigate plasma damage (as noted in para. [0033] of Gu) to an underlying gate structure during a plasma-enhanced CVD process while preserving the insulating properties of the dopant-free lower portion.
Claim 17 and 18 is rejected under 35 U.S.C. 103 as being unpatentable over Amano (US 20210280686 A1) as modified by Gu, (US 20200388693 A1) as modified by Lin (US 9691766 B1) and Nainani (US 20140004689 A1).
Regarding dependent claim 17, the combination of Amano and Gu disclose the semiconductor device structure as claimed in claim 16.
However, the combination of Amano and Gu do not explicitly disclose wherein the dopants comprise nitrogen, argon, germanium, or a combination thereof.
In the same field of endeavor, Nainani and Lin disclose wherein the dopants comprise nitrogen, argon, germanium, or a combination thereof (Lin, col. 4; lines 10-32) (Nainani, [0009]).
It would have been obvious to a person of ordinary skill in the art to combine the teachings of Amano and Gu with the dopants described in Nainani and Lin in order to alter the dielectric constant of the dielectric layer, thereby reducing a parasitic capacitance associated with the device (as noted in Wu, para. [0012]).
Regarding dependent claim 18, the combination of Amano and Gu disclose the method for forming a semiconductor device structure as claimed in claim 16.
However, Amano does not explicitly disclose wherein the upper portion of the dielectric layer has an atomic concentration of the dopants, and the atomic concentration of the dopants gradually decreases from a top of the dielectric layer towards the lower portion of the dielectric layer.
Gu teaches wherein the upper portion (120NU, FIG. 1A) of the dielectric layer (120, FIG. 1A) has an atomic concentration of the dopants, and the atomic concentration of the dopants gradually decreases from a top of the dielectric layer towards the lower portion (120NL, FIG. 1A) of the dielectric layer. (Gu, para. [0030]).
It would have been obvious to a person of ordinary skill in the art to combine the teachings of Chiang and Wu with the teachings of Gu to block or diminish plasma damage to the underlying substrate during the manufacturing process (as noted in para. [0033] of Gu).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Amano (US 20210280686 A1) and Gu (US 20200388693 A1) as modified by Ponoth (US 20120248508 A1).
Regarding dependent claim 19, the combination of Amano and Gu disclose a semiconductor device structure as claimed in claim 16.
However, Amano and Gu do not explicitly teach further comprising a conductive contact penetrating through the upper portion and the lower portion of the dielectric layer.
In the same field of endeavor, Ponoth teaches a conductive contact (1011, 1021) (FIG. 10A) in the dielectric layer (1113)(FIG. 10A), penetrating through the upper portion and the lower portion of the dielectric layer (Ponoth, FIG. 9, para. [0042]).
It would have been obvious to a person of ordinary skill in the art to combine the teachings of Amano and Gu with the teachings of Ponoth to enable a transistor to function by connecting the source, drain, and/or gate of the transistor via a conductive contact (as noted in para. [0003] of Ponoth).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over over Amano (US 20210280686 A1) and Gu (US 20200388693 A1) as modified by Zhu (US 20190304976 A1).
Regarding dependent claim 20, the combination of Amano and Gu disclose the method for forming a semiconductor device structure as claimed in claim 16.
However, the combination of Chiang and Wu do not explicitly disclose a protective structure over the gate stack, wherein a top of the protective structure is closer to a top of the dielectric layer than the gate stack.
Zhu teaches a protective structure (1039; FIG. 20) over the gate stack, wherein a top of the protective structure (1039; FIG. 20) is closer to a top of the dielectric layer (1031; FIG. 20) than the gate stack. ((Zhu, [0102].)
It would have been obvious to a person of ordinary skill in the art to combine the teachings of Chiang and Wu with the teachings of Zhu to protect the metal gate stack [Zhu, 102].
Conclusion
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US Patent Publication US-20170005006-A1 to Ando;
US Patent Publication US-20210066476-A1 to Kao; and
US Patent Publication US-20200295163-A1 to Chui.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joseph Godoy whose telephone number is (571) 272-1346. The examiner can normally be reached on Monday-Friday 9AM-5PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH PATRICK GODOY/ Examiner, Art Unit 2897
/BRADLEY SMITH/ Primary Examiner, Art Unit 2817
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