DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
The indicated allowability of claims 27, 29, 32,35-39, 41, 42, & 44-46 are withdrawn in view of the newly discovered reference(s) to Kim (US RE49,478 E) and Lee (US Pub no 2018/0026067 A1).Rejections based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 27,37,38,42, & 44 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (US RE49,478 E).
Regarding claim 27, Kim et al discloses A semiconductor device(fig. 4/fig. 9b) comprising: a first section (100b)including: a first semiconductor layer(101) (col. 16, lines 4-5); and a first wiring layer(Mu)(col. 16, line 16); and
a second section(220 of 220b) including: a second semiconductor layer(201) fig. 4/fig. 9b(col 8, lines 27-35); a second wiring layer(Md) (col. 16 lines 25-30); and
a third wiring layer((MTJ structure disposed between MMn-2 and MMn-1) (col. 9, lines 61-63,claim 1), wherein the first section (100b)and the second section(220 of 200b) are stacked vertically fig. 9b(col. 16,lines 36-40;col 8, lines 27-35), wherein the first section(100b) and the second section(220 of 200b) are bonded together such
that the first wiring layer(Mu) and the second wiring layer(Md) face each other fig. 4/ fig. 9b(col. 16, lines 36-42), wherein each of the first wiring layer (Mu)and the second wiring layer(Md) includes a plurality of electrodes(140 and 240)(col. 16, lines36-42) fig. 9b , wherein the plurality of electrodes(140) in the first wiring layer (Mu)and the plurality
of electrodes (240)in the second wiring layer(Md) are connected by CuCu connections(col. 16, lines 40-45), wherein the second semiconductor layer (201) and the second wiring layer(Md) include at least a part of a memory circuit(220), and wherein a size of the first section(100b/100) is larger than a size of the second section(220 of 200b) in a plan view fig. 1/fig. 4/fig. 9b (the pixel area is larger than eMRAM area).
Regarding claim 37, Kim et al discloses wherein the first semiconductor layer (101b) includes photoelectric conversion elements configured to generate pixel signals(col. 8, lines 1-5; col. 16, lines 64-67).
Regarding claim 38, wherein the second semiconductor layer (201) includes a first signal processing circuit configured to process pixel signals(col. 17, lines 3-18).
Regarding claim 42, Kim et al discloses An imaging apparatus (fig. 4/ fig. 9b)comprising: a backside illumination type solid-state imaging device(col. 15 lines 65) that includes: a first section(100b) including: a first semiconductor layer(101) (col. 16, lines 4-5); and a first wiring layer(Mu) )(col. 16, line 16); and a second section(220 of 200b) fig. 4/fig. 9b(col 8, lines 27-35) including: a second semiconductor layer(201) fig. 4/fig. 9b(col 8, lines 27-35); a second wiring layer(Md) (col. 16 lines 25-30); and a third wiring layer((MTJ structure disposed between MMn-2 and MMn-1) (col. 9, lines 61-63,claim 1), wherein the first section(100b) and the second section (220 of 200b)are stacked vertically fig. 9b(col. 16,lines 36-40;col 8, lines 27-35), wherein the first section (100b)and the second section (220 of 200b)are bonded together such that the first wiring layer (Mu)and the second wiring layer(Md) face each other fig. 4/ fig. 9b(col. 16, lines 36-42), wherein each of the first wiring layer (Mu)and the second wiring layer(Md) includes a plurality of electrodes(140), wherein the plurality of electrodes (140)in the first wiring layer(Mu) and the plurality of electrodes (240)in the second wiring layer(Md) are connected by CuCu connections (col. 16, lines 40-45), wherein the second semiconductor layer (201)and the second wiring layer(Md) include at least a part of a memory circuit(220), wherein the first semiconductor layer(101 ) includes photoelectric conversion elements configured to generate pixel signals(col. 8, lines 1-5; col. 16, lines 64-67)..
Regarding claim 44, Kim et al discloses wherein a
size of the first section (100)is larger than a size of the second section (220)in a plan view fig. 1//fig. 4.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 42, 45, & 46 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub no 2018/0026067 A1).
Regarding claim 42, Lee et al discloses an imaging apparatus comprising:
a first section(104) including: a first semiconductor layer(208); and a first wiring layer(210) [0025]; and a second section(106/116) including: a second semiconductor layer(226); a second wiring layer(228)[0030]; and a third wiring layer(128b)[0033], wherein the first section(104) and the second section (106/116)are stacked vertically, wherein the first section (104)and the second section (106/116)are bonded together such that the first wiring layer(210) and the second wiring layer (228)face each other[0029], wherein each of the first wiring layer (210)and the second wiring layer (228)includes a plurality of electrodes, wherein the plurality of electrodes(222) in the first wiring layer(210) and the plurality of electrodes(224) in the second wiring layer(228) are connected by CuCu connections[0029], wherein the second semiconductor layer (226)and the second wiring layer(228) include at least a part of a memory circuit[0030], and wherein the first semiconductor layer(208) includes photoelectric conversion elements configured to generate pixel signals[0026].
Lee et al fails to teach a backside illumination type solid-state imaging device. However, in the background of the invention, Lee et al discloses the use of backside illumination type solid-state imaging device[0001]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee et al with the teachings of the background of the invention since the device is increasingly favored due to low power consumption, small size, fast data processing, a direct output of data, and low manufacturing cost.
Regarding claim 45, Lee et al discloses wherein the second section further includes a third semiconductor layer(132), and wherein the third semiconductor layer includes a logic circuit[0021].
Regarding claim 46, Lee et al discloses wherein a size of the second semiconductor layer(226) is larger than a size of the third semiconductor layer(132) fig. 2b[0021].
Claim(s) 27, 29, 32, 35, 36,37, 38, 39, 41, & 44 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub no 2018/0026067 A1) in view of Wakiyama (WO 2016143288 A1).
Regarding claim 27, Lee et al discloses A semiconductor device (200a) comprising: a first section (104)[0025]including: a first semiconductor layer(208) [0025]; and a first wiring layer(210)[0025]; and a second section(106/116) [0030] including: a second semiconductor layer(226 or 130)[0030]; a second wiring layer(228)[0030]; and a third wiring layer(128b)[0030], wherein the first section(104) and the second section (106/116)are stacked vertically fig. 2a, wherein the first section (104)and the second section(106/116) are bonded together such that the first wiring layer (210)and the second wiring layer(228) face each other[0029], wherein each of the first wiring layer(210) and the second wiring layer(228) includes a plurality of electrodes(222 and 224), wherein the plurality of electrodes(222) in the first wiring layer (210)and the plurality of electrodes(224) in the second wiring layer (228)are connected by CuCu connections[0029], wherein the second semiconductor layer(226 or 130) and the second wiring layer(228) include at least a part of a memory circuit[0030] but fails to teach wherein a size of the first section is larger than a size of the second section in a plan view.
However, Wakiyama et al teaches a solid state imaging device wherein a size of the first section(402) is larger than a size of the second section(472) in a plan view(pp. 54 para 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee et al with the teachings of Wakiyama et al to reduce the size of the solid state capturing device.
Regarding claim 29, Lee et al discloses wherein the second section further includes a third semiconductor layer(130 or 132), and wherein a size of the second semiconductor layer(226) is larger than a size of the third semiconductor layer(130) fig. 2a.
Regarding claim 32, Lee et al discloses wherein the second wiring layer (228)and the third wiring layer(128b) are electrically connected via a through via(126a)[0042], and wherein the second section(106/116) further includes a third semiconductor layer(132), and wherein at least a part of the second semiconductor layer(130) and the third semiconductor layer (132)are located at a same level (fig. 2b).
Regarding claim 35, Lee et al discloses wherein the second semiconductor layer (130)is arranged between the second wiring layer(228) and the third wiring layer(128b) fig. 2b.
Regarding claim 36, Lee et al discloses wherein the second semiconductor layer (130)and the third semiconductor layer (132)are insulated by an insulating film[0033] fig. 2b.
Regarding claim 37, Lee et al discloses wherein the first semiconductor layer(104) includes photoelectric conversion elements configured to generate pixel signals[0026].
Regarding claim 38, Lee et al discloses wherein the second semiconductor layer(226) includes a first signal processing circuit configured to process pixel signals[0030] [0013-0014].
Regarding claim 39, Lee et al discloses wherein the third semiconductor layer(130 or 132) includes a second signal processing circuit configured to process pixel signals[0013-0014][0033].
Regarding claim 41, Lee et al discloses wherein the third semiconductor layer (132)includes a logic circuit [0021].
Regarding claim 44, Lee et al discloses all the claim limitations of claim 42 but fails to teach wherein a size of the first section is larger than a size of the second section in a plan view.
However, Wakiyama et al teaches a solid state imaging device wherein a size of the first section(402) is larger than a size of the second section(472) in a plan view(pp. 54 para 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee et al with the teachings of Wakiyama et al to reduce the size of the solid state capturing device.
Conclusion
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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