DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 27,35,38,39,41, 42, ,48,49,51,52, & 53 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furuhashi (US Pub no. 2019/0386052 A1) in view of Komai (US Pub no. 2016/0284753 A1).
Regarding claim 27, Furuhashi et al discloses A semiconductor device comprising: a first section (104)including: a first semiconductor layer(102); and a first wiring layer(118a to 118c)[0123]; a second section(103) including: a second semiconductor layer(101); a second wiring layer(107); and a third wiring layer(113a-113b)[0122], and a third section(26 or 28) including: a third semiconductor layer(55 or 46); and a fourth wiring layer(35a or 35c; or 57a or 57b)[0091][0064], wherein the first section(104), the second section(103) and the third section (26 or 28)are stacked vertically fig. 16; wherein the first section(104) and the second section (103)are bonded together such that the first wiring layer (118a to 118c)[and the second wiring layer(107) face each other, wherein each of the first wiring layer (107)and the second wiring layer (118a to 118c)includes a plurality of electrodes(117), wherein the plurality of electrodes(117) in the first wiring layer and the plurality of electrodes(114) in the second wiring layer (107)are connected by CuCu connections[0112](116/115), wherein the second semiconductor layer (101)and the second wiring layer(107) include at least a part of a memory circuit[0118], and wherein a size of the first section(104) is larger than a size of the second section(103) in a plan view fig. 16(the cross sectional view shows that logic (102) is larger than the other sections stacked on top and therefore would have a larger size in plan view).
Furuhashi et al fails to teach the first section, the second section, and the third section include respective portions of a wiring structure, the respective portions being located at substantially the same position in plan view and being arranged substantially in a straight line in a perspective view along the stacking direction, the wiring structure extending through at least two of the first semiconductor layer.
Komai et al discloses a semiconductor device comprising, a connection wiring(182) extending through a first semiconductor layer (81/11), second semiconductor layer (812/801),& third semiconductor layer(101/12) fig. 118[0851][0674]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Furuhashi et al with the teachings of Komai et al such that the first section, the second section, and the third section include respective portions of a wiring structure, the respective portions being located at substantially the same position in plan view and being arranged substantially in a straight line in a perspective view along the stacking direction, the wiring structure extending through at least two of the first semiconductor layer second semiconductor layer ,& third semiconductor layer results to provide connection of the pixel sensor to the logic substrate.
Regarding claim 35, Furuhashi et al discloses wherein the second semiconductor layer is arranged between the second wiring layer and the third wiring layer.
Regarding claim 38, Furuhashi et al discloses wherein
the second semiconductor layer(101) includes a first signal processing circuit (55)configured to process pixel signals[0120].
Regarding claim 39, Furuhashi et al discloses wherein the third semiconductor layer (46)includes a second signal processing circuit configured to process pixel signals[0119].
Regarding claim 41, Furuhashi et al discloses wherein the third semiconductor layer (55)includes a logic circuit[0118].
Regarding claim 42, Furuhashi et al discloses An imaging apparatus(fig. 16), comprising: a backside illumination type solid-state imaging device that includes: a first section(28), including: a first semiconductor layer(46); and a first wiring layer(57a-57b)[0064]; and a second section (26/103)including: a second semiconductor layer(101); a second wiring layer(35a-35b); and a third wiring layer(113a-113b); and a third section(104), including: a third semiconductor layer(102); and a fourth wiring layer(118a-118b)[0123], wherein the first section(28),and the second section(26/103), and the third section(104) are stacked vertically fig. 16 wherein the first section (28)and the second section (26/103)are bonded together such that the first wiring layer (57a-57b)and the second wiring layer (35a-35b)face each other fig.16[0063-0064],
wherein each of the first wiring layer (57a-57b)and the second wiring layer(35a-35b) includes a plurality of electrodes(35c), wherein the plurality of electrodes(58) in the first wiring layer (57a-57b and the plurality of electrodes in the second wiring layer are connected by CuCu connections(71/72)[0063][0065][0112], wherein the second semiconductor layer (101)and the second wiring layer(35a-35b) include at least a part of a memory circuit[0118], and wherein the first semiconductor layer(46) includes photoelectric conversion elements (2)configured to generate pixel signals[0043][0118].
Furuhashi et al discloses wherein the first section, the second section, and the third section include respective portions of a wiring structure, the respective portions being located at substantially a same position in plan view and being arranged substantially in a straight line in a perspective view along a stacking direction, the wiring structure
extending through at least two of the first semiconductor layer, the second
semiconductor layer, and the third semiconductor layer.
Komai et al discloses a semiconductor device comprising, a connection wiring(182) extending through a first semiconductor layer (81/11), second semiconductor layer (812/801),& third semiconductor layer(101/12) fig. 118[0851][0674]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Furuhashi et al with the teachings of Komai et al such that the first section, the second section, and the third section include respective portions of a wiring structure, the respective portions being located at substantially the same position in plan view and being arranged substantially in a straight line in a perspective view along the stacking direction, the wiring structure extending through at least two of the first semiconductor layer second semiconductor layer ,& third semiconductor layer results to provide connection of the pixel sensor to the logic substrate.
Regarding claim 48, Furuhashi et al discloses wherein the fourth wiring layer (118a-118b)faces the first section (28) and the second section(26/103) fig. 16.
Regarding claim 49, Furuhashi et al discloses wherein the third semiconductor layer (102)includes at least a part of a logic circuit [0118] fig. 16.
Regarding claim 51, Furuhashi et al discloses wherein the fourth wiring layer (35a or 35c; or 57a or 57b)[0091][0064]faces the first section(104) and the second section(103) fig. 16.
Regarding claim 52, Komai et al discloses wherein the wiring structure (182) is a contact[0674] fig. 118.
Regarding claim 53, Komai et al discloses wherein the wiring structure(182) is a contact[0674] fig. 118.
Allowable Subject Matter
Claims 32,36,37,47 & 50 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 27,32,35-39,41,42, & 47-53 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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