DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Drawings
All replacement FIGs are objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The drawings are pixelated because applicant did not use black (RGB = 000), despite the drawings appearing black to the naked eye. This has been confirmed by the examiner via a color inspection of applicant' s submitted pdf file. In such a case, the dithering used to convert applicant's grayscale image to black and white will add white pixels to try to estimate applicant's "gray" color, and the final drawings may not print properly or may print with reduced quality. Therefore, applicant must be sure to use only black and white. Applicant may perform the following process to correct the color content:
1. Open the drawings PDF file with Adobe Acrobat Pro DC (a similar Adobe product may work, but the examiner has only tested this in Adobe Acrobat Pro DC);
2. Click “File” and then click “Print”;
3. Select “Adobe PDF” as the printer. If not available, “Microsoft Print to PDF” may also work, though this has not been tested. If neither option is available, this process may not be applicable, and applicant should try to find an alternate way to print in only black and white.
4. Uncheck “Print in grayscale (black and white)”;
5. Uncheck “Save ink/toner”;
6. Click “Advanced”;
7. Under “Color Management”, for the “Color Profile” field, select “Black & White” near the bottom of the list. The examiner also had “Treat grays as K-only grays” checked, and “Preserve Black” checked.
8. Click “OK” and then click “Print”. The resulting PDF should comprise only black and white drawings. Please review the final drawings for potential unintended consequences of this process.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 5 is objected to because of the following informalities:
Please re-insert --and-- at the end of line 6. It appears the previous objection to remove the “and” was made in error.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-13, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Damani et al., U.S. Patent Application Publication No. 2023/0115044, in view of the examiner’s taking of Official Notice.
Referring to claim 1, Damani has taught a processor comprising:
a control register comprising a bit which is to specify a state of enablement of an implicit synchronization control (from paragraph 23 of the applicant’s specification, “‘explicit synchronization’ refers herein to thread synchronization which is provided by processor hardware based on one or more instructions of a program explicitly requesting or otherwise stating that such synchronization is to be provided. By contrast, ‘implicit synchronization’ refers herein to thread synchronization which is provided by processor hardware in the absence of any such one or more explicit instructions.” From paragraph 4 of Damani, when branch divergence occurs, the system alone (without explicit control/request by a user/program) prioritizes branch paths based on the cardinality (number of) threads for each path. This is implicit synchronization control which may be overridden by explicit control discussed in paragraphs 31-32 of Damani, register R9 is a control register that indicates the priorities of the branch paths of a branch instruction. Note that when any one bit is set in R9 for a branch path that would not have priority based on cardinality (such that R9 is not equal to RZ, i.e., 0 (RZ is a zero register as known in the art)), this would indicate that the corresponding branch path has priority, even if it involves fewer threads (thereby allowing a user to prioritize the actual function performed, not the number of threads). As a basic example, assume a branch with three branch paths in a warp with 12 threads (as shown in FIG.3). If R9=RZ=0, then they are prioritized based on cardinality (which is the default implicit control). If path 0 includes 7 threads, path 1 includes 3 threads, and path 2 includes 2 threads, then they will execute in that order, as determined by the system alone. However, if a bit is set somewhere in R9 that raises priority for path 2 over paths 0 and 1, then the order of execution would be explicitly controlled to be path 2, path 0, and path 1. This would be done where performing the function of path 2 is prioritized over the majority of the threads. As such, when the bit = 0, implicit control is enabled. When the bit = 1, explicit control is enabled (implicit control is disabled, e.g. not relied on solely));
first circuitry to execute an instruction of a program, wherein the first circuitry to execute the instruction comprises the first circuitry to perform an access to the control register (from paragraph 32, the LD instruction accesses R9 by loading priorities into R9), wherein the access is to write a value to the bit (a value of ‘1’ is written to the bit by the LD instruction), and wherein the program is to provide a thread group which comprises a first thread of execution and a second thread of execution (see FIG.3, which shows a thread group (warp) 304); and
second circuitry coupled to the control register and the first circuitry, the second circuitry to transition, based on the access, between:
a first operational mode wherein the implicit synchronization control is enabled, wherein the implicit synchronization control is to apply one or more synchronization requirements to threads of execution (from paragraph 4, when branch divergence occurs and R9=RZ=0, the system prioritizes branch paths based on the cardinality (number of) threads for each path. This is a first mode with implicit control, which will cause threads for one branch path having one cardinality to execute before threads for another branch path having another cardinality); and
a second operational mode wherein the implicit synchronization control is disabled (in a second mode, the ordering based on cardinality may be overridden by writing/reading priorities to/from R9 (implicit control is disabled in favor of explicit control). Where said another branch path is prioritized by R9 (e.g. because the function performed in said another branch path is to be prioritized instead of the cardinality (paragraph 32)), said another branch path’s synchronization with respect to said one branch path would be disabled, meaning said another branch path does not have to wait to execute until said one branch path is complete); and
wherein the second circuitry is further to determine, based on one of the first operational mode or the second operational mode, an order of execution of a first one or more instructions of the first thread of execution relative to a second one or more instructions of the second thread of execution (even if cardinality would normally dictate that said one branch path would execute first and said another branch path would execute second (first mode), switching to the second mode via setting the control register to prioritize said another branch path would reverse the execution order and cause said another branch path to execute before said one branch path).
Damani has not taught that the first one or more instructions comprise a first one or more microoperations, nor that the second one or more instructions comprises a second one or more microoperations. However, Official Notice is taken that execution of micro-operations was well known in the art before applicant’s invention. Specifically, micro-operations are low level operations that more complex instructions are decoded/translated into. This allows for different complex instruction sets to be mapped to the same processor while also simplifying the hardware design (since the hardware is built to execute groups of simple operations as opposed to complex operations directly). Use of microoperations also has other known advantages in terms of flexibility, upgradability, debugging, etc. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Damani such that the instructions of the threads include microoperations.
Referring to claim 2, Damani, as modified, has taught the processor of claim 1, wherein:
according to the one or more synchronization requirements, an execution of the first one or more microoperations is to be performed after a completion of an execution of the second one or more microoperations; based on the access, the second circuitry is to transition to the second operational mode; and the second circuitry to determine the order of execution comprises, based on the second operational mode, the second circuitry to prevent a delay of an execution of the first one or more microoperations (see the rejection of claim 1. Said another branch path corresponds to the first one or more microoperations, and said one branch path corresponds to the second one or more microoperations. Without priorities set in R9, the first mode is active, and said another branch path would be delayed (due to cardinality) such that it executes after said one branch path is complete. However, setting said another branch path to higher priority than said one branch path would remove this delay and allow said another branch path to execute before said one branch path).
Referring to claim 3, Damani, as modified, has taught the processor of claim 1, wherein: the first thread of execution is to follow a first path of a branch instruction of the program; the second thread of execution is to follow a second path of the branch instruction; according to the one or more synchronization requirements, an execution of the first one or more microoperations based on the first path is to be performed prior to an execution of the second one or more microoperations based on the second path; based on the access, the second circuitry is to transition to the second operational mode; and the second circuitry to determine the order of execution comprises, based on the second operational mode, the second circuitry to select the second one or more microoperations to be executed prior to an execution of the first one or more microoperations (again, see the rejection of claim 1. Said one branch path corresponds to the first one or more microoperations, and said another branch path corresponds to the second one or more microoperations. Said one branch path would execute first based on cardinality unless the second mode is used based on control register priorities, in which case said another branch path will execute before said one branch path).
Referring to claim 4, Damani, as modified, has taught the processor of claim 1, wherein:
the instruction is a first instruction (the LD instruction of paragraph 32 is a first instruction); the access is a first access (the same LD instructions performs a first access of R9 to set specific priorities for the subsequent branch based on R9); based on the first access, the second circuitry is to transition to the second operational mode (again, based on writing the priorities to R9, the processor will transition to a mode using the priorities to determine execution order);
Damani has not explicitly taught that the first circuitry is further to execute a second instruction of the program, wherein the first circuitry is to perform a second access to the control register; the second circuitry, based on the second access, is to transition from the second operational mode to the first operational mode; and the second circuitry is further to determine, based on the first operational mode, an order of execution of a third one or more microoperations of the first thread of execution relative to a fourth one or more microoperations of the second thread of execution. However, Official Notice is taken that a program having multiple branches was well known in the art before applicant’s invention. Multiple branches are useful to provide conditional execution among multiple paths at different points during program execution, thereby allowing increased flexibility for the programmer. As a result, it would have first been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Damani such that there are multiple branch instructions. Additionally, one of ordinary skill in the art would have recognized that each branch has its own branch paths and that the priorities of the branch path for each path may be different. For instance, a taken path of one branch may be deemed high priority, a taken path of another branch may be deemed low priority, and a taken path of a further branch may have equal priority as another path. This is simply a matter of user/compiler preference. Thus, after the branch in paragraph 32, a second branch may be encountered. Two of its two or more paths may have the same priority and, thus, R9 could be updated to reflect this. These two paths would be prioritized over any additional path (paragraph 33), but they have equal priority to one another. Thus, cardinality would then dictate which of the equal priority paths goes first (thus, first mode controls). This is just one example, but in general, the examiner asserts that there may be a number of situations associated with different branches, where the user would benefit from being allowed to flexibly change the priorities of the branch paths by setting the control register to fine-tune the priority for each branch separately and, thus, optimize execution. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Damani such that the first circuitry is further to execute a second instruction of the program (a second LD to set R9 for a second branch), wherein the first circuitry is to perform a second access to the control register; the second circuitry, based on the second access, is to transition from the second operational mode to the first operational mode (if multiple paths are equal in priority, cardinality would be used); and the second circuitry is further to determine, based on the first operational mode, an order of execution of a third one or more microoperations of the first thread of execution relative to a fourth one or more microoperations of the second thread of execution.
Referring to claim 6, Damani, as modified, has taught the processor of claim 1, wherein: the control register is a first control register of a first core of the processor (from FIG.4, there are multiple cores 500. Each core is shown in FIG.5 to include 700. Each module 700 is shown in FIG.7 to include a register file 706. The control register is simply a register from this file chose to store the priorities); the implicit synchronization control is a first synchronization control to apply the one or more synchronization requirements at the first core (again, R9 in paragraph 32 would apply the synchronization requirements for the core including that R9 register); and the processor further comprises a second control register to determine an enablement state of a second synchronization control which is to apply the one or more synchronization requirements at a second core of the processor (each core has its own registers and executes its own code and own branches. Thus, a second core will have a second control register that applies the same synchronization requirements (e.g. highest priority executes first) as the first core).
Referring to claim 7, Damani, as modified, has taught the processor of claim 1, wherein:
an execution of a first instruction by the first thread of execution is to comprise an execution of a plurality of microoperations which comprise the first one or more microoperations (FIG.3, e.g. one or more micro-operations corresponding to a first arrow (thread) in shard 312) and a third one or more microoperations (FIG.3, after the shards re-converge, the first thread will continue with a third one or more microoperations in warp 304. Note that execution of a first instruction occurs by executing the group of first and third micro-operations);
according to the one or more synchronization requirements, an execution of the plurality of microoperations is to be performed after a completion of an execution of the second one or more microoperations (if cardinalities of shards result in second shard 310 getting first priority, then the first thread has to wait until shard 310 completes); and
based on the second operational mode, the second one or more microoperations are to be executed after the first one or more microoperations, and before the third one or more microoperations (one of ordinary skill in the art recognizes that any shard could be given priority according to the control register. When shard 312 is given higher priority than shard 310, then shard 312 (first microoperation(s)) will execute first, followed by shard 310, followed by reconvergence instructions (third microoperations)).
Referring to claim 8, Damani, as modified, has taught the processor of claim 1, wherein the first thread of execution and the second thread of execution are each to be based on a single instruction, multiple data (SIMD) instruction (see paragraph 79. FIG.3, for instance, is SIMD for multiple threads (SIMT)).
Referring to claim 9, Damani, as modified, has taught the processor of claim 1, wherein the first operational mode is a default mode of the second circuitry (again, the LD needs to occur in FIG.3 (paragraph 32) in order to prioritize paths based on something other than cardinality. If a regular branch is used here that doesn’t reference R9, then the system still needs to choose which path goes first. This is done based on cardinality, per paragraph 4, e.g. the path having more threads would go first to get more done earlier).
Claims 10-13 and 15-16 are rejected for similar reasoning as claims 1-4 and 6-7, respectively.
Claim 17 is mostly rejected for similar reasoning as claim 1. Damani has further taught a system comprising:
a memory (paragraph 68, “system memory”);
a memory controller (FIG.4, 404, and paragraphs 66-68); and
a processor (FIG.4, 402) coupled to access the memory via the memory controller (controller 404 is used to access system memory via requests sent over interconnect 418), the processor comprising the components/actions of claim 1.
Claims 18-20 are rejected for similar reasoning as claims 2-3 and 7, respectively.
Allowable Subject Matter
Claims 5 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
On page 18 of applicant’s response, applicant argues that:
“…a review of Damani reveals that the reference fails to indicate whether or how the relied-upon vector register R9 might comprise (for example) a bit which is to specify a state of enablement of an implicit synchronization control which, when enabled, is to apply one or more synchronization requirements to threads of execution.
In the absence of Damani providing any indication to the contrary, it is to be presumed that the relied-upon vector register R9 includes no such bit. Applicants note that the claim rejection also cites to a prioritization (in Damani, paragraph [0004]) of branch targets strictly on a cardinality of threads. However, Damani fails to provide any indication whatsoever as to whether or how (for example) any bit of some alleged control register might specify a state of enablement of the relied-upon cardinality-based prioritization.”
The examiner respectfully disagrees. From paragraph 4, NVIDIA platforms (to which Damani is directed) include implicit synchronization control based on cardinality. However, Damani subsequently provides a way to override that implicit control by setting path priorities in a register (R9) to be referenced by a branch instruction. If R9 = 0 (no bit is set), then the implicit control is enabled. However, if any one bit is set, that means one path is given explicit priority that would result in it being executed before another path with higher cardinality. This is apparent to one of ordinary skill in the art reading Damani.
On page 18 of applicant’s response, applicant disagrees with the Official Notice and requests an affidavit.
The examiner is not relying on personal knowledge and, thus, need not provide an affidavit. Instead, in response to an adequate traversal of Official Notice, the examiner may provide a supporting reference. However, applicant’s traversal is inadequate because it does not “specifically point out the supposed errors in the examiner’s action, which would include stating why the noticed fact is not considered to be common knowledge or well-known in the art. A mere request by the applicant that the examiner provide documentary evidence in support of an officially-noticed fact is not a proper traversal.” Since applicant’s traversal is inadequate, the common knowledge or well-known in the art statement is taken to be admitted prior art. See MPEP 2144.03(C).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183