DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/04/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2022/0238430) hereinafter “Chen” (Chen is eligible as prior art based upon the effective filing date of application 17721675 which has an effective filing date of 06/11/2021 based on provisional application 63/209923 and an effective filing date of 10/30/2020 based on the grandparent application 17/085770) in view of Kim et al. (US 2021/0273042) hereinafter “Kim” and Kim et al. (US 2022/0223585) hereinafter “Kim2” and Wang et al. (US 2021/0272897) hereinafter “Wang” and in further view of Haraguchi et al. (US 2021/0050410) hereinafter “Haraguchi”.
Regarding claim 1, Fig. 6 of Chen teaches a semiconductor package structure, comprising: a substrate (Item 30); a first redistribution layer (Item 1041 and other BEOL structures within 104; Paragraph 0056) disposed over the substrate (Item 30); a semiconductor die (Item 20) disposed over the first redistribution layer (Item 1041 and other BEOL structures within 104); a capacitor (Item 106) disposed below the first redistribution layer (Item 1041 and other BEOL structures within 104) and electrically coupled to the semiconductor die (Item 20), wherein the capacitor comprises: a substrate (Item 102); and a plurality of capacitor cells (Item 112) embedded in the substrate (Item 102); a conductive layer (Item 108) in a bottom portion of the capacitor (Item 102) and electrically coupled to the plurality of capacitor cells (Items 112); and a first bump structure (Item 126) disposed between the capacitor (Item 102) and the substrate (Item 30).
Chen does not explicitly teach where the capacitor is a silicon capacitor nor where the silicon capacitor comprises a semiconductor substrate.
Kim teaches where a deep trench capacitor can be a higher density silicon capacitor (Paragraph 0033) using a silicon substrate (Item 173).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the capacitor of Chen be a silicon capacitor, where the silicon capacitor comprises a semiconductor substrate because a silicon capacitor comprising a semiconductor substrate is known to be used in as a capacitor embedded in a package substrate on which an integrated circuit is mounted (Kim Paragraph 0027).
Chen does not teach a first conductive via extending through the semiconductor substrate and through the plurality of capacitor cells nor where the first bump structure is electrically coupled to the first conductive via.
Fig. 3A of Kim2 teaches a first conductive via (Item 318) extending through a substrate (Item 320A) and through a plurality of capacitor cells (Items 302 and 304), where the first conductive via (Item 318) electrically connects a trace present on a top of the substrate (Item 320A) to a trace on a bottom of the substrate (Item 320A).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a first conductive via extending through the semiconductor substrate and through the plurality of capacitor cells, where the first bump structure is electrically coupled to the first conductive via because a conductive via extending through the substrate and plurality of capacitor cells is known to provide electrical coupling such that an electrical signal can be transmitted from electrical components on one side of the substrate to electrical components on the other side of the substrate (Kim2 Paragraph 0036).
Chen does not teach a dielectric layer extending through the semiconductor substrate and covering sidewalls of the conductive via.
Fig. 3A of Kim2 further teaches a dielectric layer (Item 320B; Paragraph 0035) extending through a substrate (Item 322) and covering sidewalls of a conductive via (Item 318).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a dielectric layer extending through the semiconductor substrate and covering sidewalls of the conductive via because the dielectric layer electrically and physically isolates a first electrode of a first capacitor and a second electrode of a second capacitor from a through substrate via (Kim2 Paragraphs 0035 and 0041).
Chen does not teach where the silicon capacitor is not entirely covered by the semiconductor die in a normal direction of the substrate.
Fig. 2F of Wang teaches where, in a semiconductor package structure, a capacitor (Item 216; Paragraph 0034) is not entirely covered by a semiconductor die (Item 208; labeled in Fig. 2F) in a normal direction of a substrate (Item 212).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the silicon capacitor not be entirely covered by the semiconductor die in a normal direction of the substrate because this allows for the design of the package to be more flexible (Wang Paragraph 0039). Further, the choice of location of the capacitor is a design choice which is rendered obvious as it is recognized as a mere rearrangement of parts (MPEP 2144; See also In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.) and In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice)).
Chen does not teach where the conductive layer is between the plurality of capacitor cells and the dielectric layer, and the dielectric layer extends along the bottom of the capacitor cells.
Fig. 15 of Haraguchi teaches a semiconductor package structure where more than one capacitor is stacked on each other, where a via (Item 10) extends through the stack, where a conductive layer (Item 2-1) makes electrical contact with an upper capacitor (Item 30-1), and where a dielectric layer (Lower Item 3) extends along the bottom of the capacitor (Item 30-1) such that the conductive layer (Item 2-1) is between the capacitor (Item 30-1) and the dielectric layer (Lower Item 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the conductive layer be between the plurality of capacitor cells and the dielectric layer, and the dielectric layer extends along the bottom of the capacitor cells because the dielectric layer electrically separates the conductive layer from other elements in the package while allowing the conductive layer to be electrically connected to the capacitor cell (Haraguchi Paragraph 0091). This configuration when combined with Chen above, also allows for the first conductive via to be electrically connected to elements below the capacitor without being electrically connected with the capacitor.
Regarding claim 5, Fig. 3 of Chen further teaches a second conductive via (Item 124) disposed below the substrate (Item 102; semiconductor when combined with Kim as stated in the rejection of claim 1 above) and electrically coupling the plurality of capacitor cells (Item 112) to the first bump structure (Item 126).
Regarding claim 21, Fig. 3 of Chen further teaches where the plurality of capacitor cells (Item 112) comprise top electrodes (U portion of Item 110), bottom electrodes (U portion of Item 108) and an interlayer dielectric layer (Paragraph 0031 where Item 102 is dielectric material; Further when Chen is combined with Kim as in claim 1 above the dielectric material between the top and bottom electrodes will remain while the substrate is a semiconductor material) between the top electrodes and the bottom electrodes.
Claims 2, 3, 11-14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2022/0238430) hereinafter “Chen” (Chen is eligible as prior art based upon the effective filing date of application 17721675 which has an effective filing date of 06/11/2021 based on provisional application 63/209923 and an effective filing date of 10/30/2020 based on the grandparent application 17/085770) in view of Kim et al. (US 2021/0273042) hereinafter “Kim”, Kim et al. (US 2022/0223585) hereinafter “Kim2”, Wang et al. (US 2021/0272897) hereinafter “Wang” and Haraguchi et al. (US 2021/0050410) hereinafter “Haraguchi” and in further view of Yu et al. (US 10283473) hereinafter “Yu”.
Regarding claim 2, the combination of Chen, Kim, Kim2, Wang and Haraguchi teaches all of the elements of the claimed invention as stated above.
Chen further teaches where the capacitor (Item 106) further comprises electrical contacts (Items 114) electrically coupling the plurality of capacitor cells (Items 112) to the first redistribution layer (Item 1041 and other BEOL structures within 104).
Chen does not explicitly teach where the electrical contacts are second bumps.
Yu teaches where a capacitor (Item 180) is electrically connected to a redistribution layer (Item 160) by electrical contacts (Item 190), where the electrical contacts are solder bumps ( Yu Column 11, Lines 34-36).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the electrical contacts be second bumps because solder bumps are known to electrically connect a capacitor die to a redistribution layer (Yu Column 11, Lines 19-21 and 34-36).
Regarding claim 3, Chen further teaches where the capacitor (Item 106; silicon when combined with Kim as stated in the rejection of claim 1 above) further comprises a wiring structure (Item 108) electrically coupling the plurality of capacitor cells (Items 112) to the redistribution layer (Item 104).
When the second bump structure (as taught by Yu in the rejection of claim 2 above) is included in the structure of Chen the wiring structure will electrically couple the capacitor cells to the second bump structure.
When the first conductive via taught by Kim2 is included in the structure of Chen as stated in the rejection of claim 1 above, the wiring structure will be electrically coupled to the first conductive via.
Regarding claim 11, Fig. 6 of Chen teaches a semiconductor package structure, comprising: a first redistribution layer (Item 1041 and other BEOL structures within 104; Paragraph 0056); a semiconductor die (Item 20) disposed over the first redistribution layer (Item 1041 and other BEOL structures within 104); and a capacitor (Item 106) disposed below the first redistribution layer (Item 1041 and other BEOL structures within 104) and electrically coupled to the semiconductor die (Item 20) through the first redistribution layer (Item 1041 and other BEOL structures within 104), wherein the capacitor comprises: a substrate (Item 102) having a first surface and a second surface opposite thereto; a plurality of capacitor cells (Item 112) extending from the first surface of the substrate (Item 102) toward a second surface of the substrate (Item 102); a first bump structure (Item 126) disposed over the first surface of the substrate (Item 102) and electrically coupled to the plurality of capacitor cells (Item 112); an electrical contacts (Items 114) disposed over the second surface of the substrate (Item 102) and electrically coupled to the first redistribution layer (Item 1041 and other BEOL structures within 104); and a conductive layer (Item 108) in a bottom portion of the capacitor (Item 102) and electrically coupled to the plurality of capacitor cells (Items 112).
Chen does not explicitly teach where the capacitor is a silicon capacitor nor where the silicon capacitor comprises a semiconductor substrate having a first surface and a second surface opposite thereto.
Kim teaches where a deep trench capacitor can be a higher density silicon capacitor (Paragraph 0033) using a silicon substrate (Item 173).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the capacitor of Chen be a silicon capacitor, where the silicon capacitor comprises a semiconductor substrate having a first surface and a second surface opposite thereto because a silicon capacitor comprising a semiconductor substrate is known to be used in as a capacitor embedded in a package substrate on which an integrated circuit is mounted (Kim Paragraph 0027).
Chen does not explicitly teach where the electrical contacts is second bump structure.
Yu teaches where a capacitor (Item 180) is electrically connected to a redistribution layer (Item 160) by electrical contacts (Item 190), where the electrical contacts are solder bumps ( Yu Column 11, Lines 34-36).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the electrical contact of Chen be a second bump structure because solder bumps are known to electrically connect a capacitor die to a redistribution layer (Yu Column 11, Lines 19-21 and 34-36).
Chen does not teach a first conductive via extending between the first bump structure to the second bump structure, through the semiconductor substrate, and through the plurality of capacitor cells, wherein the first conductive via is electrically coupled to the first bump structure to the second bump structure.
Fig. 3A of Kim2 teaches a first conductive via (Item 318) extending through a substrate (Item 320A) and through a plurality of capacitor cells (Items 302 and 304), where the first conductive via (Item 318) electrically connects a trace present on a top of the substrate (Item 320A) to a trace on a bottom of the substrate (Item 320A).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a first conductive via extending between the first bump structure to the second bump structure, through the semiconductor substrate, and through the plurality of capacitor cells, because a conductive via extending through the substrate and plurality of capacitor cells is known to provide electrical coupling such that an electrical signal can be transmitted from electrical components on one side of the substrate to electrical components on the other side of the substrate (Kim2 Paragraph 0036).
When the first conductive via taught by Kim2 is included in the structure of Chen as stated above the first conductive via will be electrically coupled to the first bump structure to the second bump structure.
Chen does not teach a dielectric layer extending through the semiconductor substrate and covering sidewalls of the conductive via.
Fig. 3A of Kim2 further teaches a dielectric layer (Item 320B; Paragraph 0035) extending through a substrate (Item 322) and covering sidewalls of a conductive via (Item 318).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a dielectric layer extending through the semiconductor substrate and covering sidewalls of the conductive via because the dielectric layer electrically and physically isolates a first electrode of a first capacitor and a second electrode of a second capacitor from a through substrate via (Kim2 Paragraphs 0035 and 0041).
Chen does not teach where the silicon capacitor is not entirely covered by the semiconductor die in a normal direction of the substrate.
Fig. 2F of Wang teaches where, in a semiconductor package structure, a capacitor (Item 216; Paragraph 0034) is not entirely covered by a semiconductor die (Item 208; labeled in Fig. 2F) in a normal direction of a substrate (Item 212).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the silicon capacitor not be entirely covered by the semiconductor die in a normal direction of the substrate because this allows for the design of the package to be more flexible (Wang Paragraph 0039). Further, the choice of location of the capacitor is a design choice which is rendered obvious as it is recognized as a mere rearrangement of parts (MPEP 2144; See also In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.) and In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice)).
Chen does not teach where the conductive layer is between the plurality of capacitor cells and the dielectric layer, and the dielectric layer extends along the bottom of the capacitor cells.
Fig. 15 of Haraguchi teaches a semiconductor package structure where more than one capacitor is stacked on each other, where a via (Item 10) extends through the stack, where a conductive layer (Item 2-1) makes electrical contact with an upper capacitor (Item 30-1), and where a dielectric layer (Lower Item 3) extends along the bottom of the capacitor (Item 30-1) such that the conductive layer (Item 2-1) is between the capacitor (Item 30-1) and the dielectric layer (Lower Item 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the conductive layer be between the plurality of capacitor cells and the dielectric layer, and the dielectric layer extends along the bottom of the capacitor cells because the dielectric layer electrically separates the conductive layer from other elements in the package while allowing the conductive layer to be electrically connected to the capacitor cell (Haraguchi Paragraph 0091). This configuration when combined with Chen above, also allows for the first conductive via to be electrically connected to elements below the capacitor without being electrically connected with the capacitor.
Regarding claim 12, Chen further teaches where the capacitor (Item 106; silicon when combined with Kim as stated in the rejection of claim 11 above) further comprises a wiring structure (Item 108) disposed between the electrical contacts (Items 114; second bump structure when combined with Yu as stated in the rejection of claim 11 above) and the substrate (Item 102; semiconductor substrate when combined with Kim as stated in the rejection of claim 11 above).
Regarding claim 14, Figs. 5 and 6 of Chen further teaches wherein the capacitor (Item 106; silicon capacitor when combined with Kim as stated in the rejection of claim 11 above) further comprises a second conductive via (Item 124) disposed between the substrate (Item 102; semiconductor substrate when combined with Kim as stated in the rejection of claim 11 above) and the first bump structure (Item 126).
Regarding claim 16, Fig. 6 of Chen further teaches a substrate (Item 30) disposed below the capacitor (Item 106; silicon when combined with Kim as stated in the rejection of claim 11 above), wherein the capacitor (Item 106) is electrically coupled to the substrate (Item 30) through the first bump structure (Item 126); and a plurality of conductive terminals (Item 130) adjacent to the capacitor (Item 106) and electrically coupling the first redistribution layer (Item 1041 and other BEOL structures within 104) to the substrate (Item 30).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2022/0238430) hereinafter “Chen” (Chen is eligible as prior art based upon the effective filing date of application 17721675 which has an effective filing date of 06/11/2021 based on provisional application 63/209923 and an effective filing date of 10/30/2020 based on the grandparent application 17/085770) in view of Kim et al. (US 2021/0273042) hereinafter “Kim”, Kim et al. (US 2022/0223585) hereinafter “Kim2”, Wang et al. (US 2021/0272897) hereinafter “Wang” and Haraguchi et al. (US 2021/0050410) hereinafter “Haraguchi” and in further view of Kang et al. (US 2019/0181217) hereinafter “Kang”.
Regarding claim 7, the combination of Chen, Kim, Kim2, Wang and Haraguchi teaches all of the elements of the claimed invention as stated above except where a top portion of the plurality of capacitor cells is disposed in the semiconductor substrate, and a bottom portion of the plurality of a capacitor cells is disposed below the semiconductor substrate.
Kang further teaches where a top portion of the plurality of capacitor cells is disposed in the semiconductor substrate (Paragraph 0019), and a bottom portion of the plurality of a capacitor cells is disposed below the semiconductor substrate.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a top portion of the plurality of capacitor cells is disposed in the semiconductor substrate, and a bottom portion of the plurality of a capacitor cells is disposed below the semiconductor substrate because a deep trench silicon capacitor taught by Kang is known to alleviate stress applied to a wafer in which the capacitor is included (Kang Paragraph 0050).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2022/0238430) hereinafter “Chen” (Chen is eligible as prior art based upon the effective filing date of application 17721675 which has an effective filing date of 06/11/2021 based on provisional application 63/209923 and an effective filing date of 10/30/2020 based on the grandparent application 17/085770) in view of Kim et al. (US 2021/0273042) hereinafter “Kim”, Kim et al. (US 2022/0223585) hereinafter “Kim2”, Wang et al. (US 2021/0272897) hereinafter “Wang” and Haraguchi et al. (US 2021/0050410) hereinafter “Haraguchi” and in further view of Kang et al. (US 2019/0181217) hereinafter “Kang” and Lin et al. (US 2022/0359374) hereinafter “Lin”.
Regarding claim 8, the combination of Chen, Kim, Kim2, Wang, Haraguchi and Kang teaches all of the elements of the claimed invention except where the bottom portion of the plurality of capacitor cells is electrically coupled to a ground.
Lin teaches where a ground is connected to a bottom portion of a plurality of capacitor cells (Paragraph 0055).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the bottom portion of the plurality of capacitor cells be electrically coupled to a ground because the ground acts a port of the capacitor to prevent noise from effecting other portions of the integrated circuit (Lin Paragraph 0055).
Regarding claim 9, the combination of Chen, Kim, Kim2, Wang, Haraguchi and Kang teaches all of the elements of the claimed invention except where a ground pad is disposed between the first bump structure and the substrate.
Lin teaches where a ground is connected to a bottom portion of a plurality of capacitor cells (Paragraph 0055).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a ground pad disposed between the first bump structure and the substrate because the ground pad acts a port of the capacitor to prevent noise from effecting other portions of the integrated circuit (Lin Paragraph 0055).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2022/0238430) hereinafter “Chen” (Chen is eligible as prior art based upon the effective filing date of application 17721675 which has an effective filing date of 06/11/2021 based on provisional application 63/209923 and an effective filing date of 10/30/2020 based on the grandparent application 17/085770) in view of Kim et al. (US 2021/0273042) hereinafter “Kim”, Kim et al. (US 2022/0223585) hereinafter “Kim2”, Wang et al. (US 2021/0272897) hereinafter “Wang” and Haraguchi et al. (US 2021/0050410) hereinafter “Haraguchi” and in further view of Lin et al. (US 2017/0278832) hereinafter “Lin2”.
Regarding claim 10, the combination of Chen, Kim, Kim2, Wang and Haraguchi teaches all of the elements of the claimed invention as stated above except a second redistribution layer disposed over the semiconductor die; and a molding material disposed between the first redistribution layer and the second redistribution layer and surrounding the semiconductor die.
Fig. 4 of Lin2 further teaches a second redistribution layer (Combination of Items 334 and 336) disposed over a semiconductor die (Item 302); and a molding material (Item 350) disposed between a first redistribution layer (Item 314) and the second redistribution layer (Combination of Items 334 and 336) and surrounding the semiconductor die (Item 302).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a second redistribution layer disposed over the semiconductor die; and a molding material disposed between the first redistribution layer and the second redistribution layer and surrounding the semiconductor die because the second redistribution layer allows for additional die to be placed above the semiconductor die and still be electrically connected to the substrate (Lin2 Paragraph 0045) while the molding material electrically isolates the semiconductor die from the surrounding conductive traces (Lin2 Paragraph 0045).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2022/0238430) hereinafter “Chen” (Chen is eligible as prior art based upon the effective filing date of application 17721675 which has an effective filing date of 06/11/2021 based on provisional application 63/209923 and an effective filing date of 10/30/2020 based on the grandparent application 17/085770) in view of Kim et al. (US 2021/0273042) hereinafter “Kim”, Kim et al. (US 2022/0223585) hereinafter “Kim2”, Wang et al. (US 2021/0272897) hereinafter “Wang”, Haraguchi et al. (US 2021/0050410) hereinafter “Haraguchi” and Yu et al. (US 10283473) hereinafter “Yu” and in further view of Lin et al. (US 2022/0359374) hereinafter “Lin”.
Regarding claim 15, the combination of Chen, Kim, Kim2, Wang, Haraguchi and Yu teaches all of the elements of the claimed invention except where the plurality of capacitor cells are electrically coupled to a ground on the first surface of the semiconductor substrate.
Lin teaches where a ground is connected to a plurality of capacitor cells (Paragraph 0055).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of capacitor cells are electrically coupled to a ground on the first surface of the semiconductor substrate because the ground acts a port of the capacitor to prevent noise from effecting other portions of the integrated circuit (Lin Paragraph 0055).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2022/0238430) hereinafter “Chen” (Chen is eligible as prior art based upon the effective filing date of application 17721675 which has an effective filing date of 06/11/2021 based on provisional application 63/209923 and an effective filing date of 10/30/2020 based on the grandparent application 17/085770) in view of Kim et al. (US 2021/0273042) hereinafter “Kim”, Kim et al. (US 2022/0223585) hereinafter “Kim2”, Wang et al. (US 2021/0272897) hereinafter “Wang” and Haraguchi et al. (US 2021/0050410) hereinafter “Haraguchi” and in further view of Lin et al. (US 2017/0278832) hereinafter “Lin2”.
Regarding claim 17, Figs. 3 and 6 of Chen teaches a semiconductor package structure, comprising: a first package structure comprising: a first redistribution layer (Item 1041 and other BEOL structures within 104); a semiconductor die (Item 20) disposed over the first redistribution layer; a capacitor (Item 106) disposed below the first redistribution layer (Item 1041 and other BEOL structures within 104) and electrically coupled to the semiconductor die (Item 20), where the capacitor (Item 106) comprises: a substrate (Item 102); and a plurality of capacitor cells (Item 112) embedded in the substrate (Item 102); and a bump structure (Item 126) disposed below the capacitor (Item 106); and a conductive layer (Item 108) in a bottom portion of the capacitor (Item 102) and electrically coupled to the plurality of capacitor cells (Items 112).
Chen does not explicitly teach where the capacitor is a silicon capacitor nor where the substrate is a semiconductor substrate.
Kim teaches where a deep trench capacitor can be a higher density silicon capacitor (Paragraph 0033) using a silicon substrate (Item 173).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the capacitor of Chen be a silicon capacitor, where the silicon capacitor comprises a semiconductor substrate because a silicon capacitor comprising a semiconductor substrate is known to be used in as a capacitor embedded in a package substrate on which an integrated circuit is mounted (Kim Paragraph 0027).
Chen does not teach a second redistribution layer disposed over the semiconductor die.
Fig. 4 of Lin2 further teaches a second redistribution layer (Combination of Items 334 and 336) disposed over a semiconductor die (Item 302).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a second redistribution layer disposed over the semiconductor die because the second redistribution layer allows for additional die to be placed above the semiconductor die and still be electrically connected to the substrate (Lin2 Paragraph 0045).
Chen does not teach a conductive via extending through the semiconductor substrate and through the plurality of capacitor cells nor where the bump structure is electrically coupled to the conductive via.
Fig. 3A of Kim2 teaches a conductive via (Item 318) extending through a substrate (Item 320A) and through a plurality of capacitor cells (Items 302 and 304), where the first conductive via (Item 318) electrically connects a trace present on a top of the substrate (Item 320A) to a trace on a bottom of the substrate (Item 320A).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a conductive via extending through the semiconductor substrate and through the plurality of capacitor cells, where the bump structure is electrically coupled to the conductive via because a conductive via extending through the substrate and plurality of capacitor cells is known to provide electrical coupling such that an electrical signal can be transmitted from electrical components on one side of the substrate to electrical components on the other side of the substrate (Kim2 Paragraph 0036).
Chen does not teach a dielectric layer extending through the semiconductor substrate and covering sidewalls of the conductive via.
Fig. 3A of Kim2 further teaches a dielectric layer (Item 320B; Paragraph 0035) extending through a substrate (Item 322) and covering sidewalls of a conductive via (Item 318).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a dielectric layer extending through the semiconductor substrate and covering sidewalls of the conductive via because the dielectric layer electrically and physically isolates a first electrode of a first capacitor and a second electrode of a second capacitor from a through substrate via (Kim2 Paragraphs 0035 and 0041).
Chen does not teach where the silicon capacitor is not entirely covered by the semiconductor die in a normal direction of the substrate.
Fig. 2F of Wang teaches where, in a semiconductor package structure, a capacitor (Item 216; Paragraph 0034) is not entirely covered by a semiconductor die (Item 208; labeled in Fig. 2F) in a normal direction of a substrate (Item 212).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the silicon capacitor not be entirely covered by the semiconductor die in a normal direction of the substrate because this allows for the design of the package to be more flexible (Wang Paragraph 0039). Further, the choice of location of the capacitor is a design choice which is rendered obvious as it is recognized as a mere rearrangement of parts (MPEP 2144; See also In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.) and In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice)).
Chen does not teach where the conductive layer is between the plurality of capacitor cells and the dielectric layer, and the dielectric layer extends along the bottom of the capacitor cells.
Fig. 15 of Haraguchi teaches a semiconductor package structure where more than one capacitor is stacked on each other, where a via (Item 10) extends through the stack, where a conductive layer (Item 2-1) makes electrical contact with an upper capacitor (Item 30-1), and where a dielectric layer (Lower Item 3) extends along the bottom of the capacitor (Item 30-1) such that the conductive layer (Item 2-1) is between the capacitor (Item 30-1) and the dielectric layer (Lower Item 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the conductive layer be between the plurality of capacitor cells and the dielectric layer, and the dielectric layer extends along the bottom of the capacitor cells because the dielectric layer electrically separates the conductive layer from other elements in the package while allowing the conductive layer to be electrically connected to the capacitor cell (Haraguchi Paragraph 0091). This configuration when combined with Chen above, also allows for the first conductive via to be electrically connected to elements below the capacitor without being electrically connected with the capacitor.
Regarding claim 18, the combination of Chen, Kim, Kim2, Wang, Haraguchi and Lin2 teaches all of the elements of the claimed invention as stated above.
Chen does not teach wherein the first package structure further comprises: a conductive pillar disposed between the first redistribution layer and the second redistribution layer and adjacent to the semiconductor die; and a molding material surrounding the semiconductor die and the conductive pillar.
Fig.4 of Lin2 further teaches wherein the first package structure further comprises: a conductive pillar (Item 322) disposed between a first redistribution layer (Combination of Items 314 and 318) and a second redistribution layer (Item 418) and adjacent to a semiconductor die (Item 302); and a molding material (Item 350) surrounding the semiconductor die (Item 302) and the conductive pillar (Item 322).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first package structure further comprises: a conductive pillar disposed between the first redistribution layer and the second redistribution layer and adjacent to the semiconductor die; and a molding material surrounding the semiconductor die and the conductive pillar because the conductive pillar allows for additional die to be placed above the semiconductor die and still be electrically connected to the substrate (Lin2 Paragraph 0045) while the molding material electrically isolates the semiconductor die from the surrounding conductive pillars (Lin2 Paragraph 0045)
Regarding claim 19, the combination of Chen, Kim, Kim2, Wang, Haraguchi and Lin2 teaches all of the elements of the claimed invention as stated above.
Chen does not teach a second package structure disposed over the second redistribution layer.
Fig.4 of Lin2 further teaches a second package structure (Combination of Items 404 and 402) disposed over the second redistribution layer (Item 418).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a second package structure disposed over the second redistribution layer because the second package will include additional die to be placed above the semiconductor die which will still be electrically connected to the substrate (Lin2 Paragraph 0045).
Regarding claim 20, Fig. 5 and 6 of Chen further teaches a substrate (Item 30) disposed below the first package structure and in contact with the bump structure (Item 126).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2022/0238430) hereinafter “Chen” (Chen is eligible as prior art based upon the effective filing date of application 17721675 which has an effective filing date of 06/11/2021 based on provisional application 63/209923 and an effective filing date of 10/30/2020 based on the grandparent application 17/085770) in view of Kim et al. (US 2021/0273042) hereinafter “Kim”, Kim et al. (US 2022/0223585) hereinafter “Kim2”, Wang et al. (US 2021/0272897) hereinafter “Wang” and Haraguchi et al. (US 2021/0050410) hereinafter “Haraguchi” and in further view of Gardner et al. (US 2019/0006334) hereinafter “Gardner”.
Regarding claim 22, the combination of Chen, Kim, Kim2, Wang and Haraguchi teaches all of the elements of the claimed invention as stated above except where the interlayer dielectric layer is formed of a high-k dielectric material.
Gardner teaches where a dielectric layer of a trench capacitor is a high-k dielectric material (Paragraph 0036).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the interlayer dielectric layer be formed of a high-k dielectric material because a high-k dielectric material is known to separate top and bottom electrodes of a capacitor and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Response to Arguments
Applicant’s arguments, see Applicant’s REMARKS, filed 03/04/2026, with respect to the rejection(s) of claim(s) 1, 11 and 17 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Haraguchi.
Conclusion
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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