Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-9 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Liang et al., US 2022/0216154 in view of Shastri et al., US 2006/0177173.
Regarding claims 1-2 and 6, Liang discloses (fig. 3 and related text) an apparatus comprising: an assembly comprising a substrate (302), one or more dies (310(110a-c)), and a thin-film interconnect structure (102); wherein the thin-film interconnect structure is arranged between the substrate (302) and the one or more dies (110a-110c), and comprises one or more polymeric layers ([0036], polymer base material) and conductive plating (305/307 conductive layers), wherein the thin film interconnect structure is configured to be bonded/connected as a standalone block (paragraphs [0019], [0041], [0042], clearly describe wiring substrate 102 as separate structure, i.e. standalone that is eventually connected/bonded to 302 via micro bumps 104), to the top surface substrate (302) via micro bumps (104, [0021]).
Liang does not disclose at least one optical tile mounted to a top surface of the substrate.
Shastri discloses (fig. 8 and related text) the use at one optical tile/element (22) mounted to a top surface of the substrate to provide accurate passive alignment between various CMOS based electronic ICs [0029].
Liang and Shastri are analogous art because they both are directed to apparatus with thin film interconnect structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liang with the specified features of Shastri because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Liang to include the optical tile/element as taught by Shastri order to provide accurate passive alignment between various CMOS based electronic ICs [0029].
The limitations “plating”, “the thin-film interconnect structure is provided to the substrate prior to providing the one or more dies to the thin-film interconnect structure” or “the thin-film interconnect structure is fabricated from a panel that is divided into a plurality of thin-film interconnect structures” are not given patentable weight because it is considered to be a product-by-process claim. “[E]ven though product-by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding claim 3, Liang as modified by Shastri discloses the thin-film interconnect structure includes one or more thin-film capacitors ([0030]).
Regarding claim 5, Liang as modified by Shastri discloses the assembly is selected from a group consisting of an application-specific integrated circuit (GPS, [0024].
Regarding claim 7, Liang as modified by Shastri discloses the substrate includes an organic substrate (polymer base materials [0036]).
Regarding claims 8 and 12, Liang discloses (fig. 3 and related text) an apparatus comprising: a thin-film interconnect structure (102) that comprises one or more polymeric layers (polymer based materials [0020]) and conductive plating (305/307, conductors); a first surface (upper surface of 102) of the thin-film interconnect structure being configured to receive one or more dies (110a-c); and a second surface (bottom surface of 102) of the thin-film interconnect structure (102) being configured to be bonded/connected to a top surface of a substrate (302) via micro bumps (104, [0021]), wherein the thin-film interconnect structure (102) is configured to be bonded/connected to the top surface of the substrate (302) as a standalone block (paragraphs [0019], [0041], [0042], clearly describe wiring substrate 102 as separate structure, i.e. standalone that is eventually connected/bonded to 302 via micro bumps 104).
Liang does not disclose at least one optical tile mounted to a top surface of the substrate.
Shastri discloses (fig. 8 and related text) the use at one optical tile/element (22) mounted to a top surface of the substrate to provide accurate passive alignment between various CMOS based electronic ICs [0029].
Liang and Shastri are analogous art because they both are directed to apparatus with thin film interconnect structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liang with the specified features of Shastri because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Liang to include the optical tile/element as taught by Shastri order to provide accurate passive alignment between various CMOS based electronic ICs [0029].
The limitation “plating” or the thin-film interconnect structure is fabricated from a panel that is divided into a plurality of thin-film interconnect structures” are not given patentable weight because it is considered to be a product-by-process claim. “[E]ven though product-by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding claim 9, Liang as modified by Shastri discloses the thin-film interconnect structure includes one or more thin-film capacitors ([0030]).
Regarding claim 11, Liang as modified by Shastri discloses an assembly comprising the thin-film interconnect structure, the one or more dies, and the substrate, and wherein the assembly is selected from a group of an application-specific integrated circuit (GPS, [0024]).
Claim(s) 4, 10, are rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Shastri and in further view of Schiek et al., US 2021/0075399.
Regarding claims 4 and 10, Liang as modified by Shastri does not disclose the thin-film interconnect structure includes one or more power management dies.
Schiek discloses (fig. 4 and related text) a thin-film interconnect structure (ML1, ML2) includes one or more thin-film capacitors (MIM/IND, capacitor/inductor along with other circuit function as power regulation/management) in order to provide a hybrid filter having a band pass function (refer to the abstract).
Liang as modified by Shastri and Schiek are analogous art because they both are directed to electronic circuit and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liang with the specified features of Schiek because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Liang to include the capacitor/inductor as taught by Schiek in order to provide a hybrid filter having a band pass function (refer to the abstract).
Claim(s) 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Shastri.
Regarding claims 13-14, Liang as modified by Shastri does not explicitly disclose the thin-film interconnect structure includes five or more polymeric layers or the first surface has a first pad pitch of at least 10 µm or the second surface has a second pad pitch of at least 100 µm.
Parameters such as number of layers or pad pitch size in the art of semiconductor process are subject to routine experimentation and optimization to achieve the desired device characterization during fabrication.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize an appropriate number of polymeric layers or pad pitch size requirements of the particular design, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. /n re Aller, 105 USPQ 233.
Claim(s) 15-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Shastri and in further view of Yang et al., US 2018/0269181.
Regarding claim 15, Liang discloses (figs. 1-2 and related text) a method comprising: fabricating, as a standalone block (paragraphs [0019], [0041], [0042], clearly describe wiring substrate 102 as separate structure, i.e. standalone that is eventually connected/bonded to 302 via micro bumps 104), a thin film interconnect structure comprising polymeric layers [0020] bonding/connecting the thin-film interconnect structure (102) onto a top surface a substrate (302) via micro bumps (302), and providing one or more dies (110a-c) onto the thin-film interconnect structure (102).
Liang does not explicitly disclose conductive plating or mounting at least one optical tile to a top surface of the substrate.
Shastri discloses (fig. 8 and related text) the use at one optical tile/element (22) mounted to a top surface of the substrate to provide accurate passive alignment between various CMOS based electronic ICs [0029].
Liang and Shastri are analogous art because they both are directed to apparatus with thin film interconnect structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liang with the specified features of Shastri because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Liang to include the optical tile/element as taught by Shastri order to provide accurate passive alignment between various CMOS based electronic ICs [0029].
Yang discloses (fig. 1 and related text) forming conductive signal traces (54) by plating [0024] in order to design electronic devices that can be manufactured using less expensive components and streamlined manufacturing process [0026].
Liang, Shastri and Yang are analogous art because they both are directed to electronic packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liang with the specified features of Yang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Liang to include the plating process as taught by Yang in order to design electronic devices that can be manufactured using less expensive components and streamlined manufacturing process [0026].
Regarding claim 16, Liang as modified by Shastri does not explicitly disclose bonding the thin-film interconnect structure to the substrate prior to providing the one or more dies to the thin-film interconnect structure.
Yang discloses (figs. 3a-3d and related text) the thin-film interconnect structure (170) is bonded/connected to the substrate (160) prior to providing the one or more dies (124a/124b) to the thin-film interconnect structure (170) in order to design electronic devices that can be manufactured using less expensive components and streamlined manufacturing process [0026].
Liang, Shastri and Yang are analogous art because they both are directed to electronic packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liang with the specified features of Yang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Liang to include the process step as taught by Yang in order to design electronic devices that can be manufactured using less expensive components and streamlined manufacturing process [0026].
Regarding claim 17, Liang as modified by Shastri and Yang disclose the thin-film interconnect structure includes one or more thin-film capacitors (Liang, [0030]).
Regarding claim 20, Liang as modified by Shastri and Yang discloses providing one or more of the micro bumps (308), to a surface of the thin-film interconnect structure (Liang, refer to [0042]).
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Liang, Shastri in view of Yang and in further view Schiek.
Regarding claim 18, Liang as modified by Shastri and Yang does not disclose the thin-film interconnect structure includes one or more power management dies.
Schiek discloses (fig. 4 and related text) a thin-film interconnect structure (ML1, ML2) includes one or more thin-film capacitors (MIM/IND, capacitor/inductor along with other circuit function as power regulation/management) in order to provide a hybrid filter having a band pass function (refer to the abstract).
Liang, Shastri, Yang and Schiek are analogous art because they both are directed to electronic circuit and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liang, Shastri and Yang with the specified features of Schiek because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Liang, Shastri and Yang to include the capacitor/inductor as taught by Schiek in order to provide a hybrid filter having a band pass function (refer to the abstract).
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Liang and Shastri in view of Yang et al., and in further view of Patil et al., US 2021/0272931.
Regarding claim 19, Liang as modified by Shastri and Yang does not explicitly disclose obtaining the thin-film interconnect structure by dividing a panel into a plurality of thin-film interconnect structures.
Patil discloses ([0086] and related figures) obtaining the thin-film interconnect structure by dividing a panel into a plurality of thin-film interconnect structures [0086] in order to design an interconnect structure that enables a small package and compact form and also providing high input/output(I/O) [0023].
Liang, Shastri Yang and Patil are analogous art because they both are directed to electronic circuit and one of ordinary skill in the art would have had a reasonable expectation of success to modify Liang, Shastri and Yang with the specified features of Patil because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Liang, Shastri and Yang to include the process the interconnect structure as taught by Patil in order to design an interconnect structure that enables a small package and compact form and also providing high input/output(I/O) [0023].
Response to Arguments
Applicant's arguments filed on 01/202026 have been fully considered but they are not persuasive. Applicant argues that no reference alone or in combination teaches, suggests or discloses a “thin film interconnect structure” that is “configured to be bonded as a standalone block to the top surface of the substrate via micro bumps”. This argument is not persuasive because Liang clearly discusses in paragraphs [0019], [0041], [0042], clearly describe wiring substrate 102 as separate structure, i.e. standalone that is eventually connected/bonded to 302 via micro bumps 104. Therefore, this particular limitation is clearly disclosed by Liang.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM.
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/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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