DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Group I (claims 1-15) in the reply filed on 11/10/2025 is acknowledged.
Claim Objections
Claims 2 and 15 are objected to because of the following informalities:
Claim 2 recites the limitation “the interconnects” in line 4. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the interconnects” (as recited in line 4) is:
“the first interconnects” (emphasis added).
Claim 15 recites the limitation “the IC dies” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the IC dies” (as recited in line 2) is:
“the one or more IC dies” (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (U.S 2018/0331087 A1).
As to claim 1, Lee et al. disclose in Fig. 3 a microelectronic assembly, comprising:
a first integrated circuit (IC) die (“first semiconductor chip” 10) having first bond-pads (12a, 12b) on a first surface (bottom surface of 10) (Fig. 3, para. [0016]-[0018]);
an organic dielectric material (“second encapsulation member” 50, para. [0027]) in contact with the first surface (bottom surface of 10) (Fig. 3, para. [0027]);
second bond-pads (“bump pads” 62) on a second surface (bottom surface) of the organic dielectric material (“second encapsulation member” 50) opposite to the first surface (bottom surface of 10) (Fig. 3, para. [0029]-[0030]);
through-dielectric vias (TDVs) (“mold vias” 60) in the organic dielectric material (“second encapsulation member” 50) between the first bond-pads (12a, 12b) and the second bond-pads (“bump pads” 62), wherein the TDVs (“mold vias” 60) are in direct contact with the first bond-pads (12a, 12b) and the second bond-pads (“bump pads” 62) (Fig. 3, para. [0028]-[0029]);
a second IC die (“second semiconductor chip” 30) embedded in the organic dielectric material (“second encapsulation member” 50) and coupled to the first bond-pads (12a, 12b) by first interconnects (“first coupling members” 40) (Fig. 3, para. [0022]-[0023], [0026]); and
a package substrate (80) coupled to the second bond-pads (“bump pads” 62) by second interconnects (“second coupling members” 70) (Fig. 3, para. [0030]).
As to claim 2, as applied to claim 1 above, Lee et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein: the first bond-pads (12a, 12b) comprise a first subset of bond-pads (12b) and a second subset of bond-pads (12a), the TDVs (“mold vias” 60) are in direct contact with the first subset of bond-pads (12b), and the first interconnects (“first coupling members” 40) between the first IC die (“first semiconductor chip” 10) and the second IC die (“second semiconductor chip” 30) are in direct contact with the second subset of bond-pads (12a) (see Fig. 3).
As to claim 3, as applied to claims 1 and 2 above, Lee et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein: the bond-pads in the first subset (12b) are spaced apart according to a first pitch, the bond-pads in the second subset (12a) are spaced apart according to a second pitch, and the first pitch is larger than the second pitch (Fig. 3).
As to claim 4, as applied to claims 1 and 2 above, Lee et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein: the bond-pads in the first subset (12b) are larger than the bond-pads in the second subset (12a) (Fig. 3).
As to claim 5, as applied to claim 1 above, Lee et al. disclose in Fig. 3 all claimed limitations including the assembly further comprising an underfill material (see underfill material between dies/chips 10 and 30, Fig. 3) in the organic dielectric material (“second encapsulation member” 50) between the first IC die (“first semiconductor chip” 10) and the second IC die (“second semiconductor chip” 30) (Fig. 3).
As to claim 6, as applied to claim 1 above, Lee et al. disclose in Fig. 3 all claimed limitations including the assembly further comprising: a third IC die (see a second “semiconductor chip” 30, Fig. 3) embedded in the organic dielectric material (50), wherein the second IC die (“second semiconductor chip” 30) is coupled to the third IC die (see a second “semiconductor chip” 30, Fig. 3) by third interconnects (“support members” 70) (Fig. 3, para. [0030]).
As to claim 7, as applied to claim 1 above, Lee et al. disclose in Fig. 3 all claimed limitations including the assembly further comprising: a polyimide layer (“first encapsulation member” 20 can be “epoxy molding compound” which is a polyimide layer, para. [0021]), wherein: a first portion (first top portion) of the organic dielectric material (50) is in contact with the first surface (bottom surface of 10), the polyimide layer (“first encapsulation member” 20) is in contact with the first portion (top portion) of the organic dielectric material (50), and a second portion (second top portion) of the organic dielectric material (50) is in contact with the polyimide layer (“first encapsulation member” 20) (Fig. 3, para. [0039]).
As to claim 8, as applied to claim 1 above, Lee et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein the first surface comprises a polyimide layer (20) in direct contact with the organic dielectric material (50) (Fig. 3).
As to claim 9, Lee et al. disclose in Fig. 3 an interposer, comprising: an organic dielectric material (“second encapsulation member” 50, para. [0027]) having a first surface (top surface of 50) and an opposing second surface (bottom surface of 50) (Fig. 3, para. [0027]); a first plurality of bond-pads) (12a, 12b) on the first surface (top surface of 50) (Fig. 3, para. [0018]); a second plurality of bond-pads (“bump pads” 62) on the second surface (bottom surface of 50) (Fig. 3, para. [0029]); TDVs (“mold vias” 60) between the first plurality of bond-pads (12a, 12b) and the second plurality of bond-pads (“bump pads” 62) (Fig. 3, para. [0028]-[0029]); and one or more IC dies (“second semiconductor chips” 30) in the organic dielectric material (“second encapsulation member” 50) (Fig. 3, para. [0022]-[0023], [0026]), wherein: the first surface (top surface of 50) is in direct contact with another IC die (“first semiconductor chip” 10) (Fig. 3, para. [0017], [0021], [0023]-[0026]), the TDVs (“mold vias” 60) are in direct contact with the first plurality of bond-pads (12a, 12b) and the second plurality of bond-pads (“bump pads” 62) (Fig. 3, para. [0028]-[0029]).
As to claim 10, as applied to claim 9 above, Lee et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein the interposer (Fig. 3) is configured to be coupled to a package substrate (80) through the second plurality of bond-pads (“bump pads” 62) (Fig. 3, para. [0028]-[0029]).
As to claim 11, as applied to claim 9 above, Lee et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein: the first plurality of bond-pads (12a, 12b) comprises a first subset of bond-pads (12b) and a second subset of bond-pads (12a), the first subset of bond-pads (12b) has a first pitch, the second subset of bond-pads (12a) has a second pitch, and the first pitch is different from the second pitch (Fig. 3).
As to claim 12, as applied to claim 9 and 11 above, Lee et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein the second subset of bond-pads (12a) is conductively coupled to the one of more IC dies (30) of the interposer (Fig. 3).
As to claim 13, as applied to claim 9 above, Lee et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein at least one IC die (30) in the one or more IC dies (30) is a bridge die configured to laterally couple two other IC dies (30, 30) attached to the first surface of the interposer (Fig. 3).
As to claim 14, as applied to claim 9 above, Lee et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein: the one or more IC dies (30, 30) include more than one IC die (30), the more than one IC dies (30, 30) are arranged in a stack between the first surface and the second surface of the interposer, and one or more IC dies (30, 30) are in each layer of the stack (Fig. 3).
As to claim 15, as applied to claims 9 and 14 above, Lee et al. disclose in Fig. 3 all claimed limitations including the interposer further comprising TDVs (“mold vias” 60) between the first plurality of bond-pads (12a, 12b) and the one or more IC dies (“second semiconductor chips” 30, 30) in the stack (Fig. 3).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: SHIM et al. (U.S 2020/0161266 A1).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 March 7, 2026