Prosecution Insights
Last updated: May 29, 2026
Application No. 17/842,215

PCB MLCC-INDUCED ACOUSTIC NOISE REDUCTION

Non-Final OA §102§103§112
Filed
Jun 16, 2022
Priority
Feb 18, 2022 — provisional 63/311,581
Examiner
TSO, STANLEY
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Non-Final)
76%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
377 granted / 493 resolved
+8.5% vs TC avg
Strong +34% interview lift
Without
With
+34.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
24 currently pending
Career history
525
Total Applications
across all art units

Statute-Specific Performance

§103
91.2%
+51.2% vs TC avg
§102
6.1%
-33.9% vs TC avg
§112
1.9%
-38.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 493 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant alleges that the word “substantially” in each of claims 2 and 6-8 does not render the claim indefinite under 112. Applicant points to MPEP 2173.05(b) which explains certain instances where the word “substantially” does not render the claim indefinite. However, the Examiner respectfully submits that the instant claims 2 and 6-8, when read in view of the specification, does not reasonably provide a standard for a person of ordinary skill in the art to know when infringement begins. For example, claim 2 recites: “a first magnitude . . . is substantially equal to and opposite from a second magnitude.” Emphasis added. It is not clear where infringement would begin if a user has a first magnitude that is similar to and opposite from a second magnitude. Applicant points to paragraph [0029] which provides an example of how the claimed phrase “is substantially equal to” could be construed to mean “may correspond to approximately 0.00029 mm displacement at 54 Hz.” Emphasis added. The Examiner construes 0.00029 mm displacement at 54 Hz as one example of potential infringement. However, the boundaries of infringement are not clearly established because the specification does not define what is meant by “approximately.” For example, if the displacement is 0.00028 mm, would this infringe? What about 0.00025 mm displacement? 0.00010 mm displacement? A user would not know where infringement begins based on a reading of the claim in view of the specification. Similarly, claim 8 recites “shifting the first signal to be substantially centered around zero volts DC.” Emphasis added. It is not clear where infringement would begin if a user shifts a first signal that is nearly centered around zero volts DC. Applicant points to [0023] which explains that the claimed phrase “substantially centered around zero volts DC” could be construed to mean to “shift a voltage waveform down to be approximately centered around 0 VDR.” Emphasis added. However, the boundaries of infringement are not clearly established because the specification does not define what is meant by “approximately.” A user would not know where infringement begins based on a reading of the claim in view of the specification. Also, the phrase “vibration is substantially equal to” in claim 6 and “vibration to be substantially equal to” in claim 7 is rejected because the specification does not define what is meant by “substantially equal.” A user would not know where infringement begins based on a reading of the claim in view of the specification. For the reasons discussed above, claims 2 and 6-8 stand rejected under 112. The Examiner respectfully submits that this rejection could be traversed by removing the word “substantially” from each of claims 2 and 6-8. Regarding the 102 rejection of claim 1, Applicant alleges that Fujii does not recite each limitation of claim 1. The Examiner respectfully disagrees with this allegation and refers to Fujii, Fig. 1A (annotated) below. PNG media_image1.png 621 811 media_image1.png Greyscale Fujii discloses every limitation of claim 1, as illustrated above. Therefore, claim 1 stands rejected under 102 over Fujii. Applicant also alleges that Applicant’s claims further distinguish over Fujii’s feedback control approach, and that Fujii does not disclose a direct, parallel signal distribution from a common source. The Examiner respectfully disagrees with this allegation and refers to Fujii, Fig. 1A, annotated, above. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2, and 6-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The term “substantially equal to” in each of claims 2 and 6-7 and “substantially centered” in claim 8 is a relative term which renders the claim indefinite. The terms “substantially equal to” and “substantially centered” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In order to expedite prosecution, the terms “substantially equal to” and “substantially centered” are construed as how they might be reasonably interpreted by a person having ordinary skill in the art. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-7 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Fujii” (US 2015/0325376). Regarding claim 1, Fujii anticipates 1. A system comprising: a first capacitor to receive a first signal and disposed on a first side of a printed circuit board (PCB), the first capacitor to generate a first PCB vibration associated with a first vibration phase (Figs. 1A-9, [0004], [0009], [0014], [0046], [0073]; a first multilayer ceramic capacitor (MLCC) is disposed on a PCB, receives a first signal and generates a first PCB acoustic noise vibration with a first vibration phase); an inverter to generate an inverted signal based on the first signal, wherein the inverter directly receives the first signal as an input and outputs the inverted signal having a phase opposite to the first signal (Figs. 1A-9, [0004], [0009], [0014], [0046], [0073]; the output of the first MLCC is electrically connected to the regulator which includes the inverter to generate an inverted signal based on the first signal); and a second capacitor coupled to the inverter to receive the inverted signal directly from the inverter and to generate a second PCB vibration associated with a second vibration phase opposite the first vibration phase, the second PCB vibration opposing the first PCB vibration to reduce an overall PCB vibration (Figs. 1A-9, [0004], [0009], [0014], [0046], [0073]; a second MLCC is electrically connected to the inverter to receive the inverted signal and generates a second PCB vibration phase opposite the first vibration phase to reduce the overall PCB vibration which generates acoustic noise), wherein the first capacitor and the second capacitor both derive their respective signals from a common signal source through different signal paths (Figs. 1A-9, [0004], [0009], [0014], [0046], [0073]; capacitors C1 and C2 both derive their input signals from a common signal source through different signal paths). Regarding claim 2, Fujii anticipates 2. The system of claim 1, wherein a first magnitude associated with the first PCB vibration is substantially equal to and opposite from a second magnitude associated with the second PCB vibration (Figs. 1A-9, [0004], [0009], [0014], [0046], [0073]; the regulator controls the magnitude of the voltage such that the first and second magnitudes are substantially equal. Examiner’s note: see the 112 rejection above for the construction of the limitation “substantially equal to”). Regarding claim 3, Fujii anticipates 3. The system of claim 1, wherein: the first PCB vibration causes the PCB to generate a first audible vibration (Figs. 1A-9, [0004], [0009], [0014], [0046], [0073]; the first PCB vibration causes the PCB to generate a first audible vibration); and the second PCB vibration opposes the first PCB vibration to reduce the first audible vibration (Figs. 1A-9, [0004], [0009], [0014], [0046], [0073]; the second PCB vibration opposes the first PCB vibration to reduce the first audible vibration). Regarding claim 4, Fujii anticipates 4. The system of claim 1, wherein: the PCB includes a rigid PCB attachment point; and the second capacitor is arranged on the PCB with respect to the rigid PCB attachment point to reduce the first PCB vibration (Figs. 1A-9, [0004], [0009], [0014], [0046], [0073]; the second MLCC is arranged on the PCB with respect to a rigid attachment point to reduce the vibration from the first MLCC). Regarding claim 5, Fujii anticipates 5. The system of claim 4, further including: a first plurality of capacitors coupled to the first signal and disposed on the first side of the PCB, the first plurality of capacitors including the first capacitor, the first plurality of capacitors to generate a first group PCB vibration associated with the first vibration phase; and a second plurality of capacitors coupled to the inverted signal and disposed on the first side of the PCB, the second plurality of capacitors including fewer capacitors than the first plurality of capacitors, the second plurality of capacitors including the second capacitor, the second plurality of capacitors to generate a second group PCB vibration associated with the second vibration phase to reduce the first group PCB vibration (Figs. 1A-9, [0004], [0009], [0014], [0046], [0073], [0075]; The above-described voltage smoothing circuit preferably may include the plurality of capacitor C4 and the capacitor C5 as the first multilayer capacitor and the second multilayer capacitor.). Regarding claim 6, Fujii anticipates 6. The system of claim 5, wherein the second plurality of capacitors is arranged on the PCB with respect to the rigid PCB attachment point such that the second group PCB vibration is substantially equal to and opposite from the first group PCB vibration to reduce the first group PCB vibration ( Figs. 1A-9, [0004], [0009], [0014], [0046], [0073], [0075]; the plurality of capacitor C4 and the capacitor C5 as the first multilayer capacitor and the second multilayer capacitor are arranged on the PCB with respect to the rigid PCB attachment point such that the second group PCB vibration is substantially equal to and opposite from the first group PCB vibration to reduce the first group PCB vibration. Examiner’s note: see the 112 rejection above for the construction of the limitation “substantially equal to”). Regarding claim 7, Fujii anticipates 7. The system of claim 5, further including an amplifier circuit coupled to the inverter and the second plurality of capacitors to generate an inverted amplified signal, wherein: the second plurality of capacitors generate the second group PCB vibration based on the inverted amplified signal; and the amplifier circuit is configured to cause the second group PCB vibration to be substantially equal to and opposite from the first group PCB vibration to reduce the first group PCB vibration (Figs. 1A-9, [0004], [0009], [0014], [0046], [0073]; the regulator includes an inverting amplification circuit and the inverting amplification circuit outputs an output voltage with a phase inverted with respect to a phase of an input voltage. Examiner’s note: see the 112 rejection above for the construction of the limitation “substantially equal to”). Regarding claim 9, Fujii anticipates 9. The system of claim 1, wherein the first capacitor and the second capacitor include multilayer ceramic capacitors (Figs. 1A-9, [0004], [0009], [0014], [0046], [0073]; the first capacitor and the second capacitor include multilayer ceramic capacitors). Regarding claim 10, Fujii anticipates 10. The system of claim 1, wherein the first capacitor and the second capacitor include piezoelectric elements (Figs. 1A-9, [0004], [0009], [0014], [0046], [0073]; the first capacitor and the second capacitor include piezoelectric elements). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Fujii in view of “Gardner” (US 8,143,871). Regarding claim 8, Fujii discloses the limitations of claim 1, above. Fujii does not disclose the limitations of claim 8. Gardner discloses 8. The system of claim 1, further including a direct current (DC) removal filter circuit to generate a zero-centered signal by shifting the first signal to be substantially centered around zero volts DC; wherein the inverter generates the inverted signal based on the zero-centered signal (Fig. 4, col. 6, lines 50-57; a DC removal circuit may be used to generate a zero-centered signal. Examiner’s note: see the 112 rejection above for the construction of the limitation “substantially centered”). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Fujii’s system with Gardner’s DC removal circuit in order to produce an output signal that may be configured to buffer and/or amplify this signal, as suggested by Gardner at col. 6, lines 50-57. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANLEY TSO/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Jun 16, 2022
Application Filed
Feb 10, 2023
Response after Non-Final Action
Jun 16, 2025
Non-Final Rejection mailed — §102, §103, §112
Sep 15, 2025
Response Filed
Oct 01, 2025
Final Rejection mailed — §102, §103, §112
Dec 01, 2025
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+34.0%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 493 resolved cases by this examiner. Grant probability derived from career allowance rate.

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