DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/16/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 & 23 have been considered but are moot because the new ground of rejection because the applicant amended independent claims 1, 17 & 19 with newly added limitations, thus moot.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In Claim 9, lines 3, the recitation of “the power amplifier” is not clear because the power amplifier is not clearly defined. It is suggested to change term “the power amplifier” to ---the amplifier circuit---. It is also noted that the term “an amplifier” as cited in Claim 1, if this in the intention then it is suggested to change to ---the amplifier----. See claim 19 for instant, the applicant defined the amplifier is a power amplifier.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 & 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahmed et al., (US 10587226 B2), hereinafter, Ahmed.
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Regarding claim 1:
Ahmed discloses in annotate Fig. 3 (Col. 4, lines 65-55, state “a bipolar junction transistors (BJT)”, an amplifier circuit comprising:
an amplifier having a first stage (stage 310) and a second stage (stage includes transistor 350), each stage including an input and an output, such that the output of the first stage (a node between capacitor 329 and transistor 350) is coupled to the input of the second stage through a DC-block capacitance ( DC block capacitor329); and a first stabilizing circuit (e.g. circuit SB1) implemented on the output side of the second stage (see transistor 350) and a second stabilizing circuit (e.g., circuit 331, it is note that the applicant does not specified first or second stabilizing circuits in this claim) implemented on the input side of the second stage (see terminal 352 of transistor 350) between the DC-block capacitance (capacitor 329) and the input of the second stage, each stabilizing circuit configured to provide stability in operation of the amplifier under a high voltage standing wave ratio condition.
Regarding claim 2:
Ahmed (Fig. 3) discloses the amplifier circuit of claim 1, wherein the second stage (the stage includes transistor 350) is an output stage of a plurality of stages (stages 310 and a stage that include transistor 350) of the amplifier.
Regarding claim 3:
Ahmed (Fig. 3) discloses the amplifier circuit of claim 2, wherein the first stage (stage 310) is a stage immediately preceding the output stage.
Regarding claim 4:
Ahmed (Fig. 3) discloses the amplifier circuit of claim 1, wherein the first stage includes a first amplifier transistor (transistor 320), and the second stage includes a second amplifier transistor (transistor 350), such that the output of the first amplifier transistor (transistor 320) is coupled to the input of the second amplifier transistor (transistor 350).
Regarding claim 5:
Ahmed (Fig. 3) discloses the amplifier circuit of claim 4, wherein each of the first and second amplifier transistors (transistors 320 & 350, (Col. 4, lines 65-55, state “a bipolar junction transistors (BJT)” thus each transistor as shown in Fig. 3 can be a BJT transistor) is implemented as a bipolar-junction transistor having a base as the input and a collector as the output.
Regarding claim 6:
Ahmed (Fig. 3) discloses the amplifier circuit of claim 5, wherein the first stabilizing circuit (circuit SB1 which include inductor and capacitor) includes a limiting circuit (e.g., inductor L2 and capacitor C2) implemented between the collector of the second amplifier transistor (drain/collector transistor 350) and ground.
Regarding claim 7:
Ahmed (Fig. 3) discloses the amplifier circuit of claim 6, wherein the limiting circuit (inductor L2 and capacitor C2) is capable of configured to reduce generation of one or more oscillatory spurs under a high out-of-band voltage standing wave ratio condition.
Regarding claim 14:
Ahmed (Fig. 3) discloses wherein the limiting circuit includes a resistance (536, Fig. 5 of Wilson) and a capacitance (L2) arranged in electrical series between the collector of the second amplifier transistor (transistors 350) and ground (see Fig. 3 of Ahmed).
Regarding claim 15:
Ahmed (Fig. 3) discloses the amplifier circuit of claim 7 wherein the limiting circuit (an arrangement that capacitor L2, Fig. 3 of Ahmed and resistor 536, Fig. 5 of Wilson which having analogous art to the Fig. 13B of the application) is configured to provide a high-pass functionality to limit voltage standing wave ratio for frequencies above a transmit in-band frequency (it is noted that no specific frequencies above a transmit in-band frequency being specified by the applicant).
Regarding claim 16:
Ahmed (Fig. 3) discloses the amplifier circuit of claim 1 wherein the amplifier is a power amplifier (Col. 1, lines 11-12, radio-frequency (RF) amplifiers) .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ahmed in view of Wilson (US 7868698 B2, of record).
Regarding claims 8, 10 & 12:
Ahmed (Fig. 3) discloses the limitations as applied in claim 7 except for a resistance implemented between the collector of the second amplifier transistor and ground; a resistance, an inductance, and a capacitance arranged in electrical series between the collector of the second amplifier transistor and ground.
Wilson (Fig. 5) disclose an amplifier circuit comprising circuit 530 which includes resistor 536 being connected in series with inductor 532 and capacitor 534.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to have modified the circuit of Ahmed to include the resistor 536 as taught by Wilson. Such a modification would have imparted the advantageous benefit of providing dampening to undesired resonance and see Col. 4, lines 22-25, “a low resistance can be provided to the drain of the transistor for the same range of frequencies that the bias network presents a high impedance”.
Accordingly, as an obvious consequence above the combination (Ahmed in view of Wilson) further discloses a resistance (Fig. 5 of Wilson, resistor 172), an inductance (Fig. 3, L2) , and a capacitance (Fig. 3, C2) arranged in electrical series between the collector of the second amplifier transistor and ground.
Insofar regarding claim 9 is understood:
The combination (Ahmed in view of Wilson) discloses the amplifier circuit of claim 8, wherein the resistance (resistor as shown in Fig. 5 of Wilson) which can be selected to limit voltage standing wave ratio across a frequency range associated with operation of the
Regarding claim 11:
The combination (Ahmed in view of Wilson) discloses the amplifier circuit of claim 10 further discloses wherein the resistance, the inductance, and the capacitance are selected (Wilson, Col. 7, lines 15-18, choose appropriate values of the capacitor, inductor and resistor and see Fig. 3a, 3b and 3c) to provide a notch functionality to limit voltage standing wave ratio at an out-of-band spur frequency.
Regarding claim 13:
The combination (Ahmed in view of Wilson) discloses the amplifier circuit of claim 12, further discloses wherein the resistance and the inductance are selected Col. 7, lines 15-18, choose appropriate values of inductor and resistor in accordance with the application in which it is being used) to provide a low-pass functionality to limit voltage standing wave ratio for frequencies below a transmit in-band frequency.
Claims 17, 19-20 & 23 are rejected under 35 U.S.C. 103 as being unpatentable over Ichitsubo et al. (US 20100253435 A1, of record), (hereinafter, Ichitsubo) in view of Ahmed.
Regarding claim 17, Ichitsubo (Figs. 1 & 2) discloses a semiconductor die comprising:
a semiconductor substrate (20 of Fig. 1); and an amplifier circuit (amplifiers as shown in Fig. 2) implemented on the semiconductor substrate except for specific amplifier circuit as cited in the claim 17.
Ahmed (Fig. 3) discloses an amplifier circuit comprising:
an amplifier having a first stage (310) and a second stage (amplifier stage includes transistor 350), each stage including an input and an output, such that the output of the first stage (310) is coupled to the input of the second stage (amplifier stage includes transistor 350) through a DC-block capacitance (329), the amplifier circuit further including
a first stabilizing circuit (SB1) implemented on the output side of the second stage (see transistor 350); and
a second stabilizing circuit (e.g., 331) implemented on the input side of the second stage (see transistor 350) between the DC-block capacitance and the input of the second stage, each stabilizing circuit configured to provide stability in operation of the amplifier under a high voltage standing wave ratio condition.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention was made to have implemented the circuit of as taught by Ahmed on the semiconductor substrate as taught by Ichitsubo for benefits of improving stability, performance and easy integration.
Regarding claim 19:
Ichitsubo (Figs. 1 & 2) discloses a packaged module comprising: a packaging substrate (module substrate 11, Fig. 1) configured to receive a plurality of components; and an amplifier circuit (amplifiers as shown in Fig. 2) implemented on the packaging substrate except for the specific amplifier circuit as cited in claim 19.
Ahmed (Fig. 3) discloses an amplifier circuit comprising:
an amplifier having a first stage (310) and a second stage (a stage includes transistor 350), each stage including an input and an output, such that the output of the first stage (310) is coupled to the input of the second stage (the stage includes transistor 350); the amplifier circuit further including
a first stabilizing circuit (e.g., SB1) implemented on the output side of the second stage (see transistor 350 and
a second stabilizing circuit (e.g., 331) implemented on the input side of the second stage (350), each stabilizing circuit configured to provide stability in operation of the amplifier under a high voltage standing wave ratio condition.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention was made to have implemented the circuit of as taught by Ahmed on the module substrate as taught by Ichitsubo for benefits of improving stability, performance and easy integration.
Regarding claim 20:
The combination discloses the amplifier circuit of claim 19, wherein the amplifier is a power amplifier (Col. 1, lines 11-12, radio-frequency (RF) amplifiers) .
Regarding claim 23:
The combination discloses the packaged module of claim 20, further comprising an output impedance matching (annotated Fig. 3 of Ahmed, O/P MC) network coupled to the output of the second stage.
Conclusion
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/KHIEM D NGUYEN/Examiner, Art Unit 2843