DETAILED ACTION
Claims 1-24 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections/Recommendations
Claim 6 is objected to because of the following informalities:
In line 1, insert a colon after “wherein”.
Claim 8 is objected to because of the following informalities:
In line 9, replace “second first” with --the second--.
Claim 9 is objected to because of the following informalities:
In line 6, delete “and”.
Claim 16 is objected to because of the following informalities:
In line 9, replace “second first” with --the second--.
Claim 24 is objected to because of the following informalities:
In line 7, replace “second first” with --the second--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 7, 15, and 23-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting an essential step, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted step between the blocking and unblocking is transitioning from the second (secure) operational mode to the first operational mode. That is, claim 1 sets forth that prediction is blocked during the second mode while the first count is less than the first history length. Dependent claim 5 merely sets forth unblocking while the first count is less than the first history length. Thus, claim 5 sets forth the prediction being both blocked and unblocked when the first count is too small. It is when the first mode (not the second mode) is operational that the unblocking can occur when the first count is less than the first history length. To unblock during the second mode would defeat the purpose of the blocking. The examiner believes that applicant may have meant for claim 5 to depend on claim 4, as similar, but definite, claims 13 and 21 depend on claims 12 and 20, respectively.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 7, “the prediction table” since there is a first prediction table and a second prediction table.
In claim 15, “the prediction table” since there is a first prediction table and a second prediction table.
In claim 23, “the prediction table” since there is a first prediction table and a second prediction table.
In claim 24, “the first branch prediction, “the second count”, and “the second branch prediction”. It appears this claim should depend on claim 22.
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-24 are rejected under 35 U.S.C. 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Bouzguarrou et al. (US 2023/0385066 A1).
Referring to claim 1, Bouzguarrou has taught an apparatus (FIG.1) comprising:
first circuitry to perform a branch prediction with a first prediction table which corresponds to a first history length (see FIG.1, predictor 46, which includes first prediction table 110 (FIG.3) that corresponds to a first history length of 5 (as shown in FIG.5)), wherein a processor is to execute an instruction based on the branch prediction (this is the purpose of branch prediction - to predict which path of instructions subsequent to a branch will be executed), wherein a lookup of the first prediction table is to be performed with an index and a tag (see FIG.3 and paragraph 76, where an entry is looked up based on part of the lookup value 132 (index) and another part of the lookup value (tag)), and wherein the first history length is a required length of a branch history to determine the index and the tag (from FIGs.3 and 5-6 and paragraphs 98-99, a GHR0 length of 5 branches (since the mode switch) must be reached in order use the GHR0 history to determine the index and the tag 132 to access the table); and
second circuitry (at least FIG.3, 102 and 104) coupled to the first circuitry, the second circuitry to:
detect a first transition of the processor from a first operational mode to a second operational mode which is more secure, relative to the first operational mode (see FIG.7, 202);
based on the first transition, maintain a first count of any respective branches by the processor since the first transition and during the second operational mode (see FIG.7, 206, and FIG.5. When the transition occurs, a counter counts the number of branches encountered since the transition), wherein the second circuitry is to perform one or more increments of the first count each based on a respective branch to be indicated in the first prediction table (from FIGs.5-6 and their descriptions, the counter is incremented for the branches and branches are to be indicated in the prediction table. For instance, when the counter value is 6 as shown in FIG.5, a next branch will cause an increment to the counter and that branch will be indicated by the T0 table); and
during the second operational mode, block the branch prediction while the first count is less than the first history length (see FIGs.5-7 and their descriptions. Table T0 110 is blocked when the first count is less than 5).
With respect to the respective branches being taken branches for which the first count is maintained, this is not patentable for multiple reasons:
First, any combination of taken/not-taken branches can be experienced by Bouzguarrou. In other words, the bits shown in FIG.5 could comprise any combinations of 0s and 1s. FIG.5 shows one example of taken and not-taken branches (corresponding to history bits of 1 and 0, respectively). While the first five branches after the switch are shown to be not-taken (0), not-taken (0), taken (1), not-taken (0), and not-taken (0) (see leftmost five bits in EL1 in FIG.5), one of ordinary skill in the art recognizes that any branch can be taken or not taken depending on system conditions, and all permutations of taken/not-taken results need not be shown to be considered taught by Bouzguarrou. That is, all permutations of 0s and 1s in FIG.5 are within the scope of Bouzguarrou. Thus, when the first five branches after the switch are instead all taken, the count would be 5 and the 5 would be a count of taken branches since the switch. Under this interpretation, the claim is rejected under 102.
Alternatively, since a count reflects both taken and not-taken branches, a count is maintained for taken branches. That is, if the first five in EL1 are as shown in FIG.5, then the counter would have counted 4 for not-taken and 1 for taken. These are effectively added by the counter to realize 5, but there was still a count of 1 just for the taken branch. Under this interpretation, the claim is rejected under 102.
Assuming, arguendo, that Bouzguarrou does not encompass all permutations of taken/not-taken outcomes, Bouzguarrou has not taught that the maintained count is a count of taken branches. However, one of ordinary skill in the art would have recognized that any permutation of taken/not-taken outcomes could occur for a sequence of branches. This is entirely dependent on the program being executed and the conditions in the system. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bouzguarrou such that the maintained count is a count of taken branches. That is, it would be obvious for the number of branches to be taken in a row after the mode switch is five (which would enable T0 based on FIG.5). Under this interpretation, the claim is rejected under 103.
Referring to claim 2, Bouzguarrou, alone or as modified, has taught the apparatus of claim 1, wherein the second circuitry is further to:
detect a condition wherein the first count is equal to or greater than the first history length during the second operational mode (see FIGs.5-7 and their descriptions. When the first count = 5, table T0 is enabled); and
unblock the branch prediction based on the condition (when T0 is enabled, it may make predictions again).
Referring to claim 4, Bouzguarrou, alone or as modified, has taught the apparatus of claim 1, wherein the second circuitry is further to: detect a second transition from the second operational mode to the first operational mode; and unblock the branch prediction based on the second transition (see paragraph 99, which states “all of the tables can be re-enabled if there is a subsequent switch back to the less privileged execution state EL0”).
Referring to claim 5, Bouzguarrou, alone or as modified, has taught the apparatus of claim 1, wherein the second circuitry is to unblock the branch prediction while the first count is less than the first history length (again, from paragraph 99, all tables can be re-enabled if there is a switch back to EL0. Thus, when a switch back to EL0 occurs before count 104 reaches 5, table T0 prediction will be unblocked while the first count is less than the first history length of 5).
Referring to claim 6, Bouzguarrou, alone or as modified, has taught the apparatus of claim 1, wherein
the branch prediction is to be a first branch prediction (the branch prediction by T0 may be called a first branch prediction);
the first circuitry is further to perform a second branch prediction with a second prediction table which corresponds to a second history length which is different than the first history length (from FIG.5, table T1 112 corresponds to a history length of 10, which is different than the first history length of 5. Each of these tables, when enabled, performs branch prediction (as shown in FIG.3)); and
the second circuitry is further to:
based on the first transition, maintain a second count of any respective branches by the processor since the first transition and during the second operational mode (similar to the reasoning given in the rejection of claim 1, a second count (up to 10 branches) for T1 is maintained after the switch to EL1. The count to 5 for T0 may be considered the first count), wherein the second circuitry is to perform one or more increments of the second count each based on a respective branch to be indicated in the second prediction table (this is rejected for similar reasoning given in the rejection of claim 1); and
during the second operational mode, block the second branch prediction while the second count is less than the second history length (see FIGs.5-7 and their descriptions. Table T1 112 is blocked when the first count is less than 10).
With respect to the respective branches being taken branches for which the second count is maintained, this is not patentable for reasons similar to the multiple reasons given in the rejection for claim 1 with respect to the first count (in other words, the taken count is obvious, if not anticipated).
Referring to claim 7, Bouzguarrou, alone or as modified, has taught the apparatus of claim 5, wherein the prediction table is an indirect prediction table (see paragraph 89-90, which refers to indirect prediction performed by a polymorphic predictor 46. Also, branch X and branch Y are each disclosed as having multiple branch target addresses, which means they are indirect branches).
Referring to claim 8, Bouzguarrou, alone or as modified, has taught the apparatus of claim 6, wherein, during the second operational mode, the second circuitry is further to:
detect a first condition wherein the first count is equal to or greater than the first history length during the second operational mode (from FIGs.5-7, a first count reaching 5 is detected);
unblock the first branch prediction based on the first condition (when the first count of 5 is detected, table T0’s prediction is unblocked);
detect a second condition wherein the second count is equal to or greater than second first history length during the second operational mode (from FIGs.5-7, a second count reaching 10 is detected); and
unblock the second branch prediction based on the second condition (when the second count of 10 is detected, table T1’s prediction is unblocked).
Claims 9-16 set forth a method performed by the apparatus of claims 1-8, respectively. Thus, claims 9-16 are rejected for similar reasoning as claims 1-8, respectively.
Claim 17 is mostly rejected for similar reasoning as claim 1. Bouzguarrou has further taught:
a first circuit to decode one or more instructions (FIG.1, decode pipeline stage 10 for decoding instructions fetched by fetch stage 6); and
a second circuit coupled to the first circuit to execute the one or more decoded instructions (FIG.1, at least execution unit 16, which includes ALU24 and FPU 22, and circuit 40).
Claims 18-24 are rejected for similar reasoning as claims 2-8, respectively.
Response to Arguments/Amendments
Based on the amendments, the double-patenting and 101 rejections have been withdrawn.
On page 13 of applicant’s response, applicant argues that “Bouzguarrou is completely silent as to what specifically the above-referenced first predetermined number might be, or how it might actually be determined. Necessarily then, Bouzguarrou must also fail to more particularly teach or suggest (for example) that the first predetermined number might be any required length of a branch history, much less some alleged required length of a branch history to determine an index and a tag with which a given prediction table is to be looked up or otherwise accessed.”
The examiner respectfully disagrees. A count of 5 in FIG.5 of Bouzguarrou corresponds to the amount of history needed to use as an index and tag into the T0 predictor to make a prediction (see the last sentence of paragraph 98 and paragraph 99). From FIG.3, this basically means that GHR0 is five bits in length. The idea is that if you use 5 bits for lookup, you want the 5 bits to correspond to branches encountered in the mode in which you’re executing, i.e., in secure mode, and not based on previous branches encountered in less secure more.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183