DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments 1 and 2 pages 1-3 in remarks, filed 08/26/2025, with respect to the rejection(s) of independent claim 14 its dependent claims under 35 USC 103 have been fully considered and are persuasive, the amendments overcome the prior art rejection previously made. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made incorporating US 20230094757 A1 Clevenger et al.
Applicant's arguments 3 pages 3-5 in remarks filed 08/26/2025 have been fully considered but they are not persuasive. For the 103 rejections against claims 21-29 Applicant individually argues that Park does not teach forming the semiconductor plugs, which the examiner agrees with, and individually argues that Kohji does not teach "wherein one of the semiconductor plugs has a sidewall in contact with a sidewall of the dielectric layer" which the examiner also agrees with. However, the applicant’s argument does not sufficiently address the combination of Park in view of Kohji which would necessarily meet this limitation as Park does not teach Kohji elements 141 and 142 fig. 16C which physically separate the plug (144 fig. 16C Kohji) of Kohji from the dielectric layer (150 fig. 16C Kohji) nor has any 103 statements been made to incorporate such elements, see annotation below of the necessitated location of the semiconductor plugs when park is modified by Kohji. For the rejection against claims 30-33, Applicant similarly argues individually that Park does not teach forming the claimed semiconductor plugs, which the examiner agrees with, and individually argues that Kohji does not teach "wherein one of the semiconductor plugs has a sidewall in contact with a sidewall of the dielectric layer", which the examiner also agrees with. However, the applicant’s argument does not sufficiently address the combination of Park in view of Kohji which would necessarily meet this limitation as Park does not teach Kohji elements 141 and 142 fig. 16C which physically separate the plug of Kohji from the dielectric layer nor has any 103 statements been made to incorporate such elements, see annotation below of the necessitated location of the semiconductor plugs when park is modified by Kohji.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
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Park Annotated fig. 10: highlighting the necessary location of plug when Park is modified in view of Kohji
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14, 18-20 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over, and further in US 20150004777 A1 Kohji et al hereafter “Kohji” in further view of US. 20100032762 A1“Park” et al hereafter “Park” and US 20230094757 A1 Clevenger et al hereafter “Clevenger”.
Claim 14 Kohji teaches a method comprising:
forming a semiconductor pillar (comprising 140 and 145 fig. 16C, under broadest reasonable interpretation as it is illustrated as a composite pillar structure that comprises channel structures 140 and crystal growth layer 145 which are semiconductor materials) extending from a substrate (comprising 110 fig. 16C);
forming a dielectric layer (comprising 150 fig. 16C) over the substrate [150 is in a vertical position over the substrates 110 illustrated in fig. 16];
performing an etching process (illustrated fig. 6, paragraph 0052 “recessed” and/or recessing qualifies as an etching process under broadest reasonable interpretation wherein “etch” includes the meaning “to make a strong clear mark or pattern on something” [oxford learner’s dictionary] wherein the mark or pattern is a recess) on the dielectric layer to form a hole (H fig. 6, illustrated in fig. 16C but not labeled) in the dielectric layer;
depositing a non-single crystalline semiconductor material (comprising 144a fig. 16A, “amorphous silicon” paragraph 0079) in the hole and on the semiconductor pillar;
performing an anneal (illustrated fig. 16C) process to crystallize the non-single crystalline semiconductor material into a single-crystalline semiconductor material [paragraph 0081-0082 “annealing process” and “the amorphous channel pad patterns 144a are crystallized into single-crystalline silicon by MILC”]; and
forming a second semiconductor material (211 fig. 16C) on the single-crystalline material
Kohji does not explicitly teach forming a transistor on the single-crystalline semiconductor material nor after forming the semiconductor pillar and the dielectric layer, performing the etch process
Park teaches a stacked semiconductor device comprising a substrate (comprising 200 fig. 10), a semiconductor pillar (224 fig. 10, sufficiently disclosed paragraph 0119-0120 “Alternatively, polysilicon doped with impurities having a conductive type the same as that of the well 216 may be deposited to form the conductive layer” and “The conductive layer may be planarized to form a second contact plug 224”) extending from the substrate, a dielectric layer (222 fig. 10) over the substrate, and a transistor (240 fig. 10) formed on top of the dielectric layer and the semiconductor pillar.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the method of forming the semiconductor pillar, the single-crystalline semiconductor material and the second single-crystalline semiconductor material as Kohji teaches as a step to form the device Park teaches such that the method includes “forming a transistor on the single-crystalline semiconductor material” using the second single-crystalline semiconductor material so that the semiconductor material of the transistor is “materially continuous” [Paragraph 0059 Kohji] with the pillar and/or substituting/combining equivalent processes known for the same purpose of forming a semiconductor pillar [see MPEP 2144.06].
Clevenger teaches a process comprising forming a dielectric layer (comprising and/or 89 fig. 9) over top a pillar (44 fig. 9); after forming the semiconductor pillar and the dielectric layer, performing an etch process (sufficiently illustrated figs. 10 and/or 11, Paragraph 0045 “ILD 91 can be patterned using lithography and removed using a dry etch process”) on the dielectric layer to form a hole [sufficiently illustrated figs. 10 and/or 11, wherein the “trench” is illustrated as material and structurally the same as a “hole” (see mpep 2112.01) and/or under broadest reasonable interpretation a “trench” and/or recess qualifies as a specific type of hole within a surface or structure] in the dielectric layer; depositing a material (134 and/or 144 fig. 14) in the hole and on the semiconductor pillar [illustrated fig. 14].
It would have been obvious to one of ordinary skill in the art to modify the process of Park in view of Kohji in further view of Clevenger such that “after forming the semiconductor pillar and the dielectric layer, performing an etch process” to enable a uniform depth of the hole and/or to ensure a suitable width of the hole [See Clevenger paragraph 0045 “upon completing the selective etch of ILD 91, the trench depth is controlled by etch stop 89 and can have uniform depth” and “The trench formed during the selective etching of ILD 91 has a width suitable”].
Claim 18 Kohji in view of Park and Clevenger as shown above teaches the method of claim 14, further comprising: patterning the non-single crystalline semiconductor material into a plurality of non-single crystalline semiconductor islands (211a fig. 16A paragraph 0079 sufficiently disclosed “forming amorphous silicon patterns”) before performing the anneal process (fig. 16C).
Claim 19 Kohji in view of Park and Clevenger as shown above teaches the method of claim 14, further comprising: forming a capping layer (241 fig. 16C) over the non-single crystalline semiconductor material [illustrated fig. 16C], wherein the annealing process is performed on the non-single crystalline semiconductor material with the capping layer in place [illustrated fig. 16C].
Claim 20 Kohji in view of Park and Clevenger as shown above teaches the method of claim 14, further comprising:
forming an spontaneous nucleation inhibition layer (220 fig. 16C meets this limitation under MPEP 2112.01 as Paragraph 0080 discloses the material as silicon oxide, silicon nitride, or silicon oxynitride which is the same that is disclosed in paragraph 0109 of the instant application) over the dielectric layer, wherein the
non-single crystalline semiconductor material is deposited over the spontaneous nucleation inhibition layer. [this limitation is met under broadest reasonable interpretation as at least a top most portion of the single crystalline semiconductor material 211 is deposited over the bottom most portion of the spontaneous nucleation inhibition layer 220 fig. 16C].
Alternatively, if the applicant disagrees it would have been obvious to one of ordinary skill in the art to modify the process of Kohji in view of Park such that “the non-single crystalline semiconductor material is deposited over the spontaneous nucleation inhibition layer” as reversal and/or rearrangement of parts is prima facie type obviousness [see MPEP 2144.04 VI. A. and/or C.]
Claim 34 Kohji in view of Park and Clevenger teach the method of claim 14,
Kohji in view of Park and Clevenger does not teach wherein the non-single crystalline semiconductor material is in contact with a sidewall of the dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to rearrange and/or change the shape of Kohji in view of Park and Clevenger such that “the non-single crystalline semiconductor material is in contact with a sidewall of the dielectric layer” as rearrangement of parts is prima facie type obviousness [see MPEP 2144.04 VI. C.] and or changes is shape are prima facie type obviousness [see MPEP 2144.04 IV. B.]
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kohji in further view of Park and Clevenger as applied to claim 14 above and in further view of US 8324660 B2 Lochtefeld et al hear after “Lochtefeld”
Claim 15 Kohji in view of Park and Clevenger as shown above teach the method of claim 14,
Kohji in view of Park does not explicitly teach wherein the semiconductor pillar is formed by patterning the substrate.
Lochtefeld teaches a semiconductor pillar (regrowth region fig. 5B and/or fig. 7C) is formed by patterning the substrate
[column 2 line 65 – column 3 line 20 Lochtefeld “a combination of substrate patterning and epitaxial lateral overgrowth ("ELO") techniques was demonstrated to greatly reduce defect densities” and “Techniques involving substrate patterning exploit the fact that the threading dislocations are constrained by geometry, i.e. that a dislocation cannot end in a crystal”]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kohji in view of Park, and Clevenger in view of Lochtefeld such that “the semiconductor pillar is formed by patterning the substrate” to greatly reduce the defect densities of the semiconductor material and/or as an art recognized equivalent for achieving the same [see MPEP 2144.06].
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kohji in further view of Park and Clevenger as applied to claim 14 above in further view of US 8294159 B2 Or-Bach et al here after “Or-Bach”.
Claim 17 Kohji in view of Park and Clevenger as shown above teach the method of claim 14,
Kohji in view of Park does not explicitly teach wherein the anneal process is laser anneal.
Or-Bach teaches a laser anneal process (Fig 24E) wherein heat transfer is minimized within the device [Sufficiently disclosed Column 23 lines 20-21].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take the anneal process that Kohji in view of Park and Clevenger teaches and modify it such that it was “a laser anneal process” as Or-Bach teaches in order to minimize heat transfer within the device during the annealing process.
Claims 21-33 is rejected under 35 U.S.C. 103 as being unpatentable over Park in further view of Kohji.
Claim 21 Park teaches a method comprising:
forming first transistor (214 fig. 10) on a substrate (200 fig. 10);
forming a dielectric layer (222 fig. 10) over the first transistor;
forming a plurality of semiconductor pillars (224 fig. 10, sufficiently disclosed paragraph 0119-0120 “Alternatively, polysilicon doped with impurities having a conductive type the same as that of the well 216 may be deposited to form the conductive layer” and “The conductive layer may be planarized to form a second contact plug 224” ) extending from the substrate into the dielectric layer [illustrated fig. 19];
forming a semiconductor structure (226b fig. 10) over the top surface of the dielectric layer; and
forming a second transistor (240 fig. 10) on the semiconductor structure.
Park does not teach forming a plurality of semiconductor plugs extending from a top surface of the dielectric layer into the dielectric layer to the plurality of semiconductor pillars, wherein one of the semiconductor plugs has a sidewall in contact with a sidewall of the dielectric layer.
Kohji teaches forming a plurality of semiconductor plugs (comprising 144 and 211 fig. 16C) extending from a top surface of a dielectric layer (150 fig. 16C) into the dielectric layer to the plurality of semiconductor pillars (comprising 140 and 145 fig. 16C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park with the teachings of Kohji such that Park includes “a plurality of semiconductor plugs extending from a top surface of the dielectric layer into the dielectric layer to the plurality of semiconductor pillars” as Kohji teaches so that the semiconductor material of the semiconductor material and/or transistor are “materially continuous” [Paragraph 0059 Kohji] with the pillar, and/or substituting/combining equivalent processes known for the same purpose of forming a semiconductor pillar [see MPEP 2144.06].
Park in view of Kohji necessarily meets the limitation “wherein one of the semiconductor plugs has a sidewall in contact with a sidewall of the dielectric layer” at least in part as it is required to modify Park such that it has the limitation “a plurality of semiconductor plugs extending from a top surface of the dielectric layer into the dielectric layer to the plurality of semiconductor pillars” as shown above, as Park does not teach Kohji elements 141 and 142 fig. 16C which physically separate the semiconductor plug (144 fig. 16C Kohji) of Kohji from the dielectric layer (150 fig. 16C Kohji) nor has any 103 statements been made to incorporate such elements. See annotation below highlighting wherein the semiconductor plugs would necessarily be located to meet the limitation as modified above.
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Park Annotated fig. 10: highlighting the necessary location of plug when Park is modified in view of Kohji
Claim 22 Park in view of Kohji as shown above teaches the method of claim 21, wherein the plurality of semiconductor pillars each have a top surface higher than a topmost position of the first transistor [sufficiently illustrated in fig. 10].
Claim 23 Park in view of Kohji as shown above teaches the method of claim 21, wherein the first transistor is a FinFET having a fin [the fin shape and FinFET structure of a transistor comprising 114, 124, 116, 118, and 120 is illustrated in fig. 1, 2, the structure of transistor 214 fig 10 is disclosed and/or illustrated as being substantially the same], and the fin of the FinFET has a top surface lower than a top surface of the plurality of semiconductor pillars [illustrated fig. 10].
Claim 24 Park in view of Kohji as shown above teaches the method of claim 21,
Park teaches a cell array region (fig. 10)
Park does not explicitly illustrate wherein the plurality of semiconductor plugs are arranged in rows and columns from a top view.
Kohji teaches the plurality of semiconductor plugs are arranged in rows and columns from a top view [sufficiently illustrated in fig. 1 by 140 wherein the semiconductor plugs 144 is illustrated as part of 140].
It would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention take the method of Park in view of Kohji and modify it such that “the plurality of semiconductor plugs are arranged in rows and columns from a top view” as rearrangements and/or duplication of parts is prima facie type obviousness [see MPEP 2144.04 VI. B. and/or C.]
Claim 25 Park in view of Kohji as shown above teaches the method of claim 21 in view of claim 24 as shown above, wherein the plurality of semiconductor pillars are arranged in rows and columns from a top view [as shown in claim 24].
Claim 26 Park in view of Kohji as shown above teaches the method of claim 21, wherein the semiconductor structure is a semiconductor fin [the fin shape structure of a transistor comprising 114 is illustrated in fig. 1, 2, the semiconductor structure 226b fig 10 is disclosed and/or illustrated as being substantially the same 114]on the top surface of the dielectric layer [illustrated fig. 10].
Claim 27 Park in view of Kohji as shown above teaches the method of claim 21, further comprising:
forming a spontaneous nucleation inhibition layer over the dielectric layer [in view of Kohji 220 fig 16C this limitation under MPEP 2112.01 as Paragraph 0080 discloses the material as silicon oxide, silicon nitride, or silicon oxynitride which is the same that is disclosed in paragraph 0109 of the instant application].
Park in view Kohji does not teach forming the spontaneous nucleation inhibition layer prior to forming the plurality of semiconductor plugs.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Park in view of Kohji such that “forming the spontaneous nucleation inhibition layer prior to forming the plurality of semiconductor plugs” takes place as “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results” [See MPEP 2144.04 IV C.]
Claim 28 Park in view of Kohji as shown above teaches the method of claim 27, wherein the spontaneous nucleation inhibition layer is a nitride-based material [Paragraph 0109 sufficiently discloses “silicon nitride” and/or “silicon oxynitride”]
Claim 29 Park in view of Kohji teaches the method of claim 21, wherein the plurality of semiconductor pillars have a height greater than a height of the plurality of semiconductor plugs [in view of Kohji sufficiently illustrated in fig. 16C].
Claim 30 Park teaches a method comprising:
forming a first transistor (214 and 208 fig. 10) on a substrate (200 fig. 10);
forming an interconnect structure over the first transistor (220 fig. 10), the interconnect structure
comprising a conductive via (220 fig. 10) vertically extending above the substrate and a conductive line laterally extending above the conductive via [sufficiently disclosed but not illustrated paragraph 0095 “A first contact plug 220 and a conductive line (not illustrated) may be provided in the first insulating interlayer 218 to be electrically connected to the impurity region 206 and the source/drain region 212, respectively”];
forming a semiconductor pillar (224 fig. 10, sufficiently disclosed paragraph 0119-0120 “Alternatively, polysilicon doped with impurities having a conductive type the same as that of the well 216 may be deposited to form the conductive layer” and “The conductive layer may be planarized to form a second contact plug 224”) extending upwards from the substrate to a position higher than the conductive via and the conductive line [sufficiently illustrated fig. 10];
forming a dielectric layer (222 fig. 10) laterally surrounding an upper portion of the semiconductor pillar;
a second transistor (234 and 240 fig. 10) over the dielectric layer
Park does not teach forming a semiconductor plug inlaid in the dielectric layer and disposed over the semiconductor pillar, wherein the semiconductor plug has opposite sidewalls interfacing opposite sidewalls of the dielectric layer; and
The second transistor above the semiconductor plug.
Kohji teaches forming a semiconductor plug (144 fig. 16C) inlaid in a dielectric layer (150 fig. 16C) and disposed over the semiconductor pillar (140 and 145 fig. 16C)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take the method of Park teaches and combine it with the method Kohji teaches such that “a semiconductor plug inlaid in the dielectric layer and disposed over the semiconductor pillar” so that the semiconductor material of the transistor is “materially continuous” [Paragraph 0059 Kohji] with the pillar and/or substituting/combining equivalent processes known for the same purpose of forming a semiconductor pillar [see MPEP 2144.06].
In view of the above the limitation the second transistor above the semiconductor plug is necessarily met in order to achieve the transistor being above the dielectric layer.
Park in view of Kohji as modified above necessarily meets the limitation “wherein the semiconductor plug has opposite sidewalls interfacing opposite sidewalls of the dielectric layer” at least in part as it is required to modify Park such that it has the limitation “a semiconductor plug inlaid in the dielectric layer and disposed over the semiconductor pillar” as shown above, as Park does not teach Kohji elements 141 and 142 fig. 16C which physically separate the semiconductor plug (144 fig. 16C Kohji) of Kohji from the dielectric layer (150 fig. 16C Kohji) nor has any 103 statements been made to incorporate such elements. See annotation below highlighting wherein the semiconductor plugs would necessarily be located to meet the limitation as modified above.
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Park Annotated fig. 10: highlighting the necessary location of plug when Park is modified in view of Kohji
Claim 31 Park in view of Kohji as shown above teaches the method of claim 30, wherein the semiconductor plug has opposite sidewalls respectively offset from opposite sidewalls of the semiconductor pillar [in view of Kohji this limitation is met under broadest reasonable interpretation as illustrated in fig. 16C as the left and right lateral side walls the semiconductor plug are offset in a vertical direction from left and right sidewalls of the semiconductor pillar].
Claim 32 Park in view of Kohji as shown above teaches the method of claim 30, wherein the semiconductor plug has opposite sidewalls respectively aligned with opposite sidewalls of the semiconductor pillar [in view of Kohji this limitation is met under broadest reasonable interpretation as illustrated in fig. 16C as the left and right lateral side walls are aligned in a horizontal direction from left and right sidewalls of the semiconductor pillar].
Claim 33 Park in view of Kohji as shown above teaches the method of claim 30, wherein the semiconductor plug is silicon, germanium or silicon germanium [in view of Kohji “silicon” Paragraph 0084].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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