DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 28, 2026 has been entered.
Response to Amendment
The amendment filed January 28, 2026 has been entered. Claims 1, 3, and 5-20 remain pending in this application. Claims 2 and 4 have been cancelled at applicant’s request. Claims 1, 3, 12, and 15 have been amended. No claims have been added. No new matter has been added.
Claim Rejections - 35 USC § 112
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999).
In Claims 12 and 15, Claims state, “wherein the Vss path is to provide a low supply reference…” This is non-standard terminology and leads to ambiguity within the claim. A supply reference is typically treated as a positive voltage supply. In context, the term here could refer to either a relatively small positive voltage (low meaning not strong) or serve as a ground (low meaning not high). The term is indefinite because the specification does not clearly redefine the term. This lack of determination is exacerbated by applicant using multiple terms in other claims seemingly referencing the same limitation, such as ‘ground[ing] the Vss path’ in Claim 1 or ‘virtual ground node’ in Claim 3. In the interest of compact prosecution, all three phrases will be interpreted as treating the Vss node as a virtual ground unless context clearly states otherwise (such as Claim 1 wherein the node is expressly left to float under certain conditions).
Claim 3 recites the limitation "the virtual ground node." There is insufficient antecedent basis for this limitation in the claim. As stated above, the Vss node in Claim 1 will be interpreted as a virtual ground node in the interest of compact prosecution.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 5-7, and 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9,679,636 B2 to Atul Katoch (hereafter Katoch) in view of US 2013/0286761 A1 to Bing Wang, et al. (hereafter Wang) and further in view of US 4,387,447 to Jeffrey M. Klaas, et al. (hereafter Klaas).
Regarding Independent Claim 1, Katoch discloses an apparatus, comprising:
a plurality of columns of memory cells in an array (A memory cell array: Katoch, col.2:33-36),
wherein each column of memory cells is coupled to a respective bit line (Columns of cells in the array connected to bit lines: Katoch, col.2:42-45) and
for each column of memory cells,
a respective footer transistor coupled to the memory cells (An individual footer, example Ft[1-1], coupled to each column of memory cells, example C[1-1]: Katoch, Figure 2).
Katoch does not teach the inclusion of a column select transistor coupled to the respective bit lines at a Vss path, wherein when the respective transistor is turn on, the Vss path is grounded, and when it the transistor is turned off, the Vss path is floated. Klaas, however, discloses a memory array as in Claim 1, wherein:
each respective bit line is coupled to a respective column select transistor (Bit lines coupled to column select transistors 15-1 through 15-4: Klass, Figure 8); and
for each column of memory cells,
a respective footer transistor coupled at a Vss path (Coupled at a Vss path: Klaas, Figure 8),
the respective footer transistor,
when turned on, is to ground the Vss path (Providing a virtual ground for the column when transistors 15-1 is turned on: Klaas, col.10:13-16) and
when turned off is to float a voltage of the Vss path (Float Vss path when transistor is off: Klaas, col.10:16-20).
Klaas teaches this arrangement is a known technique for increasing the array density in memory arrays (Klaas, col.1:32-35). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the virtual ground transistor of Klaas with the memory array of Katoch, with a reasonable expectation of success. Both inventions are well known in the field of memory array voltage management and the combination of known inventions with predictable results is obvious and not patentable.
Klaas implies, but does not clearly state, the control gate of the respective footer is coupled to a control gate of the respective column select transistor. Wang, however, discloses a memory array as in Claim 1 wherein a control gate of the respective footer transistor is coupled to a control gate of the respective column select transistor (Controlling the footer transistor and column select transistor coupled through control circuit 242: Wang, ¶[0027]). Wang teaches the inclusion of a column select transistor and a footer transistor allows for the associated memory cell to either be fully connected or disconnected from other components (Wang, ¶[0029]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the tandem control circuit of Wang with the memory architecture of Katoch, with a reasonable expectation of success. Both inventions are well known in the field of memory array voltage management and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 3, Katoch discloses the apparatus of claim 1, wherein:
for each column of memory cells (Columns of memory cells: Katoch, Figure 2),
the virtual ground node (Coupled at a Vss path: Klaas, Figure 8) is coupled to sources of the memory cells (Illustrative memory cell with source connected to bitline BL: Katoch, Figure 1),
control gates of the memory cells are coupled to respective word lines in a set of word lines (Control gates of a memory cell coupled to word line: Katoch, Figure 1), and
drains of the memory cells are coupled to the respective bit line (Drains of memory cell connected to bitline BLB: Katoch, Figure 1).
Regarding Claim 5, Katoch discloses the apparatus of claim 1, wherein:
in a read operation for a selected column of the plurality of columns,
a turn on signal is applied to the respective column select transistor and the respective footer transistor (When reading column C[1-1], column C[1-1] is connected to a strong footer: Katoch, col.8:63-64),
while a turn off signal is applied to respective column select transistors of unselected columns of the plurality of columns (When reading column C[1-1], column C[1-2] is connected to a strong footer: Katoch, col.8:65-67) and
a voltage is increased on a selected word line (Wordline controlling transistors of memory cell for read: Katoch, col.2:66-67).
Regarding Claim 6, Katoch discloses the apparatus of claim 5, wherein:
when a selected memory cell of the selected column is in a low data state,
the increase in the voltage of the selected word line (Wordline controlling transistors of memory cell for read: Katoch, col.8:26-28)
creates a discharge path through the respective column select transistor of the selected column, the selected memory cell and the respective footer transistor of the selected column (Creating a discharge path through the memory cell and footer transistors: Katoch, col.8:28-30).
Regarding Claim 7 and the substantially similar limitations of Claim 17, Katoch discloses the apparatus of claim 5, wherein:
when a selected memory cell of the selected column is in a high data state,
the selected memory cell will hold a high voltage and try to discharge through a leakage path bit line (Memory cell data in a high memory state and connecting through read bitline RBL: Katoch, col.10:19-23).
Regarding Claim 10, Katoch discloses the apparatus of claim 1, wherein:
each respective column select transistor is an nMOS transistor and each respective footer transistor is an nMOS transistor (Footer transistors are both nMOS transistors: Katoch, col.3:40-41).
Regarding Claim 11, Katoch discloses the apparatus of claim 1, wherein:
each respective column select transistor and each respective footer transistor have a same polarity (Footer transistors are both nMOS transistors: Katoch, col.3:40-41).
Regarding Independent Claim 12, Katoch discloses an apparatus, comprising:
a plurality of columns of memory cells in an array (A memory cell array: Katoch, col.2:33-36),
wherein each column of memory cells is coupled to a respective bit line (Columns of cells in the array connected to bit lines: Katoch, col.2:42-45) and
each respective bit line is coupled to a respective column select transistor (Data of columns read through footer transistors: Wang, ¶[0025]); and
for each column of memory cells,
a respective footer transistor coupled to the memory cells (An individual footer, example Ft[1-1], coupled to each column of memory cells, example C[1-1]: Katoch, Figure 2) at a Vss path (Coupled at a Vss path: Klaas, Figure 8),
wherein the respective footer transistor is independently controllable (Gates of footer transistors are independently controllable by a controller: Katoch, col.4:10-13).
to turn on in tandem with an associated column select transistor (When reading column C[1-1], column C[1-1] is connected to a strong footer: Katoch, col.8:63-64),
wherein the Vss path
is to provide a low supply reference when the footer transistor is turned on (Providing a virtual ground for the column when transistors 15-1 is turned on: Klaas, col.10:13-16) and
is to float when the footer transistor is turned off (Float Vss path when transistor is off: Klaas, col.10:16-20).
Wang teaches the inclusion of a column select transistor and a footer transistor allows for the associated memory cell to either be fully connected or disconnected from other components (Wang, ¶[0029]).
Regarding Claim 13, Katoch discloses the apparatus of claim 12, wherein
each respective footer transistor is controllable via a voltage on a respective control path (Gates of footer transistors are independently controllable by a controller: Katoch, col.4:10-13).
Regarding Claim 14, Katoch and Wang disclose the apparatus of claim 12, wherein,
for each column of memory cells (Columns of memory cells: Katoch, Figure 2),
a control gate of the respective footer transistor is coupled to a control gate of the respective column select transistor (Controlling the footer transistor and column select transistor coupled through control circuit 242: Wang, ¶[0027]).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9,679,636 B2 to Atul Katoch (hereafter Katoch), US 2013/0286761 A1 to Bing Wang, et al. (hereafter Wang), and US 4,387,447 to Jeffrey M. Klaas, et al. (hereafter Klaas), in view of US 6,633,499 B1 to Boaz Eitan, et al. (hereafter Eitan).
Regarding Claim 8, Katoch discloses the apparatus of claim 1, but fails to expressly disclose the further limitations of Claim 8. Eitan, however, discloses an apparatus as in claim 1, wherein:
for each column of memory cells, a threshold voltage of the respective footer transistor and a threshold voltage of the column select transistor are lower than threshold voltages of the memory cells (Selection transistors implemented as low threshold voltage devices: Eitan, col.9:65-67).
Eitan teaches the low threshold transistor minimizes the voltage drop along the line decreases operation time and improves the endurance of the cell (Eitan, col.9:30-43). Eitan does not expressly mention the threshold voltage used for a footer transistor, but does teach that additional transistors in the access path should operate at similarly low threshold voltages (Eitan, col.11:24-26).
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the low threshold voltage transistors of Eitan with the divide footer architecture of Katoch, with a reasonable expectation of success. They are both known inventions in the fields of bitline voltage management in memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 9, Katoch discloses the apparatus of claim 1, but fails to expressly disclose the further limitations of Claim 9. Eitan, however, describes a memory array apparatus as in Claim 1, wherein
the memory cells comprise read-only memory (ROM) cells (Applying a memory array with column select transistors to Read-Only Memory: Eitan, col.2:21).
Eitan discloses the use of ROM memory cells in a memory array is a standard method of memory apparatus manufacture (Eitan, col.2:19-23). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the Read Only Memory Cells of Eitan with the divide footer architecture of Katoch, with a reasonable expectation of success. They are both known inventions in the fields of bitline voltage management in memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9,679,636 B2 to Atul Katoch (hereafter Katoch), US 2013/0286761 A1 to Bing Wang, et al. (hereafter Wang), and US 4,387,447 to Jeffrey M. Klaas, et al. (hereafter Klaas), in view of US 2022/0028467 to Hyung Jin Choi (hereafter Choi).
Regarding independent Claim 15, Katoch discloses an apparatus, comprising:
the selected column of memory cells is coupled to a bit line (Columns of cells in the array connected to bit lines: Katoch, col.2:42-45);
a respective footer transistor is coupled to each memory cell in the selected column of memory cells (An individual footer, example Ft[1-1], coupled to each column of memory cells, example C[1-1]: Katoch, Figure 2)
to perform the read operation,
the processor is to apply a turn on voltage to the respective footer transistor and the respective column select transistor of the selected column of memory cells (When reading column C[1-1], column C[1-1] is connected to a strong footer: Katoch, col.8:63-64),
apply a turn off voltage to respective footer transistors and respective column select transistors of unselected column of memory cells in the array (When reading column C[1-1], column C[1-2] is connected to a strong footer: Katoch, col.8:65-67) and
increase a voltage on a selected word line (Wordline controlling transistors of memory cell for read: Katoch, col.2:66-67).
Katoch does not teach the inclusion of a column select transistor coupled to the respective bit lines at a Vss path, wherein when the respective transistor is turn on, the Vss path is grounded, and when it the transistor is turned off, the Vss path is floated. Klaas, however, discloses a memory array as in Claim 1, wherein:
each respective bit line is coupled at a Vss path (Coupled at a Vss path: Klaas, Figure 8)
to provide a low supply reference when the footer transistor is turned on (Providing a virtual ground for the column when transistors 15-1 is turned on: Klaas, col.10:13-16) and
to float the Vss path when turned off (Float Vss path when transistor is off: Klaas, col.10:16-20); and
Klaas teaches this arrangement is a known technique for increasing the array density in memory arrays (Klaas, col.1:32-35). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the virtual ground transistor of Klaas with the memory array of Katoch, with a reasonable expectation of success. Both inventions are well known in the field of memory array voltage management and the combination of known inventions with predictable results is obvious and not patentable.
Klaas implies, but does not clearly state, the control gate of the respective footer is coupled to a control gate of the respective column select transistor. Wang, however, discloses a memory array as in Claim 1 wherein a control gate of the respective footer transistor is coupled to a control gate of the respective column select transistor (Controlling the footer transistor and column select transistor coupled through control circuit 242: Wang, ¶[0027]). Wang teaches the inclusion of a column select transistor and a footer transistor allows for the associated memory cell to either be fully connected or disconnected from other components (Wang, ¶[0029]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the tandem control circuit of Wang with the memory architecture of Katoch, with a reasonable expectation of success. Both inventions are well known in the field of memory array voltage management and the combination of known inventions with predictable results is obvious and not patentable.
Neither Katoch nor Wang expressly disclose a memory controller, although both discuss protocols in which control voltages are applied to various control gates, implying the existence of a controller. Choi, however, expressly discloses a memory device to store instructions (Disclosing a memory controller 200: Choi, ¶[0035]) and a processor to execute the instructions to perform a read operation for a selected memory cell in a selected column of memory cells in an array (A memory controller executing the instructions to read a cell: Choi, ¶[0035]). Choi teaches a memory control may control the general operations of the storage device (Choi, ¶[0036]).
Therefore, it would have been obvious to one having ordinary skill in the art to combine the memory controller of Choi with the memory apparatus of Katoch and Wang, with a reasonable expectation of success. All three inventions are known variations of memory array management and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 16, Katoch discloses the apparatus of claim 15, wherein
when the selected memory cell is in a low data state,
the increase in the voltage of the selected word line (Wordline controlling transistors of memory cell for read: Katoch, col.8:26-28)
creates a discharge path through the respective column select transistor of the selected column, the selected memory cell and the respective footer transistor of the selected column (Creating a discharge path through the memory cell and footer transistors: Katoch, col.8:28-30).
Regarding Claim 17, Katoch discloses the apparatus of claim 15, wherein
when the selected memory cell is in a high data state,
the selected memory cell will hold a high voltage and try to discharge through a leakage path bit line (Memory cell data in a high memory state and connecting through read bitline RBL: Katoch, col.10:19-23).
Regarding Claim 18, Katoch discloses the apparatus of claim 15, wherein:
the respective footer transistor of the selected column of memory cells is to ground the selected column of memory cells when the turn on voltage is applied to the respective footer transistor of the selected column of memory cells (Paths connected to NVSS with transistor on: Katoch, Figure 1; Further, NVSS having a low logical value voltage: Katoch, col.3:67-4:3).
Regarding Claim 19, Katoch discloses the apparatus of claim 15, wherein:
the respective footer transistor of the selected column of memory cells is to float voltages of the selected column of memory cells when a turn off voltage is applied to the respective footer transistor of the selected column of memory cells (Paths isolated from NVSS with transistor off: Katoch, Figure 1; Further, NVSS having a low logical value voltage: Katoch, col.3:67-4:3).
Regarding Claim 20, Wang discloses the apparatus of claim 15, wherein:
a control gate of the respective footer transistor is coupled to a control gate of the respective column select transistor (Controlling the footer transistor and column select transistor coupled through control circuit 242: Wang, ¶[0027]).
Response to Arguments
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 9,472,288 B2 to James Michael Gardner, et al.: Disclosing a floating gate memory array with dedicated column select and footer.
US 7,679,949 B1 to Robert Paul Masleid: Disclosing a column select multiplexer circuit for a RAM memory array.
US 6,570,811 B1 to Koichi Morikawa: Disclosing a writing control circuit for a memory array.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/UYEN SMET/Primary Examiner, Art Unit 2824