Prosecution Insights
Last updated: July 17, 2026
Application No. 17/843,365

CHIP STRUCTURE AND WIRELESS COMMUNICATION APPARATUS

Non-Final OA §103
Filed
Jun 17, 2022
Priority
Dec 18, 2019 — continuation of PCTCN2019126256
Examiner
ZARNEKE, DAVID A
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Huawei Technologies Co., Ltd.
OA Round
3 (Non-Final)
71%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
573 granted / 809 resolved
+2.8% vs TC avg
Moderate +11% lift
Without
With
+10.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
51 currently pending
Career history
853
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
85.3%
+45.3% vs TC avg
§102
3.7%
-36.3% vs TC avg
§112
1.1%
-38.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 809 resolved cases

Office Action

§103
DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/24/26 has been entered. Response to Arguments Applicant’s arguments, see the claim amendments filed 4/24/26, with respect to the rejection(s) of the claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of other figures of Dalal. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1, 3, 6-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dalal et al. US 8,129,266. Regarding claim 1, Dalal (figures 5, 8 and 9) teaches a chip structure, comprising: a die 10, a first chip bond pad 23, and a second chip bond pad 24, wherein: a first radio frequency circuit 13 (column 1, lines 10-31 teaches wireless communication and column 3, lines 6-9 teaches passive devices), a second radio frequency circuit 17 (column 1, lines 10-31 teaches wireless communication and column 3, lines 6-9 teaches passive devices), a first interconnect metal wire (left 18), and a second interconnect metal wire (right 18) are disposed in the die 10; the first interconnect metal wire (left 18) is connected to the first radio frequency circuit 13, and the first interconnect metal wire (left 18) is configured to provide an alternating current ground (column 3, lines 28-35) for the first radio frequency circuit 13; the second interconnect metal wire (right 18) is connected to the second radio frequency circuit 17, and the second interconnect metal wire (right 18) is configured to provide an alternating current ground (column 3, lines 28-35) for the second radio frequency circuit 17; the first chip bond pad 84 and the second chip bond pad 85 are disposed on an outer surface of the die 10; and the first chip bond pad 84 is connected (through 32/23/20) to the first interconnect metal wire (left 18), the second chip bond pad 85 is connected (through 34/24/20) to the second interconnect metal wire (right 18), and the first interconnect metal wire (left 18) and the second interconnect metal wire (right 18) are isolated from each other (figures 4-5 show they are isolated); wherein the chip structure further comprises a first chip solder pad (on top of 84 wherein column 5, lines 18-20 states openings are formed in 70 to allow access, & figure 8 teaches solder pads attached to exposed bond pad), a second chip solder pad (on top of 85 wherein column 5, lines 18-20 states openings are formed in 70 to allow access, & figure 8 teaches solder pads attached to exposed bond pad), a first redistribution metal wire (left 18) connecting the first chip bond pad 84 and the first chip solder pad (on top of 84 wherein column 5, lines 18-20 states openings are formed in 70 to allow access, & figure 8 teaches solder pads attached to exposed bond pad), and a second redistribution metal wire (right 18) connecting the second chip bond pad 85 and the second chip solder pad (on top of 85 wherein column 5, lines 18-20 states openings are formed in 70 to allow access, & figure 8 teaches solder pads attached to exposed bond pad), and wherein each of the first chip solder pad (on top of 84 wherein column 5, lines 18-20 states openings are formed in 70 to allow access, & figure 8 teaches solder pads attached to exposed bond pad) and the second chip solder pad (on top of 85 wherein column 5, lines 18-20 states openings are formed in 70 to allow access, & figure 8 teaches solder pads attached to exposed bond pad) is configured to provide a respective solder point 72 (of figure 8). Though Dalal fails to specifically teach a radio frequency circuit, Dalal (column 1, lines 10-31 teaches wireless communication and column 3, lines 6-9 teaches passive devices) teaches devices that are conventionally known to use radio frequency circuits. Radio frequency circuits are types of passive devices used in wireless communication. With respect to claim 3, Dalal (figure 5) teaches a redistribution layer 55/30/28, wherein: the first chip solder pad (on top of 84 wherein column 5, lines 18-20 states openings are formed in 70 to allow access, & figure 8 teaches solder pads attached to exposed bond pad) and the second chip solder pad (on top of 85 wherein column 5, lines 18-20 states openings are formed in 70 to allow access, & figure 8 teaches solder pads attached to exposed bond pad) are disposed on an outer surface of the redistribution layer 32/34; a first redistribution metal wire 32/23/20 and a second redistribution metal wire 34/24/20 are disposed in the redistribution layer 55/30/28; and the first redistribution metal wire 32/23/20 and the second redistribution metal wire 34/24/20 are isolated from each other (figure 5 shows they are isolated). As to claims 6 and 7, though Dalal, which teaches wireless communication devices (column 1, lines 10-31) and passive devices (column 3, lines 6-9), fails to specifically teach the first radio frequency circuit comprises a first inductive device (claim 6); nor the second radio frequency circuit comprises a second inductive device (claim 7), it would have been obvious to one of ordinary skill in the art at the time of the invention to use first and second inductive devices in the invention of Dalal because inductive devices are conventionally known and used as The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). In re claim 8, though Dalal fails to teach a first radio frequency receive path and a second radio frequency receive path, wherein: the chip structure is configured to receive a downlink carrier aggregation signal; the downlink carrier aggregation signal comprises a first component carrier and a second component carrier; the first radio frequency receive path is configured to receive the first component carrier; the second radio frequency receive path is configured to receive the second component carrier; and the first radio frequency circuit is disposed in the first radio frequency receive path, and the second radio frequency circuit is disposed in the second radio frequency receive path, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Dalal because it is a conventionally known and used application of the device of Dalal. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). Concerning claim 9, though Dalal fails to teach the first radio frequency circuit is a first local oscillator, and the first radio frequency circuit is configured to provide a local-frequency signal for the first radio frequency receive path, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Dalal because it is a conventionally known and used application of the device of Dalal. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). Pertaining to claim 10, though Dalal fails to teach the second radio frequency circuit is a second local oscillator, and the second radio frequency circuit is configured to provide a local-frequency signal for the second radio frequency receive path, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Dalal because it is a conventionally known and used application of the device of Dalal. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). In claim 11, though Dalal fails to teach the second radio frequency circuit is a low noise amplifier, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Dalal because it is a conventionally known and used application of the device of Dalal. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 5/19/26
Read full office action

Prosecution Timeline

Show 5 earlier events
Apr 11, 2025
Response after Non-Final Action
Sep 10, 2025
Non-Final Rejection mailed — §103
Dec 05, 2025
Response Filed
Jan 27, 2026
Final Rejection mailed — §103
Apr 20, 2026
Response after Non-Final Action
Apr 24, 2026
Request for Continued Examination
Apr 28, 2026
Response after Non-Final Action
May 22, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685159
3D INTEGRATED CHIPS WITH MICROFLUIDIC COOLING
4y 2m to grant Granted Jul 14, 2026
Patent 12684914
LUMIPHORIC MATERIAL STRUCTURES FOR LIGHT-EMITTING DIODE PACKAGES AND RELATED METHODS
3y 8m to grant Granted Jul 14, 2026
Patent 12685109
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
2y 10m to grant Granted Jul 14, 2026
Patent 12666968
Semiconductor Device and Method Forming Same
4y 0m to grant Granted Jun 23, 2026
Patent 12666740
SOLID-STATE IMAGING DEVICE
3y 3m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
71%
Grant Probability
82%
With Interview (+10.7%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 809 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month