Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Claims
Examiner notes that in the instant application:
-Claims 1-14 and 21-26 are pending.
-Claims 15-20 are cancelled.
-Claims 25 and 26 are new.
-Claims 1 and 13 are amended.
-Claims 3, 4, and 7-12 are withdrawn.
Response to Amendment
The amendment to the claims filed on February 24, 2026 does not comply with the requirements of 37 CFR 1.121(c)(2) because Claims 1 and 13 remove limitations from the previously presented versions of the claims without marking them. Amendments to the claims filed on or after July 30, 2003 must comply with 37 CFR 1.121(c)(2) which states:
(2) When claim text with markings is required. All claims being currently amended in an amendment paper shall be presented in the claim listing, indicate a status of “currently amended,” and be submitted with markings to indicate the changes that have been made relative to the immediate prior version of the claims. The text of any added subject matter must be shown by underlining the added text. The text of any deleted matter must be shown by strike-through except that double brackets placed before and after the deleted characters may be used to show deletion of five or fewer consecutive characters. The text of any deleted subject matter must be shown by being placed within double brackets if strike-through cannot be easily perceived. Only claims having the status of “currently amended,” or “withdrawn” if also being amended, shall include markings. If a withdrawn claim is currently amended, its status in the claim listing may be identified as “withdrawn—currently amended.”
The properly marked amended Claims 1 and 13 are made of record and presented below:
1. (Currently Amended) A three-dimensional (3D) memory device, comprising: interleaved conductive layers and dielectric layers on a substrate, wherein edges of the conductive layers and dielectric layers define a plurality of stairs; and
a plurality of landing structures each over a respective conductive layer at a respective stair and between adjacent pillar structures each of which extends , both the first layer and the second layer are in contact with the adjacent pillar structures located in adjacent stairs.
13. (Currently Amended) A memory system, comprising:
a three-dimensional (3D) memory device, comprising:
interleaved conductive layers and dielectric layers on a substrate, wherein edges of the conductive layers and dielectric layers define a plurality of stairs; and
a plurality of landing structures each over a respective conductive layer at a respective stair and between adjacent pillar structures each of which extends second material, both the first layer and the second layer are in contact with the adjacent pillar structures located in adjacent stairs, and
a memory controller coupled to the 3D memory device and configured to control operations of the 3D memory device.
Response to Arguments
Applicant’s amendments and arguments filed February 24, 2026 have been fully considered but are not persuasive.
In particular Examiner notes that the phrase “in contact” under broadest reasonable interpretation does not require the elements in question to be in direct contact, i.e. that there are no intervening layers or elements. Thus, even as originally presented in the Non-Final dated December 17, 2025, the incorporation of the teachings of Nishida into Kim already teaches the amended limitation as it relates to being in contact to adjacent pillar structures.
Furthermore, the newly amended limitations specifies that the adjacent pillar structures are located “in adjacent stairs” which is unclear as to what range of “adjacent” the pillars are referencing and may be interpreted as separate pillars from the ones which are defined as the ones which each of the plurality of landing structures are between.
For the sake of compact prosecution, Examiner will incorporate and cite a new reference to address the amendments both as written and from what may be interpretable from Applicant’s embodiments. The rejection has been updated to address the newly amended limitations.
Claim Objections
Claims 1 and 13 are objected to because of the following informalities:
The limitation section “having a second material, both the first layer” should read --having a second material, wherein both the first layer--
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 2, 5, 6, 13, 14, and 21-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1, the limitation “in contact with the adjacent pillar structures located in adjacent stairs” is unclear as to what is the intent of “in adjacent stairs” is, as it relates to the pillars referenced, and may be interpreted as separate pillars from the ones which are defined as the ones which each of the plurality of landing structures are between.
Regarding Claims 2, 5, 6, 21, and 25 are rejected due to their dependency on Claim 1.
Regarding Claim 13, the limitation “in contact with the adjacent pillar structures located in adjacent stairs” is unclear as to what is the intent of “in adjacent stairs” is, as it relates to the pillars referenced, and may be interpreted as separate pillars from the ones which are defined as the ones which each of the plurality of landing structures are between.
Regarding Claims 2, 5, 6, 21, and 25 are rejected due to their dependency on Claim 1.
For the purpose of this Office Action, the Examiner will read the limitation “in contact with the adjacent pillar structures located in adjacent stairs” of Claim 1 and Claim 13 as --in contact with the adjacent pillar structures each of the landing structures are between--
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 6, 21, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. Pub. 2017/0117222), hereinafter Kim I, in view of Kim et al. (U.S. Pub. 2017/0040337), hereinafter Kim II.
Regarding Claim 1, Kim I teaches a three-dimensional (3D) memory device (‘embodiment of a vertical memory device’; Fig. 38, Paragraph [0157]), comprising:
-interleaved conductive layers (‘gate lines’ (160); Fig. 38, Paragraph [0032]) and dielectric layers (‘insulating interlayer pattern’ (106); Fig. 38, Paragraph [0032]) on a substrate ((100); Fig. 38, Paragraph [0032]), wherein
-edges of the conductive layers ((160)) and dielectric layers ((106)) define a plurality of stairs (gate lines / insulating interlayer pattern ‘may be stacked in a pyramidal shape or a stepped shape’; Fig. 38, Paragraphs [0046] and [0052]); and
-a plurality of landing structures (plurality of ‘step portions’ of (106); Fig. 38, Paragraph [0053]) each over a respective conductive layer (160) at a respective stair (a given pair of (106) and (160) with the same length in the second direction, e.g. (106b) and (160a)),
-each of the landing structures (‘step portions’) comprises a first layer (‘second etch-stop layer pattern’ (166); Fig. 38, Paragraph [0055]) having a first material (e.g. ‘a metal nitride’; Paragraphs [0049] and [0058]) and
-a second layer (‘first etch-stop layer pattern’ (112); Fig. 38, Paragraph [0055]) having a second material (e.g. ‘silicon dioxide’; Paragraphs [0052] and [0056]),
Kim I does not teach that the landing structures are:
-between adjacent pillar structures each of which extends into the substrate.
-both the first layer and the second layer are in contact with the adjacent pillar structures each of the landing structures are between.
Kim II teaches a three-dimensional (3D) memory device (‘first exemplary structure’; Figs. 3-6, Paragraphs [0059]), wherein:
the landing structures (portion of conductive layers (130) which contact vias (110) connect to; Fig. 4, Paragraphs [0059] and [0066]) are between adjacent pillar structures ((DCH); Fig. 5, Paragraph [0059]) each of which extends into the substrate ((102); Fig. 5, Paragraph [0066]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kim II into the device of Kim I such that the landing structures are between adjacent pillar structures each of which extends into the substrate. Furthermore, the incorporation would necessarily result in both the first layer and the second layer are in contact with the adjacent pillar structures each of the landing structures are between. This would be due to the fact that doing so would produce the expected result of providing mechanical support to the stair area, decreasing the probability of breaking (Kim II, Paragraph [0073]).
For the remainder of this rejection, unless otherwise specified, all element references are from Kim I. e.g. (100) refers to element 100 of Kim I while (Kim II, (100)) refers to element 100 of Kim II.
Regarding Claim 2, Kim I as modified by Kim II teaches a three-dimensional (3D) memory device (‘embodiment of a vertical memory device’; Fig. 38, Paragraph [0157]) of Claim 1, wherein:
-the second layer (112) is between the first layer (166) and the respective conductive layer (160) and covers top surfaces and side surfaces of the plurality of stairs (Fig. 38, Paragraph [0055]), and
-the first layer (166) covers top surfaces of the second layer (112) without covering side surfaces of the second layer (Fig. 38, Paragraph [0159]; Note the Examiner understands the term ‘covering’ as is defined by the Merriam-Webster Dictionary as “something that covers or conceals” wherein cover is defined (by entry 3) as “to lay or spread something over”).
Regarding Claim 5, Kim I as modified by Kim II teaches the 3D memory device (‘embodiment of a vertical memory device’; Fig. 38, Paragraph [0157]) of Claim 1, wherein:
-the second material (material of (112)) comprises silicon oxide, silicon oxynitride, or a combination thereof. (‘silicon dioxide’; Paragraphs [0052] and [0056])
Regarding Claim 6, Kim I as modified by Kim II teaches the 3D memory device (‘embodiment of a vertical memory device’; Fig. 38, Paragraph [0157]) of Claim 1, wherein:
-at each of the plurality of stairs (a given pair of (106) and (160) with the same length in the second direction), a respective dielectric layer (106, e.g. (106b)) is above (e.g. in the first direction, Fig. 38) and in contact with the respective conductive layer (160, e.g. (160a)).
Regarding Claim 21, Kim I as modified by Kim II teaches the 3D memory device (‘embodiment of a vertical memory device’; Fig. 38, Paragraph [0157]) of Claim 6, further comprising:
-a plurality of contact structures ((198); Fig. 38, Paragraph [0160]) each extending through a respective landing structure (‘step portions’) and the respective dielectric layer (106), and in contact with the respective conductive layer (160) of the respective stair.
Regarding Claim 25, Kim I as modified by Kim II teaches the 3D memory device (‘embodiment of a vertical memory device’; Fig. 38, Paragraph [0157]) of Claim 2, wherein:
-each pillar structure (Kim II, (DCH)) is in contact with a vertical portion of the second layer that covers the side surface of the corresponding stair (necessarily the case with the incorporation of the teachings of Kim II into Kim I, see Kim II Paragraph [0073] and Figs. 5 and 6, the pillar structures directly contact the ends of the stairs, where the second layer would be in Kim I).
Claims 13, 14, 22-24, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. Pub 2015/0008506), hereinafter Yang, in view of Kim I, and in further view of Kim II. An annotated version of Fig. 16B of Yang, hereinafter “Fig. A”, is included below for reference.
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Regarding Claim 13, Yang teaches a memory system (‘memory system’ (1310); Fig. 17B, Paragraph [0151]), comprising:
a three-dimensional (3D) memory device (‘memory system (1310) having at least one of the semiconductor memory devices 1 to 17’, e.g. (16), specifically integrated as memory (1311); Fig. A, Paragraph [0151]), comprising:
-interleaved conductive layers (plurality of gates (225); Fig. A, Paragraph [0125]) and dielectric layers (plurality of layers (215); Fig. A, Paragraph [0125]) on a substrate ((200); Fig. A, Paragraph [0125]), wherein
-edges of the conductive layers (plurality of (225)) and dielectric layers (plurality of (215)) define a plurality of stairs (‘gate stack (206) are patterned to form a staircase’; Fig. A, Paragraph [0127]); and
-a plurality of landing structures (plurality of (Steps); Fig. A) each over a respective conductive layer (225) at a respective stair (a given pair of (225) and (215), e.g. the bottom)), wherein
-a second layer ((230); Fig. A, Paragraph [0124]) having a second material (e.g. silicon oxide; Paragraph [0126]),
-a memory controller ((1312); Fig. 17B, Paragraph [0151]) coupled to the 3D memory device (1311) and configured to control operations of the 3D memory device (as in the memory system (1310)).
Yang does not teach:
-a first layer having a first material
Kim I teaches a three-dimensional (3D) memory device (‘embodiment of a vertical memory device’; Fig. 38, Paragraph [0157]), comprising:
-a first layer (‘second etch-stop layer pattern’ (166); Fig. 38, Paragraph [0055]) having a first material (e.g. ‘a metal nitride’; Paragraphs [0049] and [0058])
It would have been obvious to one of ordinary skill in the art at the time the claims were effectively filed to incorporate the teachings of Kim I into the device of Yang such that the three-dimensional (3D) memory device comprised a first layer having a first material with the first layer covering top surfaces of the second layer without covering side surfaces of the second layer. It is noted that this incorporation would be such that the first layer (Kim, (166)) covers top surfaces of the second layer (Kim (112), as to Yang (230)) without covering side surfaces of the second layer (Fig. 38, Paragraph [0159]; Note the Examiner understands the term ‘covering’ as is defined by the Merriam-Webster Dictionary as “something that covers or conceals” wherein cover is defined (by entry 3) as “to lay or spread something over”). Furthermore, the incorporation of this structure would be such that the device further comprised a plurality of contact structures (Kim, (198); Fig. 38, Paragraph [0160]) each extending through a respective landing structure (Kim, ‘step portions’) and the respective dielectric layer (Kim, (106)), and in contact with the respective conductive layer (Kim, (160)) of the respective stair. The incorporation of the contact structures would be motivated by the fact it would have the predictable result of increasing functionality by allowing to directly and separately contact individual gate lines. The incorporation of a first layer, specifically, would be motivated by the fact doing so would increase device efficiency by decreasing the electrical resistance through the contacts (Kim, Paragraph [0162]).
Yang nor Kim I additionally does not teach that the landing structures are:
-between adjacent pillar structures each extending through the interleaved conductive layers and dielectric layers and into the substrate.
Kim II teaches a three-dimensional (3D) memory device (‘first exemplary structure’; Figs. 3-6, Paragraphs [0059]), wherein:
the landing structures (portion of conductive layers (130) which contact vias (110) connect to; Fig. 4, Paragraphs [0059] and [0066]) are between adjacent pillar structures ((DCH); Fig. 5, Paragraph [0059]) each of which extends into the substrate ((102); Fig. 5, Paragraph [0066]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kim II into the device of Kim I such that the landing structures are between adjacent pillar structures each of which extends into the substrate. Furthermore, the incorporation would necessarily result in both the first layer and the second layer are in contact with the adjacent pillar structures each of the landing structures are between. This would be due to the fact that doing so would produce the expected result of providing mechanical support to the stair area, decreasing the probability of breaking (Kim II, Paragraph [0073]).
Regarding Claim 14, Yang as modified by Kim I and Kim II teaches the memory system ((2000); Fig. 20B, Paragraph [0150]) of Claim 13, wherein:
- the second layer (Yang, (230)) is between the first layer (Kim I, (166)) and the respective conductive layer (Yang, (225)) and covers top surfaces and side surfaces of the plurality of stairs (Yang, plurality of pairs of (225) and (215)), and the first layer (Kim I, (166)) covers top surfaces of the second layer (Yang, (230)) without covering side surfaces of the second layer (As detailed in the incorporation of the teachings of Kim I into the device of Yang in Claim 13 above. See also Kim I Fig. 38, Paragraph [159]).
Regarding Claim 22, Yang as modified by Kim I and Kim II teaches the memory system ((2000); Fig. 20B, Paragraph [0150]) of Claim 13, wherein:
- the second material (Yang, material of 215s) comprises silicon oxide, silicon oxynitride, or a combination thereof. (Yang, ‘silicon oxide’; Paragraph [0126])
Regarding Claim 23, Yang as modified by Kim I and Kim II teaches the memory system ((2000); Fig. 20B, Paragraph [0150]) of Claim 13, wherein:
-at each of the plurality of stairs (Yang, a given pair of (225) and (215)), a respective dielectric layer (Yang, (215)) is above (Yang, e.g. in the vertical direction) and in contact with a respective conductive layer (Yang, (225)).
Regarding Claim 24, Yang as modified by Kim I and Kim II teaches the memory system ((2000); Fig. 20B, Paragraph [0150]) of Claim 23, further comprising:
-a plurality of contact structures (Kim I, (198)) each extending through a respective landing structure (Kim I, ‘step portions’) and the respective dielectric layer (Kim I, (106)), and in contact with the respective conductive layer (Kim I, (160)) of the respective stair. (As detailed in the incorporation of the teachings of Kim I into the device of Yang in Claim 13 above. See also Kim I Fig. 38 and Paragraph [0160])
Regarding Claim 26, Yang as modified by Kim I and Kim II teaches the memory system ((2000); Fig. 20B, Paragraph [0150]) of Claim 14, wherein:
-each pillar structure (Kim II, (DCH)) is in contact with a vertical portion of the second layer that covers the side surface of the corresponding stair (necessarily the case with the incorporation of the teachings of Kim II into Yang as modified by Kim I, see Kim II Paragraph [0073] and Figs. 5 and 6, the pillar structures directly contact the ends of the stairs, where the second layer would be in Yang as modified by Kim I).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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/D.M./Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812