DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-15, in the reply filed on 06/30/2025 is acknowledged. The traversal is on the ground(s) that “the Office has failed to articulate facts sufficient to demonstrate that the alleged groups are independent or distinct”. This is not found persuasive because of the detailed reasons given in the Requirement for Restriction/Election mailed on 05/05/2025. To summarize those reasons, the product as claimed in Group II could be made by a another and materially different process than that claimed in Group I, for example by depositing a semiconductor layer over a plurality of first, second and third isolation islands on a dummy substrate, forming a bit line doped region in a top portion of the semiconductor layer over each of the plurality of first isolation islands then removing the dummy substrate so that the semiconductor layer becomes the substrate. This process is distinct from the limitation in claim 1 requiring “forming a bit line doped area in the semiconductor substate at a bottom portion of each of the plurality of second trenches”.
The requirement is still deemed proper and is therefore made FINAL.
Claims 16-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 05/05/2025.
Drawings
The drawings are objected to because the cross sections shown in FIGS. 1, 2, 4-8, 10-14, 16-17, 19-20, and 22-43 do not indicate in which direction the cross section is taken (e.g. first direction along C-D or second direction along A-B in the top view of FIG. 21). Although the specification may indicate the direction of the cross section for each figure, it is recommended to explicitly include this in each figure for clarity. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines 7-8 recite “the plurality of first trenches and the plurality of second trenches are spaced apart from each other in the first direction”. It is unclear how the plurality of first trenches and the plurality of second trenches can be spaced apart in the first direction when they both extend along a first direction, per lines 3-4 of the claim. As best understood, the plurality of first trenches and the plurality of second trenches as spaced apart from each other in the second direction, as shown in FIGS. 19 and 20. Appropriate correction is required. No new matter should be entered.
Claim 11, lines 3-4 recite “forming a plurality of through holes exposing a surface of the source area in the first dielectric layer”. It is unclear how a surface of the source area is exposed in the first dielectric layer, since the first dielectric layer is formed on the semiconductor substrate and is separate from the source area. As best understood, the through holes expose a surface of the source area through the first dielectric layer, as shown in FIG. 38 of the disclosure. Similarly, lines 6-7 recite “…forming a capacitor hole exposing the capacitor plug in the second dielectric layer”, which is understood as “…forming a capacitor hole exposing the capacitor plug through the capacitor hole in the second dielectric layer”. Appropriate correction is required. No new matter should be entered.
Claims 2-10 and 12-15 are rejected at least based on their dependency on claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, and 10-12, as best understood, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho in US 2012/0094454 A1 (hereinafter Cho).
Regarding claim 1, Cho teaches in FIGS. 2A-13B and related text, a method for forming a storage device, comprising:
providing a semiconductor substrate (102, FIG. 3B, [0062]), and forming a plurality of active areas (108A/B, FIGS. 7B/7C, [0084]) in the semiconductor substrate (102), wherein the plurality of active areas (108A/B) are spaced apart from each other by a plurality of first trenches (134, FIG. 7B, [0084]) and a plurality of second trenches (124, FIG. 7B, [0079]) extending along a first direction (y, FIG. 7A) and a plurality of third trenches (104, FIG. 7C, [0062]) extending along a second direction (x, FIG. 7A), the plurality of first trenches (134) and the plurality of second trenches (124) communicate with the plurality of third trenches (104; trenches intersect, FIG. 7A), the plurality of first trenches (134) and the plurality of second trenches (124) are spaced apart from each other in the second direction (x), a depth (P2, FIG. 7B, [0068]) of each of the plurality of second trenches (124) is less than a depth (P3, FIG. 7B, [0081]) of each of the plurality of first trenches (134; see FIG. 7B), and a depth (P1, FIG. 7C, [0068]) of a region of each of the plurality of third trenches (104) other than a communication region of each of the plurality of third trenches (104) with each of the plurality of second trenches (124) is greater than the depth (P2) of each of the plurality of second trenches (124, [0068]);
forming a bit line doped area (142, FIG. 9A, [0092]) in the semiconductor substrate (102) at a bottom portion of each of the plurality of second trenches (124, FIG. 9A) and at a bottom portion of the communication region of each of the plurality of third trenches (104, FIG. 9B) with each of the plurality of second trenches (124);
forming a first isolation layer (136/106, FIG. 8A, [0085]/[0062]) in each of the plurality of first trenches (134) and each of the plurality of third trenches (106), wherein a surface of the first isolation layer (136/106) is lower than a surface of each of the plurality of active areas (108A/B, FIG.8A);
forming a gate dielectric layer (172G, FIGS. 13A/13B, [0105]) surrounding the plurality of active areas (108A/108B; 172G is at least present in cross sections BX1-BX1- and CY2-CY2’ and is therefore disposed on multiple sides of active areas 108A/108B) on surfaces of the plurality of active areas (108A/108B, FIG. 13B);
forming, on a surface of the gate dielectric layer (172G) arranged on side walls of the plurality of active areas (108A/108B), a plurality of metal gates (174CG, FIGS. 13A/13B, [0048]) surrounding the plurality of active areas (108A/B; 174CG is at least present in cross sections BX1-BX1- and CY2-CY2’ and is therefore disposed on multiple sides of active areas 108A/108B), wherein a top surface (top side surface, see annotated FIG. 13B below) of each of the plurality of metal gates (174CG) is lower than a top surface of each of the plurality of active areas (108A/B, FIG. 13B); and
forming a source area (160, FIGS 13A/B, [0104]) on the top surface of each of the plurality of active areas (108A/B).
PNG
media_image1.png
639
523
media_image1.png
Greyscale
Annotated FIG. 13B (Cho)
Regarding claim 2, Cho teaches the method for forming the storage device according to claim 1. Cho further teaches wherein a width of the bit line doped area (142, FIG. 9A) is greater than or equal to a width of the bottom portion of each of the plurality of second trenches (124, FIG. 9A).
Regarding claim 3, Cho teaches the method for forming the storage device according to claim 2. Cho further teaches wherein the bit line doped area (142) is formed through a first ion implantation process ([0092]), and impurity ions implanted through the first ion implantation process are N-type impurity ions or P-type impurity ions ([0092]).
Regarding claim 5, Cho teaches the method for forming the storage device according to claim 1. Cho further teaches wherein the source area (160) is formed through a second ion implantation process ([0104]).
Regarding claim 10, Cho teaches the method for forming the storage device according to claim 1. Cho teaches further comprising: forming a capacitor (192 is capacitor lower electrode, FIG. 13A, [0107]-[0112]) connected to the source area (160) on the surface of the semiconductor substrate (102).
Regarding claim 11, Cho teaches the method for forming the storage device according to claim 10. Cho further teaches wherein forming the capacitor connected to the source area (160) on the surface of the semiconductor substrate (102) comprises: forming a first dielectric layer (180, FIG. 13A, [0108]) on the semiconductor substrate (102); forming a plurality of through holes (184H, FIG. 13A, [0108]) exposing a surface of the source area (160) in the first dielectric layer (180); forming a contact plug (184, FIG. 13A, [0110] in each of the plurality of through holes (184H); forming a second dielectric layer (190, FIG. 13A, [0111]) on the first dielectric layer (180); forming a capacitor hole (190H, FIG. 13A, [0111]) exposing the contact plug (184) in the second dielectric layer (190); and forming the capacitor (lower capacitor electrode 192, FIG. 13A, [0111]-[0112]) in the capacitor hole (190H).
Regarding claim 12, Cho teaches the method for forming the storage device according to claim 1. Cho further teaches wherein the plurality of active areas (180A/180B) are arranged in rows and columns (see FIG. 2A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6, as best understood, is rejected under 35 U.S.C. 103 as being unpatentable over Cho in US 2012/0094454 A1 (hereinafter Cho) and in view of Kim in US 2012/0153379 A1 (hereinafter Kim).
Regarding claim 6, Cho teaches the method for forming the storage device according to claim 2. Cho does not explicitly teach wherein a type of impurity ions doped in the source area is the same as a type of impurity ions doped in the bit line doped area.
Kim teaches in FIG. 1 and related text a type of impurity ions doped in a source area (102, [0033]) is the same as a type of impurity ions doped in a bit line doped area (101, [0033]).
Cho and Kim are analogous art to the claimed invention because they are directed to semiconductor devices with vertical transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cho in view of Kim because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cho such that a type of impurity ions doped in the source area is the same as a type of impurity ions doped in the bit line doped area, as taught by Kim, with the purpose of creating source/drain regions for the vertical transistor ([Kim, [0033]), which would create p-n junctions at the interface of the channel region.
Claim 7, as best understood, is rejected under 35 U.S.C. 103 as being unpatentable over Cho in US 2012/0094454 A1 (hereinafter Cho) and in view of Song in US 2007/0051994 A1 (hereinafter Song).
Regarding claim 7, Cho teaches the method for forming the storage device according to claim 1. Cho further teaches wherein forming the plurality of metal gates (174CG) comprises: forming a metal layer (conductive layer, [0105]) on the surface of the gate dielectric layer (172G, [0105]) and the surface of the first isolation layer (136; conductive layer covers entire upper surface of substrate 102).
Cho does not explicitly teach removing an excess portion of the metal layer through maskless etching to form the plurality of metal gates surrounding the plurality of active areas on the surface of the gate dielectric layer arranged on the side walls of the plurality of active areas.
Song teaches in FIGS. 6A-6C and related text, removing an excess portion of a metal layer (190, FIG. 6A, [0062]) through maskless etching (anisotropic etch, [0063]) to form a plurality of metal gates (195, FIG. 6C, [0063]) surrounding a plurality of active areas (104, FIG. 6C, [0063]) on the surface of a gate dielectric layer (180, FIG. 6A [0063]) arranged on the side walls of the plurality of active areas (140), in order ensure the plurality of metal gates (195) are electrically insulated from each other ([0064]).
Cho and Song are analogous art to the claimed invention because they are directed to semiconductor devices with vertical transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cho in view of Song because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cho to include removing an excess portion of the metal layer through maskless etching to form the plurality of metal gates surrounding the plurality of active areas on the surface of the gate dielectric layer arranged on the side walls of the plurality of active areas, as taught by Song, with the purpose of ensuring electrical insulation between each other (Song, [0064]).
Prior Art of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2016/0293419 A1 discloses a method of forming first and second mask patterns extending in a first direction and spaced apart from each other, forming third mask patterns on the first and second mask patterns and extending in a second direction perpendicular to the first direction, etching the first and second mask patterns using the third mask pattern, wherein a remaining portion of the plurality of first mask patterns can be used as a discrete etching mask (e.g. in FIG. 12).
Allowable Subject Matter
Claims 4, 8-9, and 13-15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 recites “before performing the first ion implantation process, forming a protective layer…on side walls and bottom surfaces of the plurality of third trenches” in combination with other limitations. The prior art of record does not teach or disclose the quoted limitations.
Claim 8 recites the limitations “after forming the plurality of metal gates, forming a second isolation layer covering the plurality of metal gates and filling the plurality of first trenches, the plurality of third trenches and the plurality of second trenches; and forming, in the second isolation layer in the plurality of third trenches, a plurality of conductive connection structures extending along the second direction and configured to connect the plurality of metal gates with each other”. The prior art of record does not teach or disclose these limitations.
Claim 9 recites the limitations “wherein forming the plurality of metal gates comprises: forming a metal layer filling the plurality of first trenches, the plurality of third trenches and the plurality of second trenches on the surface of the gate dielectric layer and on the surface of the first isolation layer; … cutting the metal layer filing the plurality of third trenches along the second direction to form the plurality of metal gates surrounding the plurality of active areas on the surface of the gate dielectric layer arranged on the side walls of the plurality of active areas.” in combination with other limitations. The prior art of record does not teach or disclose the quoted limitations.
Claim 13 recites the limitations “wherein forming the plurality of active areas comprises: forming, on the semiconductor substrate, a plurality of first mask patterns arranged parallel to each other and extending along the first direction, wherein a plurality of first openings and a plurality of second openings are alternately arranged between any two of the plurality of first mask patterns adjacent to each other, and a width of each of the plurality of first openings is greater than a width of each of the plurality of second openings; forming, on the plurality of first mask patterns, a plurality of second mask patterns arranged parallel to each other and extending along the second direction, wherein a plurality of sixth openings are provided between any two of the plurality of second mask patterns adjacent to each other; etching the plurality of first mask patterns along the plurality of sixth openings by using the plurality of second mask patterns as masks to form a plurality of third openings extending along the second direction in the plurality of first mask patterns, wherein a remaining portion of the plurality of first mask patterns is formed as a plurality of discrete etching masks; and etching the semiconductor substrate by using the plurality of etching masks as masks to form the plurality of first trenches corresponding to the plurality of first openings, the plurality of second trenches corresponding to the plurality of second openings, and the plurality of third trenches corresponding to the plurality of third openings in the semiconductor substrate, wherein a plurality of areas between the plurality of first trenches, the plurality of second trenches, and the plurality of third trenches are formed as the plurality of active areas, the plurality of first trenches and the plurality of second trenches communicate with the plurality of third trenches, the depth of each of the plurality of second trenches is less than the depth of each of the plurality of first trenches, and the depth of the region of each of the plurality of third trenches other than the communication region of each of the plurality of third trenches with each of the plurality of second trenches is greater than the depth of each of the plurality of second trenches”. The prior art of record does not teach or disclose the quoted limitations.
Claim 14 recites limitations in addition to those recited in claim 13, but the prior art of record does teach or disclose the limitations of claim 13.
Claim 15 recites the limitations “wherein forming the plurality of first mask patterns comprises: forming a first hard mask layer on the semiconductor substrate; forming, on the first hard mask layer, a plurality of first strip structures extending along the first direction and arranged parallel to each other; forming a first sacrificial spacer layer on side walls and top surfaces of the plurality of first strip structures and on a surface of the first hard mask layer between the plurality of first strip structures; filling a first filling layer between the plurality of first strip structures; removing the first sacrificial spacer layer on surfaces of the side walls of the plurality of first strip structures to form a plurality of fourth openings between the plurality of first strip structures and the first filling layer; etching the first hard mask layer along the plurality of fourth openings to form the plurality of first openings in the first hard mask layer; forming a second filling layer filling the plurality of first openings; forming, on the second filling layer, a plurality of second strip structures extending along the first direction and arranged parallel to each other, wherein each of the plurality of second strip structures covers the second filling layer in a respective one of the plurality of first openings and a portion of the first hard mask layer on both sides of the respective one of the plurality of first openings; forming a second sacrificial spacer layer on side walls and top surfaces of the plurality of second strip structures and on surfaces of the first hard mask layer and the first filling layer between the plurality of second strip structures; filling a third filling layer between the plurality of second strip structures; removing the second sacrificial spacer layer on surfaces of the side walls of the plurality of second strip structures to form a plurality of fifth openings between the plurality of second strip structures and the third filling layer, wherein a width of each of the plurality of fifth openings is less than a width of each of the plurality of fourth openings; and etching the first hard mask layer between the plurality of first openings along the plurality of fifth openings to form the plurality of second openings in the first hard mask layer, wherein the width of each of the plurality of second openings is less than the width of each of the plurality of first openings, and a remaining portion of the first hard mask layer between the plurality of second openings and the plurality of first openings is formed as the plurality of first mask patterns”, in addition to the limitations recited in claims 13 and 14. The prior art of record does not teach or disclose the combined limitations of claims 13, 14 and 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN LEE JOHNSON JR whose telephone number is (571)270-3217. The examiner can normally be reached Mon-Fri: 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.L.J./Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811
Prosecution Insights