Prosecution Insights
Last updated: April 19, 2026
Application No. 17/844,453

ADHESIVE SHEET AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Non-Final OA §103
Filed
Jun 20, 2022
Examiner
SMITH, SAMUEL JONATHAN
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
3 (Non-Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
3y 5m
To Grant
84%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
29 granted / 35 resolved
+14.9% vs TC avg
Minimal +1% lift
Without
With
+0.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
17 currently pending
Career history
52
Total Applications
across all art units

Statute-Specific Performance

§103
59.9%
+19.9% vs TC avg
§102
28.9%
-11.1% vs TC avg
§112
10.5%
-29.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 35 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 8 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woychik (US 20150270209 A1) in view of Lee (US 20200211920 A1), Sato (US 20200148544 A1) and JP 5293496 B2. Regarding claim 1, Woychik discloses a semiconductor package (Fig. 2B; 50) comprising: a first substrate (41); a second substrate (40) comprising a semiconductor element formed thereon (IC Die 10-4 for example); and a molding member surrounding the second substrate (Fig. 3C, molding 322). However, Woychik does not explicitly disclose an adhesive film layer between the first substrate and the second substrate; wherein the adhesive film layer comprises a crystalline spherical silica filler in a matrix, wherein an average dimension of the spherical silica filler is greater than 25 µm and equal to or less than 100 µm, and wherein a thermal conductivity of the spherical silica filler is about 5.5 W/m·K to about 30 W/m·K. On the other hand, Lee discloses an adhesive film layer between the first substrate and the second substrate (Fig. 1); wherein the adhesive film layer comprises a crystalline spherical silica filler (Fig. 2, first thermal conductive members 12; para. 27 "the first thermal conductive members 12 may include… crystalline silicon oxide", silicon oxide is commonly known as silica) in a matrix (10), wherein an average dimension of the spherical silica filler is greater than 25 µm and equal to or less than 100 µm (Para. 27 "Each of the first thermal conductive members 12 may have a major axis WT2 with a length of about 1 µm to about 1500 µm"). It would have been obvious to one of ordinary skill in the art before the time of the effective filing of the invention to modify Woychik according to the teachings of Lee such that the adhesive film would be positioned between the first and second substrates, and the adhesive film layer would comprise a crystalline silica filler in a matrix, and a dimension of the silica filler would be greater than 25 µm and equal to or less than 100 µm, in order to mitigate heat between the two substrates using a filler than is sufficiently large to allow for sufficient thermal conductivity while also being sufficiently small to maintain the strength and uniformity of the adhesive film layer. Woychik in view of Lee still does not disclose a spherical filler in the adhesive film layer. On the other hand, JP 5293496 B2 discloses an adhesive film comprising a crystalline spherical silica filler in a matrix (Bottom of pg. 1 "The adhesive composition comprises a resin and a filler.", where the resin corresponds to the polymer matrix; "The filler has a spherical form"; Pg. 4 "Examples of the filler include… silica"). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Woychik in view of Lee according to the teachings of JP 5293496 B2 such that the crystalline silica filler would have a spherical shape and an average dimension greater than 25 µm and equal to or less than 100 µm in order to ensure uniform thermal conductivity of the adhesive film layer. Woychik in view of Lee and JP 5293496 B2 still does not disclose and wherein a thermal conductivity of the spherical silica filler is about 5.5 W/m·K to about 30 W/m·K. However, Sato discloses wherein a thermal conductivity of the spherical silica filler is about 5.5 W/m·K to about 30 W/m·K (Para. 6 "In particular, since quartz has a denser crystal structure than other crystals, the thermal conductivity is as high as 12.8 W/mK, and spherical silica particles containing a large amount of quartz are considered to have a high thermal conductivity", where quartz is known to be a form of silica). It would have been obvious to one of ordinary skill before the time of effective filing of the invention to modify Woychik in view of Lee and JP 5293496 B2 according to the teachings of Sato such that the thermal conductivity of the spherical filler would be about 5.5 W/m·K to about 30 W/m·K, in order to ensure that the silica filler is capable of managing the heat produced during the operation or manufacturing of the semiconductor package. Regarding claim 8, JP 5293496 B2 discloses wherein an overall thermal conductivity of the adhesive film layer is about 1 W/(m·K) to about 5 W/(m·K) (Pg. 11 "the thermal conductivity is preferably 1.0 W / mK or more"). Regarding claim 22, Woychik discloses a semiconductor package (Fig. 2B; 50) comprising: a first substrate (41); a second substrate (40) comprising a semiconductor element formed thereon (IC Die 10-4 for example); and a molding member surrounding the second substrate (Fig. 3C, molding 322). However, Woychik does not explicitly disclose an adhesive film layer between the first substrate and the second substrate; wherein the adhesive film layer comprises a crystalline spherical silica filler dispersed in a matrix, wherein a thermal conductivity of the spherical silica filler is about 5.5 W/m·K to about 30 W/m·K. On the other hand, Lee discloses an adhesive film layer between the first substrate and the second substrate (Fig. 1); wherein the adhesive film layer comprises a crystalline spherical silica filler (Fig. 2, first thermal conductive members 12; para. 27 "the first thermal conductive members 12 may include… crystalline silicon oxide", silicon oxide is commonly known as silica) in a matrix (10). It would have been obvious to one of ordinary skill in the art before the time of the effective filing of the invention to modify Woychik according to the teachings of Lee such that the adhesive film would be positioned between the first and second substrates, and the adhesive film layer would comprise a crystalline silica filler in a matrix, in order to mitigate heat between the two substrates using a filler as is common in the art. Woychik in view of Lee still does not disclose a spherical filler in the adhesive film layer. On the other hand, JP 5293496 B2 discloses an adhesive film comprising a crystalline spherical silica filler in a matrix (Bottom of pg. 1 "The adhesive composition comprises a resin and a filler.", where the resin corresponds to the polymer matrix; "The filler has a spherical form"; Pg. 4 "Examples of the filler include… silica"). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Woychik in view of Lee according to the teachings of JP 5293496 B2 such that the crystalline silica filler would have a spherical in order to ensure minimize the viscosity of the adhesive material during manufacturing, thereby improving the uniformity of the resulting adhesive film layer and reducing the risk of clogging when the adhesive film layer is being formed. Woychik in view of Lee and JP 5293496 B2 still does not disclose and wherein a thermal conductivity of the spherical silica filler is about 5.5 W/m·K to about 30 W/m·K. However, Sato discloses wherein a thermal conductivity of the spherical silica filler is about 5.5 W/m·K to about 30 W/m·K (Para. 6 "In particular, since quartz has a denser crystal structure than other crystals, the thermal conductivity is as high as 12.8 W/mK, and spherical silica particles containing a large amount of quartz are considered to have a high thermal conductivity", where quartz is known to be a form of silica). It would have been obvious to one of ordinary skill before the time of effective filing of the invention to modify Woychik in view of Lee and JP 5293496 B2 according to the teachings of Sato such that the thermal conductivity of the spherical filler would be about 5.5 W/m·K to about 30 W/m·K, in order to ensure that the silica filler is capable of managing the heat produced during the operation or manufacturing of the semiconductor package. Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woychik (US 20150270209 A1) in view of Lee (US 20200211920 A1), Sato (US 20200148544 A1) and JP 5293496 B2 as applied to claims 1, 8 and 22 above, and further in view of Hofstetter (US 20150284608 A1). Regarding claim 2, Woychik in view of Lee, Sato, and JP 5293496 B2 discloses the semiconductor package of claim 1. However, Woychik in view of Lee, Sato and JP 5293496 B2 does not explicitly disclose wherein a content of the spherical silica filler in the adhesive film layer is about 1 weight% to about 90 weight%. On the other hand, Hofstetter discloses wherein a content of the spherical silica filler in the adhesive film layer is about 1 weight% to about 90 weight% (Para. 36 "0 to 50 wt. % fillers"). It would have been obvious to one of ordinary skill in the art before the time of the effective filing of the invention to modify Woychik in view of Lee, Sato and JP 5293496 B2 according to the teachings of Hofstetter such that a content of the spherical silica filler in the adhesive film layer would be about 1 weight% to 90 weight%, in order to ensure that the amount of filler is sufficiently high to maintain a high thermal conductivity, while remaining sufficiently low to maintain a thin, uniform and workable adhesive layer. Regarding claim 3, Woychik in view of Lee, Sato and JP 5293496 B2 discloses the semiconductor package of claim 1. However, Woychik in view of Lee, Sato and JP 5293496 B2 does not explicitly disclose wherein the spherical silica filler comprises coesite or cristobalite. On the other hand, Hofstetter discloses wherein the spherical silica filler comprises coesite or cristobalite (Para. 31 "the two-component epoxy adhesive comprises… additives such as those that are customary for epoxy resin adhesives. Examples of optional additives are fillers"; para. 100 "Optionally one or more fillers may be used… Examples are… cristobalite"). It would have been obvious to one of ordinary skill in the art before the time of the effective filing of the invention to modify Woychik in view of Lee, Sato and JP 5293496 B2 according to the teachings of Hofstetter such that the spherical filler would comprise cristobalite, in order to improve the translucence of the adhesive layer by using a filler with a relatively low refractive index. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woychik (US 20150270209 A1) in view of Lee (US 20200211920 A1), Sato (US 20200148544 A1) and JP 5293496 B2 as applied to claims 1, 8 and 22 above, and further in view of “Refractive Indices of Fused Silica at Low Temperatures" (Waxler et al.), hereinafter referred to as Waxler. Regarding claim 4, Woychik in view of Lee, Sato and JP 5293496 B2 discloses the semiconductor package of claim 1. However, Woychik in view of Lee, Sato and JP 5293496 B2 does not explicitly disclose wherein a refractive index of the spherical silica filler is about 1.65 or less. PNG media_image1.png 353 638 media_image1.png Greyscale On the other hand, Waxler discloses the refractive index of silica being about 1.65 or less (see table below). It would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to incorporate the teachings of Waxler in order to maintain a sufficiently translucent adhesive layer such that alignment markers can be detected during manufacturing. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woychik (US 20150270209 A1) in view of Lee (US 20200211920 A1), Sato (US 20200148544 A1) and JP 5293496 B2 as applied to claims 1, 8 and 22 above, and further in view of Iwayama (US 20150016072 A1). Regarding claim 5, Woychik in view of Lee, Sato and JP 5293496 B2 discloses the semiconductor package of claim 1. However, Woychik in view of Lee, Sato and JP 5293496 B2 does not explicitly disclose wherein a sphericity of the spherical silica filler is about 0.8 to about 1. On the other hand, Iwayama discloses wherein a sphericity of the spherical silica filler is about 0.8 to about 1 (Para. 146 "a sphericity of the spherical silica… is not less than 0.8."). It would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to modify Woychik in view of Lee, Sato and JP 5293496 B2 according to the teachings of Iwayama such that the sphericity of the silica filler would be between 0.8 to 1, in order to improve the uniformity of shape and thickness of the adhesive layer. Allowable Subject Matter Claims 9-17 and 21 allowed. The following is an examiner’s statement of reasons for allowance: The prior art fails to disclose a semiconductor package comprising: a package substrate; an interposer substrate on the package substrate; a first semiconductor device on the interposer substrate and comprising a plurality of stacked semiconductor chips; a second semiconductor device adjacent the first semiconductor device and on the interposer substrate, and a molding member surrounding the side surfaces of the plurality of stacked semiconductor chips, wherein the first semiconductor device further comprises an adhesive film layer between adjacent ones of the plurality of stacked semiconductor chips, wherein the adhesive film layer comprises a matrix and a crystalline silica filler dispersed in the matrix, and a content of the crystalline silica filler is about 30 weight% to about 90 weight% with respect to a weight of the adhesive film layer, and wherein a side surface of the adhesive film layer on a lowermost one of the plurality of stacked semiconductor chips is coplanar with a side surface of the lowermost one of the plurality of stacked semiconductor chips and a side surface of the molding member. Specifically, the prior art fails to disclose a side surface of the adhesive film layer on a lowermost one of the plurality of stacked semiconductor chips being coplanar with a side surface of the lowermost one of the plurality of stacked semiconductor chips and a side surface of the molding member. For this reason, claims 10-17 and 21 are also allowable as dependents of claim 9. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant's arguments filed 12/4/2025 have been fully considered but they are not persuasive. As noted in the Advisory Action mailed on 12/23/2025, the indication of allowability previously provided with respect to former claim 6 has been withdrawn in light of newly found prior art. Therefore, incorporation of those limitations into amended claim 1 and newly added claim 22 does not place either claim in condition for allowance. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S.J.S./Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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Prosecution Timeline

Jun 20, 2022
Application Filed
Jun 10, 2025
Non-Final Rejection — §103
Jul 11, 2025
Interview Requested
Jul 21, 2025
Examiner Interview Summary
Jul 21, 2025
Applicant Interview (Telephonic)
Sep 04, 2025
Response Filed
Oct 01, 2025
Final Rejection — §103
Dec 04, 2025
Response after Non-Final Action
Jan 06, 2026
Request for Continued Examination
Jan 20, 2026
Response after Non-Final Action
Jan 26, 2026
Non-Final Rejection — §103
Mar 03, 2026
Interview Requested
Mar 11, 2026
Examiner Interview Summary
Mar 11, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
84%
With Interview (+0.7%)
3y 5m
Median Time to Grant
High
PTA Risk
Based on 35 resolved cases by this examiner. Grant probability derived from career allow rate.

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