DETAILED ACTION
This Office action responds to Applicant’s RCE amendments filed on 09/18/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection mailed on 06/24/2024. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/18/2025 has been entered.
Amendment Status
The amendment filed as an RCE submission on 09/18/2025, responding to the Office action mailed on 09/18/2025 has been entered. The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-11, 13-17, and 28.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-8, 11, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Lau (US 2021/0202407) in view of Camacho (US 2009/0166785) in view of Bathan (US 2009/0140394) in further view of Kim (US 2022/0359420).
Regarding claim 1, Lau shows (see, e.g., Lau: figs. 1J and 2) the most aspects of the instant invention including a semiconductor package 100a, comprising:
A package substrate 170
A semiconductor chip 110 on the package substrate 170
A mold layer 130 on the package substrate 170
wherein:
The mold layer 130 has a first side surface and a first trench 140
The first trench 140 extends from a top surface 132 of the mold layer 130 toward a bottom surface 134 of the mold layer 130
An antenna pattern 164 on the mold layer 130
A first connection terminal 140 filling the first trench 140
wherein:
The antenna pattern 164 is electrically connected to the package substrate 170 through the first connection terminal 140
A substrate pad 155 on a top surface of the package substrate 170 and coupled with the first connection terminal 140
Lau, however, fails (see, e.g., Lau: figs. 1J and 2) to show that the first trench 140 is disposed at the first side surface of the mold layer 130. Camacho, in a similar semiconductor package to Lau, teaches (see, e.g., Camacho: figs. 5a and 5d) a first trench 64 disposed at the first side of the mold layer 68 (see, e.g., par. [0035]). Camacho also teaches that the first trenches are through hole via (THV) filled with conductive material, which are integrated in semiconductor packages by providing short electrical conduction paths from the active device to the package substrate in order to reduce signal propagation, to have lower capacitance, and achieve overall better circuit performance (see, e.g., Camacho: abstract and par. [0004]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the first trench of Camacho in the semiconductor package of Lau to provide short electrical conduction paths from the active device to the package substrate in order to reduce signal propagation, to have lower capacitance, and achieve overall better circuit performance.
Lau, however, fails (see, e.g., Lau: figs. 1J and 2) to show that the first trench 140 is disposed at the first side surface of the mold layer 130. Camacho, in a similar semiconductor package to Lau, teaches (see, e.g., Camacho: figs. 5a and 5d) a first trench 64 disposed at the first side of the mold layer 68 (see, e.g., Camacho: par. [0035]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the first trench of Lau or the first trench of Camacho because these were recognized in the semiconductor art for their use as trenches through mold layer in the semiconductor packages, as taught by Lau and by Camacho, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
The Lau in view of Camacho fails to teach (see, e.g., Lau: figs. 1J and 2) that a side surface of the substrate pad 155 is vertically aligned with a side surface of the first connection terminal 140. Lau further shows (see, e.g., Lau: figs. 1J and 2) that the side surface of the substrate pad 155 is not vertically aligned with a side surface of the first connection terminal 140.
Bathan, in a similar semiconductor package to Lau in view of Camacho, teaches (see, e.g., Bathan: fig. 3f) that a side surface of the substrate pad 92 is vertically aligned with a side surface of the first connection terminal 86. Bathan also teaches that the substrate pad 92 is designed to operate as an intermediate conduction layer to route electrical signals between the first connection terminal 86 and UBMs 94 (see, e.g., Bathan: par. [0039]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the substrate pad with a side surface vertically aligned with a side surface of the first connection terminal in the device of Lau in view of Camacho, as taught by Bathan, to operate as an intermediate conduction layer to route electrical signals between the first connection terminal and UBMs.
Lau in view of Camacho fails to teach (see, e.g., Lau: figs. 1J and 2) that a side surface of the substrate pad 155 is vertically aligned with a side surface of the first connection terminal 140. Lau further shows (see, e.g., Lau: figs. 1J and 2) that the side surface of the substrate pad 155 (is not vertically aligned with a side surface of the first connection terminal 140. However, Bathan, in a similar semiconductor package to Lau in view of Camacho, teaches (see, e.g., Bathan: fig. 3f) that a side surface of the substrate pad 92 is vertically aligned with a side surface of the first connection terminal 86.
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the vertically non-aligned substrate pad of Lau/Camacho or the vertically aligned substrate pad of Bathan because these were recognized in the semiconductor art for their use as substrate pads in the semiconductor packages, as taught by Lau in view of Camacho and by Bathan, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Lau in view of Camacho in view of Bathan fails to teach (see, e.g., Lau: figs. 1J and 2) that the mold layer 130 covers an entire top surface of the semiconductor chip 110. Kim, in a similar semiconductor package to Lau in view of Camacho in view of Bathan, teaches (see, e.g., Kim: fig. 2h) that the mold layer 270 covers the entire top surface of the semiconductor chip 262. Kim further shows (see, e.g., Kim: fig. 2h) that the mold layer 270 allows to envelop mounted devices such as the liquid encapsulant can be deposited without issues related to encapsulant 270 flowing between units (see, e.g., Kim: par. [0036]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the mold layer to cover an entire tip surface of the semiconductor chip in the device of Lau in view of Camacho in view of Bathan, as taught by Kim, to to envelop mounted devices such as the liquid encapsulant can be deposited without issues related to encapsulant flowing between units.
Lau in view of Camacho in view of Bathan in view of Kim shows (see, e.g., Kim: fig. 2h) that the antenna pattern 280 directly contacts an upper surface of the mold layer 270.
Regarding claim 2, Lau in view of Camacho in view of Bathan in view of Kim (see, e.g., Camacho: figs. 5a and 5d) shows that:
The first side surface of the mold layer 68 exposes the side surface of the first connection terminal 64
The side surface of the first connection terminal 64 is coplanar with the first side surface of the mold layer 68
Regarding claim 3, Lau in view of Camacho in view of Bathan in view of Kim (see, e.g., Canacho: figs. 5a and 5d) shows that, when viewed in a plan view, the first trench 64 is provided at a center region of the first side surface of the mold layer 68.
Regarding claim 4, Lau in view of Camacho in view of Bathan in view of Kim (see, e.g., Camacho: figs. 5a and 5d) shows that a top surface of the first connection terminal 64 has a semi-circular shape, when viewed in a plan view.
Regarding claim 5, Lau in view of Camacho in view of Bathan in view of Kim teaches (see, e.g., Bathan: fig. 3f) that a side surface of the substrate pad 92 is vertically aligned with a side surface of the first connection terminal 86.
Regarding claim 6, Lau in view of Camacho in view of Bathan in view of Kim (see, e.g., Lau: figs. 1J and 2) shows that the first trench 140 exposes a top surface of the substrate pad 155.
Regarding claim 7, Lau in view of Camacho in view of Bathan in view of Kim (see, e.g., Lau: figs. 1J and 2) shows that the first connection terminal 140 is connected to a top surface of the substrate pad 155.
Regarding claim 8, Lau in view of Camacho in view of Bathan in view of Kim (see, e.g., Lau: figs. 1J and 2) shows that:
The mold layer 130 further includes a second side surface adjacent to the first side surface
Each of the first side surface and the second side surface of the mold layer 130 is coplanar with a corresponding side surface of the two adjacent side surfaces of the package substrate 170
Regarding claim 11, Lau in view of Camacho in view of Bathan in view of Kim (see, e.g., Camacho: figs. 5a and 5d) shows that the mold layer 68 has a third side surface and a second trench 64 disposed at the third side surface. Also, Lau (see, e.g., Lau: figs. 1J and 2) shows that:
The second trench 140 has a line shape extending from the top surface 132 of the mold layer 130 toward the bottom surface 134 of the mold layer 130
The antenna pattern 164 is electrically connected to the package substrate 170 through a second connection terminal 140 filling the second trench 140
Regarding claim 28, Lau in view of Camacho in view of Bathan in view of Kim (see, e.g., Kim: figs. 2g and 2h) shows that the antenna pattern 280 is provided in plural, and wherein the plurality of antenna patterns 280 are arranged on the entire top surface of the semiconductor chip 264 periodically in rows and columns.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lau in view of Camacho in view of Bathan in view of Kim in further view of Hong (US 2008/0290479).
Regarding claim 9, Lau in view of Camacho in view of Bathan in view of Kim shows the most aspects of the instant invention including a semiconductor package 100a (see, e.g., Lau: figs. 1J and 2), comprising a package substrate 170, a semiconductor chip 110 on the package substrate 170 and a first trench 64, where a first connection terminal 64 in in the first trench.
However, Lau in view of Camacho in view of Bathan in view of Kim fails to teach that the first trench is disposed at the corner of the mold layer. Moreover, Lau in view of Camacho in view of Bathan in view of Kim shows (see, e.g., Lau: figs. 1J and 2) that the first trench is on the lateral side of the mold layer 68. Hong, in a similar device to Lau in view of Camacho in view Bathan in view of Kim, shows (see, e.g., Hong: figs. 5A and 5B) that the first trench 500 is disposed at the corner of the mold layer 200 (see, e.g., Hong: par. [0052]). Hong further shows that the first trench 500 is disposed at the corner of the mold layer 200 (see, e.g., Hong: par. [0052]) transfers the electrical signal from the device of the device region 300 or applies a voltage to the device of the device region 300 through the lead frames 310 that are electrically connected to the electroconductive patterns 220 (see, e.g., Hong: par. [0055]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the first trench disposed at the corner of the mold layer in the device of Lau in view of Camacho in view Bathan in view of Kim, as taught by Hong, to transfer the electrical signal from the device or apply a voltage to the device through the lead frames that are electrically connected to the electroconductive patterns.
However, Lau in view of Camacho in view of Bathan in view of Kim fails to teach that the first trench is disposed at the corner of the mold layer. Moreover, Lau in view of Camacho in view Bathan in view of Kim shows (see, e.g., Lau: figs. 1J and 2) that the first trench is on the lateral side of the mold layer 68. Hong, in a similar device to Lau in view of Camacho in view Bathan in view of Kim, shows (see, e.g., Hong: figs. 5A and 5B) that the first trench 500 is disposed at the corner of the mold layer 200 (see, e.g., Hong: par. [0052]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the first trench disposed on the lateral side of the mold layer of Lau in view of Camacho in view Bathan in view of Kim or the first trench disposed at the corner of the mold layer of Hong because these were recognized in the semiconductor art for their use as trenches in the semiconductor packages, as taught by Lau in view of Camacho in view Bathan in view of Kim and by Hong, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Lau in view of Camacho in view Bathan in view of Kim in view of Hong (see, e.g., Hong: figs. 5A and 5B) also shows that:
The side surface of the first connection terminal 500 has a first side surface and a second side surface connected to the first side surface and the second side surface of the mold layer 200, respectively
The first side surface and the second side surface of the first connection terminal 500 are coplanar with the first side surface and the second side surface of the mold layer 200, respectively
Regarding claim 10, Lau in view of Camacho in view Bathan in view of Kim in view of Hong (see, e.g.,Hong: figs. 5A and 5B) also shows that a top surface of the first connection terminal 500 has a sector shape of a circle, when viewed in a plan view.
Claims 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lau (US 2021/0202407) in view of Camacho (US 2009/0166785) in view of Jou (US 2017/0294697) in further view of Kim (US 2022/0359420).
Regarding claim 13, Lau shows (see, e.g., Lau: figs. 1J and 2) the most aspects of the instant invention including a semiconductor package 100a, comprising:
A package substrate 170 with a substrate pad 155
A semiconductor chip 110 on the package substrate 170
A mold layer 130 on the package substrate 170 to cover the semiconductor chip 110
An antenna pattern 164 on the mold layer 130
A first connection terminal 140 extending toward the package substrate 170
A second connection terminal 140 extending toward the package substrate 170
The antenna pattern 164 is connected both to the first connection terminal 140 and the second connection terminal 140 (see, e.g., figs. 1J and 2, where there are two elements 140 as first and second connection terminals)
Lau, however, fails (see, e.g., Lau: figs. 1J and 2) to show that the first connection terminal 140 extends along a first side surface of the mold layer 130 and the second connection terminal extends along a second side surface of the mold layer 130. Camacho, in a similar semiconductor package to Lau, teaches (see, e.g., Camacho: figs. 5a and 5d) a first connection terminal 64 disposed at the first side of the mold layer 68 and the second connection terminal 64 disposed at the first side of the mold layer 68 (see, e.g., Camacho: par. [0035]). Camacho also teaches that the first and second connection terminals are through hole via (THV) filled with conductive material, which are integrated in semiconductor packages by providing short electrical conduction paths from the active device to the package substrate in order to reduce signal propagation, to have lower capacitance, and achieve overall better circuit performance (see, e.g., Camacho: abstract and par. [0004]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the connection terminal of Camacho in the semiconductor package of Lau to provide short electrical conduction paths from the active device to the package substrate in order to reduce signal propagation, to have lower capacitance, and achieve overall better circuit performance.
Lau, however, fails (see, e.g., Lau: figs. 1J and 2) to show that the first connection terminal 140 extends along a first side surface of the mold layer 130 and the second connection terminal extends along a second side surface of the mold layer 130. Camacho, in a similar semiconductor package to Lau, teaches (see, e.g., Camacho: figs. 5a and 5d) a first connection terminal 64 disposed at the first side of the mold layer 68 and the second connection terminal 64 disposed at the first side of the mold layer 68 (see, e.g., Camacho: par. [0035]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the first and second connection terminals of Lau or the first and second connection terminals of Camacho because these were recognized in the semiconductor art for their use as connection terminals through mold layer in the semiconductor packages, as taught by Lau and by Camacho, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Lau in view of Camacho fails (see, e.g., Lau: figs. 1J and 2) to show that the substrate pad 155 includes a first side surface that is vertically aligned with the first side surface of the mold layer 130.
Jou, in a similar semiconductor package to Lau in view of Camacho, shows (see, e.g., Jou: fig. 24) a substrate pad 106/110 having a side surface vertically aligned with a side surface mold layer 612 (see, e.g., Jou: par. [0049]). Jou also shows that the substrate pad 106/110 is used as a coupling signal transmission electrode (see, e.g., Jou: par. [0016]) and the substrate pad position vertically aligned with the side surface of the mold layer is to improve the design of the redistribution layer (RDL) in a certain semiconductor package (see, e.g., figs. 20-24).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the substrate pad of Jou in the semiconductor package of Lau in view of Camacho to improve the design of the redistribution layer (RDL) in a certain semiconductor package.
Lau in view of Camacho also fails (see, e.g., Lau: figs. 1J and 2) to show that the substrate pad 155 includes a first side surface that is vertically aligned with the first side surface of the mold layer 130. Jou, in a similar semiconductor package to Lau in view of Camacho, teaches (see, e.g., Jou: fig. 24) a substrate pad 106/110 having a side surface vertically aligned with a first side surface of the mold layer 130.
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the substrate pad of Lau in view of Camacho or the substrate pad of Jou because these were recognized in the semiconductor art for their use as signal transmitting substrate pads in the semiconductor packages, as taught by Lau in view of Camacho and by Jou, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Lau in view of Camacho in view of Jou fails (see, e.g., Lau: figs. 1J and 2) to show that the antenna pattern 164 directly contacts an upper surface of the mold layer 130. Kim, in a similar semiconductor package to Lau in view of Camacho in view of Jou, teaches (see, e.g., Kim: fig. 2h) that the antenna pattern 280 directly contacts an upper surface of the mold layer 270. Kim further shows (see, e.g., Kim: fig. 2h) that antenna pattern 280 directly contacts an upper surface of the mold layer 270 to allow the antenna being patterned from the shielding layer 276 such as the antenna pattern being outside the shielding pattern in order to receive electromagnetic fields (see, e.g., Kim: par. [0039]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the antenna pattern that directly contacts an upper surface of the mold layer in the device of Lau in view of Camacho in view of Jou, as taught by Kim, to allow the antenna being patterned from the shielding layer such as the antenna pattern being outside the shielding pattern in order to receive electromagnetic fields.
Lau in view of Camacho in view of Jou in view of Kim (see, e.g., Kim: figs. 2g and 2h) shows that the antenna pattern 280 is provided in plural, and wherein the plurality of antenna patterns 280 are arranged on the entire top surface of the semiconductor chip 264 periodically in rows and columns.
Regarding claim 14, Lau in view of Camacho in view of Jou in view of Kim (see, e.g., Camacho: figs. 5a and 5d) shows that:
The mold layer 68 has a first trench 64 disposed at the side surface and a second trench 64 disposed at the second side surface
Each of the first trench 64 and the second trench 64 has a line shape vertically penetrating the mold layer 68
The first connection terminal 64 and the second connection terminal 64 fills the trench 64
Regarding claim 15, Lau in view of Camacho in view of Jou in view of Kim (see, e.g., Camacho: figs. 5a and 5d) shows that:
The first connection terminal 64 has a side surface
The first side surface of the mold layer 68 is connected to the side surface of the first connection terminal 64
The side surface of the connection terminal 64 is coplanar with the first side surface of the mold layer 68
Regarding claim 16, Lau in view of Camacho in view of Jou in view of Kim (see, e.g., Lau: figs. 1J and 2) shows that:
The first trench 140 exposes a top surface of the substrate pad 155
The first connection terminal 140 is connected to the top surface of the substrate pad 155
Regarding claim 17, Lau in view of Camacho in view of Jou in view of Kim (see, e.g., Camacho: figs. 5a and 5d) shows that a top surface of the first connection terminal 64 has a sector shape of a circle or a semi-circular, when viewed in a plan view.
Response to Arguments
Examiner has read and considered Applicants’ arguments, and finds them to be unpersuasive in view of the new grounds of rejection. The applicability of the new references to the amended elements is discussed in the claim rejections above.
The applicants argue:
Lau fails to disclose or otherwise render obvious the following limitations of "… the mold layer covers an entire top surface of the semiconductor chip”, “… the antenna pattern directly contacts an upper surface of the mold layer”, and “the antenna pattern is provided in plural, and wherein the plurality of antenna patterns are arranged on the entire top surface of the semiconductor chip periodically in rows and columns”, as recited in claims 1 and 13.
The examiner responds:
In view of the new grounds of rejection, see, e.g., Kim: figs. 2g and 2h, where Kim, in a similar semiconductor package to Lau in view of Camacho in view of Bathan, teaches (see, e.g., Kim: fig. 2h) that the mold layer 270 covers the entire top surface of the semiconductor chip 262. Kim further shows (see, e.g., Kim: fig. 2h) that the mold layer 270 allows to envelop mounted devices such as the liquid encapsulant can be deposited without issues related to encapsulant 270 flowing between units (see, e.g., Kim: par. [0036]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the mold layer to cover an entire tip surface of the semiconductor chip in the device of Lau in view of Camacho in view of Bathan, as taught by Kim, to to envelop mounted devices such as the liquid encapsulant can be deposited without issues related to encapsulant flowing between units.
Lau in view of Camacho in view of Bathan in view of Kim shows (see, e.g., Kim: fig. 2h) that the antenna pattern 280 directly contacts an upper surface of the mold layer 270.
Also, Lau in view of Camacho in view of Jou in view of Kim (claim 13) or Lau in view of Camacho in view of Bathan in view of Kim (claim 1) (see, e.g., Kim: figs. 2g and 2h) shows that the antenna pattern 280 is provided in plural, and wherein the plurality of antenna patterns 280 are arranged on the entire top surface of the semiconductor chip 264 periodically in rows and columns.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814