DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 01/20/2026 with respect to the rejections of claims 1-11 under 35 U.S.C. 102 have been fully considered but they are not persuasive. While the response thoroughly identifies differences between the Applicant’s invention and the prior art reference Javier, the broadest reasonable interpretation of the claimed set of conductive leads does allow Javier to fully read upon the claimed invention. It is not unreasonable to include the unused reference numerals 304, 304 and 306 in Figure 3 as part of the conductive leads 303, even if those specific components are not conductive. These reference numerals label parts of a single component that appear to penetrate the encapsulant on both the bottom and sides of the chip package in Figure 3, which reads upon the claimed language. Additionally, Figure 3 does not depict an incomplete device as evidenced by reference numerals 101 and 102 and paragraph [0013] of Javier. Reference numerals 101 and 102 are shared between Figure 1 and Figure 3 of Javier. The rejection is therefore maintained and is made final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Javier et al. (US-20150014832-A1 – hereinafter Javier).
Regarding claim 1, Javier teaches an electronic device (Fig.4A 100; ¶0025), comprising:
a package structure (Fig.4A 130; ¶0025) having a first side (bottom side), a second side (top side), a third side (Fig.4A 101; ¶0018), a fourth side (Fig.4A 102; ¶0018), and a fifth side (hypotenuse side), the first side (bottom side) extending in a first plane of orthogonal first and second directions (flat bottom plane), the second side (top side) extending in a second plane of the first and second directions (flat top plane), the second side (top side) spaced apart from the first side (bottom side) along a third direction (vertical direction) that is orthogonal to the first and second directions (horizontal directions), the third side (101) extending along the third direction (vertical direction) from the first side (bottom side) to the second side (top side), the third side (101) extending along the second direction from the fourth side (102) to the fifth side (hypotenuse side), the fourth side (102) extending along the third direction (vertical direction) from the first side (top side) to the second side (bottom side), the fourth side (102) extending along the first direction from the third side (101) to the fifth side (hypotenuse side), and the fifth side (hypotenuse side) extending from the third side (101) to the fourth side (102);
a semiconductor die (Fig.4A 310; ¶0025); and
a set of conductive leads (Fig.4A 303; ¶0025) along the third side (101), one of the set of conductive leads (Fig.4A left 303) electrically coupled to a conductive terminal of the semiconductor die (310);
wherein the package structure (130) encloses a portion of the semiconductor die (310) and portions of the set of conductive leads (303), and the package structure (130) exposes further portions of the set of conductive leads (303) along the first side (bottom side), and additional portions of the set of conductive leads (303) along the third side (101).
Regarding claim 2, Javier teaches the electronic device of claim 1, wherein a third plane of the third side (101) and a fourth plane of the fourth side (102) are at a first angle (these sides form an angle), a fifth plane of the fifth side (hypotenuse side) and the fourth plane (102) are at a second angle (these sides form an angle), the third (101) and fifth planes (hypotenuse side) are at a third angle (these sides form an angle), and the first angle is greater than the second and third angles (the embodiment in Fig.4A depicts a right triangle, so the angle formed by 101 and 102 is the greatest).
Regarding claim 3, Javier teaches the electronic device of claim 2, wherein the first angle is approximately 90°, the second angle is approximately 45°, and the third angle is approximately 45° (the embodiment in Fig.4A depicts a right triangle, so this claim is met).
Regarding claim 4, Javier teaches The electronic device of claim 2, wherein the second and third angles are equal (the embodiment in Fig.4A depicts a right triangle, so this claim is met).
Regarding claim 5, Javier teaches the electronic device of claim 1, further comprising a die attach pad (Fig.4A center portion of 302; ¶0025) and a tie bar (Fig.4A a single extension of 302 reaching the outer edges of 130), wherein:
the semiconductor die (310) is mounted on the die attach pad (center portion of 302);
the tie bar (single extension of 302) is connected to the die attach pad (center portion of 302); and
a portion of the tie bar (single extension of 302) is exposed along one of the third (101), fourth (102), and fifth (hypotenuse side) sides of the package structure (130).
Regarding claim 6, Javier teaches the electronic device of claim 5, wherein the tie bar (single extension of 302) is exposed along the fifth side (hypotenuse side) of the package structure (130).
Regarding claim 7, Javier teaches the electronic device of claim 6, further comprising a second tie bar (Fig.4A back extensions of 302), the second tie bar (back extensions of 302) exposed along one of the third (101) and fourth (102) sides of the package structure (130).
Regarding claim 8, Javier teaches the electronic device of claim 6, wherein the tie bar (single extension of 302) is exposed along one of the third (101) and fourth (102) sides of the package structure (130).
Regarding claim 9, Javier teaches the electronic device of claim 5, wherein the tie bar (single extension of 302) is spaced apart from the first side (bottom side) of the package structure along the third direction (vertical direction; see Fig.4B).
Regarding claim 11, Javier teaches the electronic device of claim 1, further comprising a second set of conductive leads (Fig.4A right 303) along the fourth side (102), one of the second set of conductive leads (right 303) electrically coupled to a second conductive terminal of the semiconductor die (310), wherein the package structure (130) encloses portions of the second set of conductive leads (right 303), and the package structure (130) exposes further portions of the second set of conductive leads (right 303) along the first side (bottom side) and additional portions of the second set of conductive leads (right 303) along the fourth side (102).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Javier in view of Lin et al. (US-20210134707-A1 – hereinafter Lin).
Regarding claim 10, Javier teaches the electronic device of claim 5.
Javier does not teach wherein the die attach pad has a rectangular shape with opposite sides parallel to the fifth side of the package structure.
Lin teaches a rectangular die attach pad (Fig.2 210; ¶0041 of Lin).
Shape differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. Additionally, the Applicant has presented no discussion in the specification which convinces the Examiner that the particular shape of the die attach pad is anything more than one of numerous shapes a person of ordinary skill in the art would find obvious for the purpose of mounting a die (In re Dailey, 149 USPQ 47 (CCPA 1976)). It appears that these changes produce no functional differences and therefore would have been obvious.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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