DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Amendment filed on January 20, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 10-12, 15-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over by Zhang et al. (US 2020/0066839, Filed: Aug. 22, 2018, hereinafter Zhang) in view of Kim et al. (US 2017/0200738, hereinafter Kim), and further in view of Wong et al. (US 2022/0328648, Provisional application filed on Apr. 9, 2021; hereinafter Wong).
Regarding claim 1, Zhang discloses for a semiconductor structure comprising that
an I/O device region (I/O device region 100, Fig. 13) comprising a first dielectric spacer (first dielectric material spacer 22L, Fig. 13) and first inner spacers (first inner dielectric spacer 26L, Fig. 13), the first dielectric spacer (22L, Fig. 13) separating a first source/drain contact (first source/drain contact structure 54L, Fig. 13) and an upper portion of a first gate region (first gate cap 52L, Fig. 13), and the first inner spacers (26L, Fig. 13) are located between a first vertical stack of nanosheets (first semiconductor channel material nanosheet 18NS, Fig. 13) and separating a first source/drain region (first source/drain structure 28L, Fig. 13) from a lower portion of the first gate region (I/O gate conductor portion 50, Fig. 13); and
a core logic device region (logic device region 102, Fig. 13) comprising a second dielectric spacer (second dielectric material spacer 22R, Fig. 13) and second inner spacers (second inner dielectric spacer 26R, Fig. 13), the second dielectric spacer (22R, Fig. 13) separating a second source/drain contact (second source/drain contact structure 54R, Fig. 13) and an upper portion of a second gate region (second gate cap 52R, Fig. 13), and the second inner spacers (26R, Fig. 13) are located between a second vertical stack of nanosheets (second semiconductor channel material nanosheet 14NS, Fig. 13) and separating a second source/drain region (second source/drain structure 28R, Fig. 13) from a lower portion of the second gate region (logic device gate conductor portion 40, Fig. 13).
Zhang does not explicitly disclose that the first inner spacers in the I/O device region are laterally wider than the second inner spacers in the core logic device region.
However, Kim discloses a transistor having gate-all-around structure (Abstract) that the substrate 100 of the device (Figs. 22-23) includes the first region I and the second region II, and “the first region I and the second region II may each be one of, for example, logic region, SRAM regio, and input/output (I/O) region. For example, the first region I and the second region II may be the regions performing a same function, or the regions performing different functions” (emphasis added, [0083]), and therefore, the first region by Kim may perform a function of the logic region and the second region by Kim may perform a function of the I/O region (Figs. 22-23); in this case, the first region I by Kim corresponds to the core logic device region in the claimed invention and the second region II by Kim corresponds to the I/O device region in the claimed invention; the inner spacer 141 in the first region I is located laterally between the first gate electrode 120 and the first source/drain region 150 (Fig. 23), and the inner spacer 242 in the second region II is located laterally between second gate electrode 220 and the second source/drain region 250 (Fig. 23); and the inner spacer 242 in the second region II is laterally wider than the inner spacer 142 in the first region I (i.e., the width SW21 is laterally wider than the width SW11, Fig. 23), therefore, one of ordinary skill in the art would readily recognize that the inner spacers between the gate and the source/drain regions in the I/O region and the core logic region of Zhang could be modified in view of Kim to have different widths in the respective regions, for example, the inner spacer in the I/O device region with a greater width than that in the logic device region, as taught by Kim.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that to modify the gate-all-around field-effect transistor (GAAFET) structure such that the width of the inner spacer between the gate and the source/drain regions in an input/output (I/O) device region is greater than that in a logic device region, as disclosed by Kim, and such a modification would have been an obvious design choice to improve device reliability by reducing electric field concentration and/or mitigating hot-carrier effect in the I/O transistors, while maintaining high performance in the logic device region.
Further regarding claim 1, Zhang in view of Kim differs from the claimed invention by not showing that the upper portion of the first gate region has a width that is greater than the lower portion of the first gate region.
However, Wong discloses for spacer features of nanosheet-based gate-all-around transistors that the device includes that an upper portion of the gate structure 250 and a lower portion of the gate structure 250 (see attached Fig. 1B below), and the gate spacer layer 202 is formed both side of the upper portion of the gate structure 250 and the inner spacer features 206 is formed on both side of the lower portion of the gate structure 250 (Fig. 1B); because Applicants do not specifically claim that the upper portion of the first gate region has a width that is greater than an entirety of the lower portion of the first gate region, the upper portion of the gate structure 250 by Wong has a width that is greater than the center region of the lower portion of the gate structure 250.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that to modify the gate-all-around field-effect transistor (GAAFET) structure such that a width of the upper portion of the gate structure can be greater than a width of the lower portion of the gate structure, as disclosed by Wong, such a modification would have been an obvious design choice to improve device reliability by reducing electric field concentration and/or mitigating hot-carrier effect in the I/O transistors, while maintaining high performance in the logic device region.
Regarding claim 2, Zhang further discloses that the first dielectric spacer (22L, Fig. 13) in the I/O device region (100, Fig. 13) is laterally wider than the second dielectric spacer (22R, Fig. 13) in the core logic device region (102, Fig. 13), because Applicants do not specifically claim that an entirety of the first dielectric spacer is laterally wider than an entirety of the second dielectric spacer, or specify the particular lateral positions at which the widths of the first and second dielectric spacers are measured, the first and second dielectric material spacer 22L and 22R by Zhang have a trapezoidal profile, i.e., wider at the lower portion, therefore, a lower portion of the first dielectric material spacer 22L is laterally wider than an upper portion of the second dielectric material spacer 22R in Zhang (Fig. 13).
Regarding claim 3, Zhang further discloses that the first dielectric spacer (22L, Fig. 13) and the first inner spacers (26L, Fig. 13) are laterally wider than the second dielectric spacer (22R, Fig. 13) and the second inner spacers (26R, Fig. 13), because Applicants do not specifically claim whether each of the first dielectric spacer and first inner spacer is individually laterally wider than each of the second dielectric spacer and second inner spacer, or whether a combined width of the first dielectric spacer and first inner spacer is laterally wider than a combined width of the second dielectric spacer and second inner spacer, a combined width of the lower portion of the first dielectric material spacer 22L and first inner spacer 26L is greater than a combined width of the upper portion of the second dielectric material spacer 22R and second inner spacer 26R in Zhang (Fig. 13).
Regarding claim 4, Zhang further discloses that each nanosheet of the first vertical stack of nanosheets in the I/O device region (each 18NS or channel region 18C in region 100, Fig. 13) is laterally wider than each nanosheet of the second vertical stack of nanosheets in the core logic device region (each 14NS or channel region 14C in 102 region, Fig. 13).
Regarding claim 6, Zhang further discloses that each of the first dielectric spacer (22L, Fig. 13), the first inner spacers (26L, Fig. 13), the second dielectric spacer (22R, Fig. 13), and the second inner spacers (26R, Fig. 13) comprises a solid dielectric material, because “One example of a dielectric spacer material that may be employed in the present application is silicon nitride” (emphasis added, [0048]), therefore it comprises solid silicon nitride dielectric material.
Regarding claim 7, Zhang further discloses that the solid dielectric material that provides the first dielectric spacer (22L, Fig. 13) and the second dielectric spacer (22R, Fig. 13) is compositionally the same as the solid dielectric material that provides the first inner spacers (26L, Fig. 13) and the second inner spacers (26R, Fig. 13), because “In one example, the inner dielectric spacer material is composed of silicon nitride” (emphasis added, [0056]).
Regarding claim 8, Zhang does not explicitly disclose that the solid dielectric material that provides the first dielectric spacer and the second dielectric spacer is compositionally different from the solid dielectric material that provides the first inner spacers and the second inner spacers.
However, Kim further discloses that the first and second outer spacers 141 and 241 correspond to the first and second dielectric spacers in the claimed invention, and the first and second inner spacers 142 and 242 correspond to the claimed invention; and Kim further discloses that “The first outer spacer 141 and the second outer spacer 241 may each include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), silicon oxycarbonitride (SiOCN), and a combination thereof. The first inner spacer 142 and the second inner spacer 242 may each include at least one of, for example, low-k dielectric material, silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), silicon oxycarbonitride (SiOCN), and a combination thereof.” ([0118]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first and second outer spacers 141 and 241 may be formed of a compositionally different dielectric material than that of the first and second inner spacers 142 and 242, as disclosed in paragraph [0118] of Kim. For example, one would form the outer spacers 141/241 of silicon nitride while forming the inner spacers 142/242 of silicon oxide, in order to achieve improved etch selectivity and/or dielectric isolation between gate and source/drain regions, as commonly practiced in the fabrication of gate-all-around FETs.
Regarding claim 10, Zhang further discloses that the first gate region (52L, Fig. 13) has a first channel length (lateral length or width of 18NS, Fig. 13) and the second gate region (52R, Fig. 13) has a second channel length (lateral length or width of 14NS, Fig. 13), and the second channel length (length or width of 14NS, Fig. 13) is less than the first channel length (length or width of 18NS, Fig. 13).
Regarding claim 11, Zhang further discloses that the first source/drain region (28L, Fig. 13) extends outward from a sidewall of each nanosheet of the first vertical stack of nanosheets (sidewall of the vertical stack of the channel 18C, Fig. 13) and the second source/drain region (28R, Fig. 13) extends outward from a sidewall of each nanosheet of the second vertical stack of nanosheets (sidewall of the vertical stack of the channel 14C, Fig. 13).
Regarding claim 12, Zhang further discloses that the I/O device region (100, Fig. 13) is present in a first portion of a semiconductor substrate (left portion of the semiconductor substrate 10, Fig. 13) and the core logic device region (102, Fig. 13) is located in a second portion of the semiconductor substrate (right portion of the semiconductor substrate 10, Fig. 13) which is located laterally adjacent to the first portion of the semiconductor substrate (Fig. 13).
Regarding claim 15, Zhang further discloses for a semiconductor structure comprising that
an I/O device region (100, Fig. 13) comprising a first dielectric spacer (22L, Fig. 13) and first inner spacers (26L, Fig. 13), the first dielectric spacer (22L, Fig. 13) separating a first source/drain contact (54L, Fig. 13) and an upper portion of a first gate region (52L, Fig. 13), and the first inner spacers (26L, Fig. 13) are located between a first vertical stack of nanosheets (vertical stack of 18C, Fig. 13) and separating a first source/drain region (28L, Fig. 13) from a lower portion of the first gate region (50, Fig. 13); and
a core logic device region (102, Fig. 13) comprising a second dielectric spacer (22R, Fig. 13) and second inner spacers (26R, Fig. 13), the second dielectric spacer (22R, Fig. 13) separating a second source/drain contact (54R, Fig. 13) and an upper portion of a second gate region (52R, Fig. 13), and the second inner spacers (26R, Fig. 13) are located between a second vertical stack of nanosheets (vertical stack of 14C, Fig. 13) and separating a second source/drain region (28R, Fig. 13) from a lower portion of the second gate region (40, Fig. 13).
Zhang does not explicitly disclose that the first dielectric spacer in the I/O device region is laterally wider than the second dielectric spacer in the core logic device region.
However, Zhang further discloses that the first and second dielectric material spacer 22L and 22R by Zhang have a trapezoidal profile, i.e., wider at the lower portion, therefore, a lower portion of the first dielectric material spacer 22L is laterally wider than an upper portion of the second dielectric material spacer 22R in Zhang (Fig. 13). Examiner notes that Applicants do not specifically claim that an entirety of the first dielectric spacer is laterally wider than an entirety of the second dielectric spacer, or specify the particular lateral positions at which the widths of the first and second dielectric spacers are measured, therefore, one of ordinary skill in the art would compare widths of the lower portion of the first dielectric material spacer 22L with the upper portion of the second dielectric material spacer 22R.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a dielectric spacer in an I/O device region may be wider than a dielectric spacer in a core logic device region, as disclosed by Zhang.
Further regarding claim 15, Zhang in view of Kim differs from the claimed invention by not showing that the upper portion of the first gate region has a width that is greater than the lower portion of the first gate region.
However, Wong discloses for spacer features of nanosheet-based gate-all-around transistors that the device includes that an upper portion of the gate structure 250 and a lower portion of the gate structure 250 (see attached Fig. 1B below), and the gate spacer layer 202 is formed both side of the upper portion of the gate structure 250 and the inner spacer features 206 is formed on both side of the lower portion of the gate structure 250 (Fig. 1B); because Applicants do not specifically claim that the upper portion of the first gate region has a width that is greater than an entirety of the lower portion of the first gate region, the upper portion of the gate structure 250 by Wong has a width that is greater than the center region of the lower portion of the gate structure 250.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that to modify the gate-all-around field-effect transistor (GAAFET) structure such that a width of the upper portion of the gate structure can be greater than a width of the lower portion of the gate structure, as disclosed by Wong, such a modification would have been an obvious design choice to improve device reliability by reducing electric field concentration and/or mitigating hot-carrier effect in the I/O transistors, while maintaining high performance in the logic device region.
Regarding claim 16, Zhang further discloses that the first dielectric spacer (22L, Fig. 13) and the first inner spacers (26L, Fig. 13) are laterally wider than the second dielectric spacer (22R, Fig. 13) and the second inner spacers (26R, Fig. 13), because Applicants do not specifically claim whether each of the first dielectric spacer and first inner spacer is individually laterally wider than each of the second dielectric spacer and second inner spacer, or whether a combined width of the first dielectric spacer and first inner spacer is laterally wider than a combined width of the second dielectric spacer and second inner spacer, a combined width of the lower portion of the first dielectric material spacer 22L and first inner spacer 26L is greater than a combined width of the upper portion of the second dielectric material spacer 22R and second inner spacer 26R in Zhang (Fig. 13).
Regarding claim 17, Zhang further discloses that each nanosheet of the first vertical stack of nanosheets (each of 18NS of the vertical stack of 18NS or 18C, Fig. 13) in the I/O device region (100, Fig. 13) is laterally wider than each nanosheet of the second vertical stack of nanosheets (each of 14NS of the vertical stack of 14NS or 14C, Fig. 13) in the core logic device region (102, Fig. 13).
Regarding claim 19, claim 19 is rejected for the same reasons discussed in claim 6 above.
Claims 5, 9, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2020/0066839, Filed: Aug. 22, 2018, hereinafter Zhang) in view of Kim et al. (US 2017/0200738, hereinafter Kim) and further in view of Wong et al. (US 2022/0328648, Provisional application filed on Apr. 9, 2021; hereinafter Wong) as applied to claims 1 and 15 above, and further in view of Wu et al. (US 2021/0020741, Filed: Jul. 18, 2019, hereinafter Wu) The teachings of Zhang in view of Kim and further in view of Wong are discussed above.
Regarding claim 5, Zhang in view of Kim and further in view of Wong differs from the claimed invention by not showing that each of the first dielectric spacer, the first inner spacers, the second dielectric spacer, and the second inner spacers comprises an air gap surrounded by a solid dielectric material.
However, Wu discloses for nanosheet transistors with inner airgaps that the device (Fig. 12) includes the spacers between the high-k metal gate 126 and the source/drain regions 62, which correspond to the gate region and the source/drain region in the claimed invention, and the spacer 102 at an upper portion and a lower portion vertically between nanosheets can correspond to the dielectric spacer and inner spacers in the claimed invention, respectively (Fig. 12); and Wu further discloses that airgaps 104 are formed in the spacers 102 at the lower portion and airgaps 104’ are formed in the spacers 102 at the upper portion, and airgaps 104/104’ are surrounded by dielectric material spacers (Fig. 12), therefore, one of ordinary skill in the art would recognize that the inner spacers disclosed by Zhang and Kim can be modified with the spacers having airgaps in Wu, in order to reduce the effective dielectric constant of the spacer region, thereby improving overall device performance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that inner spacers of gate-all-around FETs can include airgaps surrounded by dielectric material, as disclosed by Wu, in order to reduce the effective dielectric constant of the spacer region, thereby improving overall device performance.
Regarding claim 9, Wu further discloses that each of the first dielectric spacer (spacer 102 at an upper left portion, Fig. 12), the first inner spacers (spacer 102 at a lower left portion, Fig. 12), the second dielectric spacer (spacer 102 at an upper right portion, Fig. 12), and the second inner spacers (spacer 102 at a lower right portion, Fig. 12) comprises an air gap (104/104’, Fig. 12), as the same reasons discussed in claim 5 above.
Regarding claim 18, claim 18 is rejected for the same reasons discussed in claim 5 above.
Regarding claim 20, claim 20 is rejected for the same reasons discussed in claim 9 above.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2020/0066839, Filed: Aug. 22, 2018, hereinafter Zhang) in view of Kim et al. (US 2017/0200738, hereinafter Kim) and further in view of Wong et al. (US 2022/0328648, Provisional application filed on Apr. 9, 2021; hereinafter Wong) as applied to claim 12 above, and further in view of Xie et al. (US 9,799,748; hereinafter Xie). The teachings of Zhang in view of Kim are discussed above.
Regarding claim 14, Zhang in view of Kim and further in view of Wong differs from the claimed invention by not showing that the first source/drain region and the second source/drain region are spaced apart from the semiconductor substrate by a dielectric material layer, the dielectric material layer also extends beneath both the first vertical stack of nanosheets and the second vertical stack of nanosheets.
However, Xie discloses for forming inner spacers on gate-all-around FETs that the source/drain material 180 is in direct contact with the buried insulating layer 115 formed on the silicon substrate 110 (Fig. 1K, Col. 5, line 27). Accordingly, the source/drain materials 180 by Xie are separated from the silicon substrate 110 by the buried insulating layer 115, which corresponds to the dielectric material layer in the claimed invention. Furthermore, the buried insulating layer 115 by Xie extends beneath both the left and right vertical stacks of the semiconductor material layer 125 (channel layers, Fig. 1K).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a dielectric or insulating layer can be provided on the topmost portion of a semiconductor substrate, as disclosed by Xie, in order to electrically isolate the active device region and improve the device performance of the GAAFET structure.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815