DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR
1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/12/2026 has been entered.
Response to Amendment
The amendment filed 01/14/2026 has been entered. As directed, claims 1, 4, 7-8, 11, 14-15 and 20
have been amended, no claim have been canceled or added. Thus claims 1-20 remain pending in the application. However, rejection under 35 U.S.C. 112(b) has been made based on the amendment. Additionally, claim 1 is marked as "previously presented." However, claim 1 includes amendments filed 01/14/2026. Therefore, the “previously presented” status appears to be a typo.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20, in “Applicant Arguments/Remarks Made
in an Amendment,” pages 11-13, have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The newly applied reference Mavis (US6127864A) teaches multiple sampling and sample releasing systems are clocked by different clock signals, generate and receive data at different and distinct times using edge-triggered elements. Therefore, the combination of Chalfin in view of Mizrachi and Mavis together teach or suggest limitations of claims 1-6, 8-13 and 15-19, Chalfin in view of Mizrachi and Mavis and Tokuda and Gaillard teach or suggest limitations of claims 7, 14 and 20. Therefore, the rejection under 35 U.S.C. 103 is maintained.
Claim Interpretation
Under the broadest reasonable interpretation in light of specification, the recited first, second and
primary (third) client devices are interpreted as computing or simulation components, including hardware, software executed by a computer system, a processor or processing unit, a virtual machine, a host system, a simulation module, a simulator, a co-simulator, or an equivalent computer-implemented components configured to perform the recited functions.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and
103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8-13 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over
Chalfin US6879948B1 in view of Mizrachi US20110191092A1 and Mavis US6127864A.
Claim 1, Chalfin teaches (Currently Amended) A method comprising:
receiving a circuit design (Col.7, lines 12-24, “Assuming that all relevant System design information is encapsulated in a machine-readable form, the design information can be read to allow creation of a test bench specifically for each DUT of the system.”);
simulating, by a first client device, a first portion of the circuit design within a first simulation environment based on(Col.1, lines 64-66, “Each component is represented as a simulated device under test (DUT) that is incorporated into a simulation module.”Col.3, lines 29-32, “Device under test (DUT) refers to a block of VERILOG code (or other hardware simulation language) that, when executed, Simulates a digital circuit or a portion thereof for testing purposes.” Col.4, lines 58-61, “Simulation modules are illustrated in greater detail in FIG. 3. A given simulation module includes a DUT 305. DUT 305 includes code that, when executed, simulates the operation of the physical circuit corresponding to DUT 305.” Col.5, lines 49-50, “A given Simulation module also includes a programming language interface (PLI) 315.” Col.6, lines 49-50, “Within any given Simulation module, appropriate clock signals must be provided to the DUT.” Col.5, lines 11-18, “Because DUT 305 may include multiple clock domains, test bench 310 provides the necessary clock signal for each clock domain of DUT 305. … Clock signals for the various clock domains of DUT 305 are created by test bench 310.” Col.7, lines 1-7, “Given that test bench 310 is aware of the required clock rates for the various clock domains of DUT 305, test bench 310 provides the necessary clock signals to the clock domains of DUT 305. In particular, test bench 310 provides a clock signal 611 to clock domain 610, provides a clock signal 621 to clock domain 620, and provides a clock signal 631 to clock domain 630.” Col.5, lines 1-2, “DUT 305 requires a set of inputs and one or more clock signals. DUT 305 also produces one or more output signals.” Col.5, lines 8-11, “It is the responsibility of test bench 310 to provide input and clock signals to DUT 305 and to accept outputs produced by DUT 305.” Col.8, lines 42-47, “Simulation modules 110A through 110C are implemented in Software and can therefore be loaded into computer system 900 through any of these means. Likewise, clock arbitrator 105 can also be implemented in software and can therefore be loaded into computer system 900 through any of these means.” Examiner note: the reference teaches a first simulation module 110A (i.e., first client device) executes its own DUT (i.e., first portion of the circuit design) within a self-contained environment that includes a PLI and test bench (i.e., first simulation environment). The test bench generates local clock signals (i.e., first local clock signal) to drive the DUT, which outputs signals (i.e., first simulation data));
simulating, by a second client device, a second portion of the circuit design within a second edge of a second simulation environment based on (Col. 4, lines 32-34, “It is the responsibility of test bench 310 to provide input and clock signals to DUT 305 and to accept outputs produced by DUT 305.” Col.4, lines 58-63, “Simulation modules are illustrated in greater detail in FIG. 3. A given simulation module includes a DUT 305. DUT 305 includes code that, when executed, simulates the operation of the physical circuit corresponding to DUT 305. The component represented by DUT 305 can be a chip, for example.” Col.2, lines 25-27, “The invention described herein can provide clock signals of different rates to different clock domains of an individual DUT during simulation.” Col.2, lines 33-35, “The invention has the advantage of Simulating a complete System of DUTS without creating a Single, excessively large executable image.” Col.5, lines 49-50, “A given Simulation module also includes a programming language interface (PLI)315. The function of the PLI315 is to accept clock credit from a clock arbitrator and to enable the DUT 305 to operate for a number of clock cycles corresponding to the value of the received clock credit.” Col.6, lines 49-50, “Within any given Simulation module, appropriate clock signals must be provided to the DUT.” Col.4, lines 26-35, “Clock arbitrator 105 is responsible for maintaining synchronization of the Simulated System. Maintaining Synchronization entails coordinating the processing of each DUT, AS will be described in greater detail below, Synchronization is maintained by issuance of clock credit. This is illustrated in greater detail in FIG. 2. Clock arbitrator 105 is shown issuing a clock credit 200 to each of simulation modules 110A through 110. Upon receipt of a clock credit 200, each simulation module allows its DUT to operate.” Col.5, lines 13-18, “Test bench 310 first creates a clock Signal having a clock rate equivalent to the least common multiple of the clock rates required by the clock domains of DUT 305. This clock signal is referred to as the master clock signal. Clock signals for the various clock domains of DUT 305 are created by test bench 310.” Col.7, lines 1-7, “Given that test bench 310 is aware of the required clock rates for the various clock domains of DUT 305, test bench 310 provides the necessary clock signals to the clock domains of DUT 305. In particular, test bench 310 provides a clock signal 611 to clock domain 610, provides a clock signal 621 to clock domain 620, and provides a clock signal 631 to clock domain 630.” Col.5, lines 1-2, “DUT 305 requires a set of inputs and one or more clock signals. DUT 305 also produces one or more output signals.” Col.5, lines 8-11, “It is the responsibility of test bench 310 to provide input and clock signals to DUT 305 and to accept outputs produced by DUT 305.” Examiner note: the reference teaches that a second simulation module 110B (i.e., second client device) executes its own DUT (i.e., second portion of the circuit design) within an independent environment that includes a test bench and PLI (i.e., second simulation environment). Each test bench provides its own local clock signal (i.e., second local clock signal) to drive the second DUT, which produces its own output signals (i.e., second simulation data)),
wherein the first local clock signal differs from the second local clock signal (Col.2, lines 25-30, “The invention described herein can provide clock signals of different rates to different clock domains of an individual DUT during simulation. The invention has the additional feature of being able to create a test bench that manages inputs and outputs Specifically for a particular DUT during Simulation.” Col.5, lines 11-18, “Because DUT 305 may include multiple clock domains, test bench 310 provides the necessary clock signal for each clock domain of DUT 305. Test bench 310 first creates a clock Signal having a clock rate equivalent to the least common multiple of the clock rates required by the clock domains of DUT 305. This clock signal is referred to as the master clock signal. Clock signals for the various clock domains of DUT 305 are created by test bench 310.” Col.7, lines 4-7, “In particular, test bench 310 provides a clock signal 611 to clock domain 610, provides a clock signal 621 to clock domain 620, and provides a clock signal 631 to clock domain 630.” Col. 4, lines 32-34, “It is the responsibility of test bench 310 to provide input and clock signals to DUT 305 and to accept outputs produced by DUT 305.” Col.4, lines 34-35, “Upon receipt of a clock credit 200, each simulation module allows its DUT to operate.” Examiner note: the reference teaches multiple simulation modules (e.g., 110A and 110B) each execute their respective DUTs under separate, locally controlled test benches (i.e., first local clock signals differ from second local clock signals)); and
.
However, Chalfin fails to teach a first edge of a first local clock signal, a first edge of a second local clock signal, and receiving, at a primary client device, the first simulation data and the second simulation data at a first edge of a primary clock signal and synchronously with each other, wherein the primary clock signal differs from the first local clock signal and the second local clock signal, wherein the first simulation data and the second simulation data are generated asynchronously with each other and asynchronously with the primary clock signal, and wherein the first edge of the first local clock signal is unaligned with the first edge of the second local clock signal.
Mizrachi teaches receiving, at a primary client device, the first simulation data and the second simulation data at a ([0040], “In some embodiments, simulator 24 and co-simulators communicate using a mechanism that ensures synchronization and data integrity between the various signals and databases in the simulator and co-simulators. The following description refers to a system configuration in which the simulator and co-simulators communicate using VPI.” [0041], “Simulator 24 typically simulates a Verilog design in a sequence of simulation time slots … In the ingress phase the co-simulator reads the values of one or more signals from the simulator … In the egress phase the co-simulator provides the processing results, e.g., updated values of the signals, back to the simulator.” [0053], “When multiple co-simulators 28 (or other units) communicate with simulator 24 using the above-described mechanism, the signals and databases of all these units will remain synchronized. Each co-simulator carries out its ingress, execution and egress phases. In case of non-blocking assignments, the egress phase has to be performed only after all the co-simulators that were triggered in the same time slot have completed their respective ingress phases. A similar synchronization is also needed between a co-simulator and the simulator (even in the case of a single co-simulator).” Examiner note: the reference teaches that simulator 24 communicates with multiple co-simulators 28 through a synchronization mechanism ensuring time alignment and data integrity among all units. Each co-simulator generates updated signal values (i.e., simulation results including first and second simulation data) and transmits them back to simulator 24. The simulator 24 receives these results only after all co-simulators have completed phases within the same simulation time slot, thereby the results from all co-simulators are received synchronously with each other).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chalfin to incorporate the teachings of Mizrachi, and apply a synchronized co-simulation in order to improve synchronization accuracy and enable a primary simulator to receive simulation results from multiple co-simulators synchronously within the same simulation cycle. In this case, Chalfin teaches simulation environment includes multiple simulation modules perform operation under a clock arbitrator which issues timing credits to coordinate each modules’ operation. Mizrachi teaches a synchronized multiple co-simulator includes a primary simulator manages timing alignment and data exchange among co-simulators, and simulation results are received synchronously within a unified simulation time slot. The combination of teaching would predictably provide benefit of improving synchronization accuracy, timing coordination, and computational efficiency by allowing distributed simulation modules to operate under a unified synchronization control, ensuring all simulation results are aligned and received at the same time by the primary simulator.
However, Chalfin and Mizrachi fail to teach a first edge of a first local clock signal, a first edge of a second local clock signal, and a first edge of a primary clock signal, wherein the primary clock signal differs from the first local clock signal and the second local clock signal, wherein the first simulation data and the second simulation data are generated asynchronously with each other and asynchronously with the primary clock signal, and wherein the first edge of the first local clock signal is unaligned with the first edge of the second local clock signal.
Mavis teaches a first edge of a first local clock signal, a first edge of a second local clock signal (Figs 7-8; Col.8, lines 46-66, “The temporal sampling stage 108 contains multiple sampling systems to sample data at input IN at different sampling times … Each sampling system 112, 114, and 116 contains an edge triggered D flip-flop … the D flip-flops 112-116 are triggered on the falling edges of corresponding clock signals CLKA, CLKB, …”. Examiner note: the reference teaches a first edge of a first local clock signal by disclosing that each sampling system includes an edge-triggered D flip-flop clocked by a corresponding clock signal (e.g., CLKA as first local clock signal and CLKB as second local clock signal), and each of them triggered on an edge of the clock signal (e.g., first falling edge of CLKA and first falling edge of CLKB) to sample input data), thereby generating simulation data at first edge of the first and second clock signals), and
a first edge of a primary clock signal (Col.9, “The vote timing system 118 contains three level sensitive latches 128, 130, and 132 that are clocked by a fourth clock signal CLKD.” Col.10, lines 6-8 “In the temporally redundant latch, data is released to the combinatorial logic 104 on the rising edge of sampling clock CLKD …”. Examiner note: the reference teaches a clock CLKD (i.e., primary local clock signal) that controls data release stage, wherein the data from multiple sampling circuits is received and propagated at the rising edge of CLKD, thereby indicating that the receiving operation is performed at a first edge of the primary clock signal), wherein the primary clock signal differs from the first local clock signal and the second local clock signal (Col.9, lines 41-47, “Temporal redundancy in the circuit 100 is achieved by combining a temporal sampling stage 108 with a sample release stage 110 where the sampling is controlled by multiple time-spaced sampling clock signals (i.e., CLKA, CLKB, and CLKC) and the release is invoked by a different voting or release clock signal CLKD.”), wherein the first simulation data and the second simulation data are generated asynchronously with each other and asynchronously with the primary clock signal (Col.8, lines 33-38, “each latch takes multiple, time-spaced samples of the same data input at different and distinct "sampling" times as clocked by different clock signals CLKA, CLKB …The latch 102, 106 then votes on the samples at another "voting" or "release" time, which is again different than the "sampling" times.”), and wherein the first edge of the first local clock signal is unaligned with the first edge of the second local clock signal (Fig.8, edge of CLKA is unaligned with edge of CLKB).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chalfin and Mizrachi to incorporate the teachings of Mavis, and apply edge-triggered clocking and temporally distinct sampling operations in order to improve timing accuracy and better emulate circuit-level timing behavior within a simulation environment. In this case, Chalfin teaches simulation environment includes multiple simulation modules perform operation under a clock arbitrator which issues timing credits to coordinate each modules’ operation. Mizrachi teaches a synchronized multiple co-simulator includes a primary simulator manages timing alignment and data exchange among co-simulators, and simulation results are received synchronously within a unified simulation time slot. Mavis teaches multiple sampling and sample release systems are clocked by different clock signals, generate and receive data at different and distinct sampling times using edge-triggered elements. Because simulation systems are used to model and verify circuit behavior, it would have been obvious to incorporate known clock with edge based timing techniques from circuit implementations into the simulation framework to more accurately represent timing relationships between different clock domains. The combination of teaching would predictably provide benefit of enabling coordinated simulation while incorporating edge-based data generation and temporally distinct clock operations, thereby improving timing flexibility and allowing data to be generated at different clock edges and collected in a coordinated manner.
Claim 2, Chalfin teaches The method of claim 1, wherein the circuit design includes configuration data including the first local clock signal of the first simulation environment, and the second local clock signal of the second simulation environment (Col.3, lines 29-32, “Device under test (DUT) refers to a block of VERILOG code (or other hardware simulation language) that, when executed, Simulates a digital circuit or a portion thereof for testing purposes.” Col.3, lines 34-37, “Test bench refers to code that is ancillary to the DUT but operates in conjunction with the DUT. The test bench manages all inputs and outputs of the DUT, including clock signals, and can be written in VERILOG.” Col.7, lines 4-7, “In particular, test bench 310 provides a clock signal 611 to clock domain 610, provides a clock signal 621 to clock domain 620, and provides a clock signal 631 to clock domain 630.” Col.7, lines 12-24, “Assuming that all relevant System design information is encapsulated in a machine-readable form, the design information can be read to allow creation of a test bench specifically for each DUT of the system.” Examiner note: for each simulation module (i.e., first and second client devices), the associated test bench code as configuration data that defines that module’s simulation environment and specifies the modules’ own clock signal (i.e., first and second local clock signal).
Claim 3, Chalfin teaches The method of claim 2, further comprising:
generating, by the first client device, first sampled values of the first simulation data based on the first local clock signal (Col.3, lines 29-32, “Device under test (DUT) refers to a block of VERILOG code (or other hardware simulation language) that, when executed, Simulates a digital circuit or a portion thereof for testing purposes.” Col.4, lines 58-61, “Simulation modules are illustrated in greater detail in FIG. 3. A given simulation module includes a DUT 305. DUT 305 includes code that, when executed, simulates the operation of the physical circuit corresponding to DUT 305.” Col.5, lines 49-50, “A given Simulation module also includes a programming language interface (PLI)315.” Col.6, lines 49-50, “Within any given Simulation module, appropriate clock signals must be provided to the DUT.” Col.5, lines 11-18, “Because DUT 305 may include multiple clock domains, test bench 310 provides the necessary clock signal for each clock domain of DUT 305. Test bench 310 first creates a clock Signal having a clock rate equivalent to the least common multiple of the clock rates required by the clock domains of DUT 305. This clock signal is referred to as the master clock signal. Clock signals for the various clock domains of DUT 305 are created by test bench 310.” Col.5, lines 1-2, “DUT 305 requires a set of inputs and one or more clock signals. DUT 305 also produces one or more output signals.” Col.5, lines 8-11, “It is the responsibility of test bench 310 to provide input and clock signals to DUT 305 and to accept outputs produced by DUT 305.” Examiner note: the reference teaches each simulation module (i.e., 110A as first client device) executes its own DUT (i.e., first portion of the circuit design) within a self-contained environment that includes a PLI and test bench (i.e., first simulation environment). The test bench generates local clock signals (i.e., first local clock signal) to drive the DUT, which outputs simulation signals (i.e., first simulation data). A POSITA would understand that the DUT executes over discrete clock cycles defined by the first local clock, the generated output signals corresponds to first discrete sampled values of the simulated data generated on each clock tick); and
generating, by the second client device, second sampled values of the second simulation data based on the second local clock signal (Col.3, lines 29-32, “Device under test (DUT) refers to a block of VERILOG code (or other hardware simulation language) that, when executed, Simulates a digital circuit or a portion thereof for testing purposes.” Col.4, lines 58-61, “Simulation modules are illustrated in greater detail in FIG. 3. A given simulation module includes a DUT 305. DUT 305 includes code that, when executed, simulates the operation of the physical circuit corresponding to DUT 305.” Col.5, lines 49-50, “A given Simulation module also includes a programming language interface (PLI)315.” Col.6, lines 49-50, “Within any given Simulation module, appropriate clock signals must be provided to the DUT.” Col.5, lines 11-18, “Because DUT 305 may include multiple clock domains, test bench 310 provides the necessary clock signal for each clock domain of DUT 305. Test bench 310 first creates a clock Signal having a clock rate equivalent to the least common multiple of the clock rates required by the clock domains of DUT 305. This clock signal is referred to as the master clock signal. Clock signals for the various clock domains of DUT 305 are created by test bench 310.” Col.5, lines 1-2, “DUT 305 requires a set of inputs and one or more clock signals. DUT 305 also produces one or more output signals.” Col.5, lines 8-11, “It is the responsibility of test bench 310 to provide input and clock signals to DUT 305 and to accept outputs produced by DUT 305.” Examiner note: the reference teaches each simulation module (i.e., 110B as second client device) executes its own DUT (i.e., second portion of the circuit design) within a self-contained environment that includes a PLI and test bench (i.e., second simulation environment). The test bench generates local clock signals (i.e., second local clock signal) to drive the DUT, which outputs simulation signals (i.e., second simulation data). A POSITA would understand that the DUT executes over discrete clock cycles defined by the first local clock, the generated output signals corresponds to second discrete sampled values of the simulated data generated on each clock tick)), wherein the first sampled values and the second sampled values are generated asynchronously with each other (Col.1., lines 66-67, “Each simulation module can execute as an independent thread in parallel with all other simulation modules. “ Col.5, lines 7-11, “The clock signals, input Signals, and output Signals associated with DUT 305 are managed by a test bench 310. It is the responsibility of test bench 310 to provide input and clock signals to DUT 305 and to accept outputs produced by DUT 305.” Col.5, lines 13-28, “Test bench 310 first creates a clock Signal having a clock rate equivalent to the least common multiple of the clock rates required by the clock domains of DUT 305 … It is the responsibility of test bench 310 to create the needed clock Signals by creating and manipulating the master clock Signal.” Col.5, lines 36-46, “Given the requirement that test bench 310 must manage all inputs and outputs of DUT 305, test bench 310 must be created specifically for DUT 305 … The interface information … can then be used to create a test bench specific for each component.” Examiner note: the reference teaches each simulation modules (e.g., 110A and 110B) executes as an independent thread in parallel with all other simulation modules. Each simulation module includes its own DUT and test bench; the test bench provides clock and input signals to the DUT and manages its outputs. Each test bench creates and manipulates its own master clock signal to drive the associated DUT and is generated specifically for the DUT. A POSITA would understand that each simulation module operates under an independent local clock and produces its simulated output (i.e., sampled values) based on the clock, the modules run in parallel with separately generated local clocks, the output sampled values from the respective modules occur at different timing instants as asynchronously generated with each other).
Claim 4, Chalfin further teaches (Currently Amended) The method of claim 3, wherein the configuration data (Col.3, lines 34-37, “Test bench refers to code that is ancillary to the DUT but operates in conjunction with the DUT. The test bench manages all inputs and outputs of the DUT, including clock signals, and can be written in VERILOG.”).
However, Chalfin fails to teach primary clock signal, and wherein primary client device issues a read command to receive the first and second value.
Mizrachi teaches primary client device issues a read command to receive the first and second value ([0071], “Whenever the co-simulator prepares to schedule a callback, it reads the signal_driven_by_co_simulator signal from the simulator via VPI … writes back the incremented value to the simulator via VPI. Since the simulator implements the update of signal_updated_by_simulator as described above, the simulator will call the co-simulator (with VPI value change reason).” [0041], “In the ingress phase the co-simulator reads the values of one or more signals from the simulator.” [0042], “In some embodiments, the co-simulator reads a given simulator signal by … requesting the simulator to provide a trigger when the signal value changes. This feature is referred to as “callback on value change” in VPI terminology.” [0059], “In the next value change callback trigger 90, the co-simulator … obtains the execution results and performs the egress phase.” [0040], “… a mechanism that ensures synchronization and data integrity between the various signals and databases in the simulator and co-simulators.” Examiner note: the simulator 24 triggers co-simulators 28 and obtains output values via callback or read operations. Under BRI, the callback mechanism corresponds to a read command issued by the primary simulator to retrieve the first and second sample values from the co-simulators, and he data exchange occurs under synchronized timing control).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chalfin to incorporate the teachings of Mizrachi, and apply a primary simulator issues read commands to retrieve data from co-simulators via callback or trigger mechanisms in order to enable the primary device to request and receive sample values from each simulation modules under synchronized timing control. The combination of teaching would provide benefit of improving simulation coordination and data retrieval accuracy by allowing the primary controller that manages timing to perform data read commands within a unified synchronization framework.
However, Chalfin and Mizrachi fail to teach, but Mavis teaches the primary clock signal and receive first and second sampled values based on the first edge of the primary clock signal (see Mavis, Figs.7-8 and Col. 8-10; for example, Col.8, lines 46-66, “The temporal sampling stage 108 contains multiple sampling systems to sample data at input IN at different sampling times … Each sampling system 112, 114, and 116 contains an edge triggered D flip-flop … the D flip-flops 112-116 are triggered on the falling edges of corresponding clock signals CLKA, CLKB, and CLKC …”. Col.9, “The vote timing system 118 contains three level sensitive latches 128, 130, and 132 that are clocked by a fourth clock signal CLKD.” Col.10, lines 6-8 “In the temporally redundant latch, data is released to the combinatorial logic 104 on the rising edge of sampling clock CLKD …”).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chalfin and Mizrachi to incorporate the teachings of Mavis, and apply edge-triggered clocking and temporally distinct sampling operations in order to improve timing accuracy and better emulate circuit-level timing behavior within a simulation environment. In this case, In this case, Chalfin teaches the primary clock arbitrator issues clock to synchronize multiple simulation modules. Mizrachi teaches the mechanism of actively issuing read commands to collect data from the modules. Mavis teaches multiple sampling and sample release systems are clocked by different clock signals, generate and receive sample values at different and distinct sampling times using edge-triggered elements. The combination of teaching would predictably provide benefit of enabling coordinated simulation while incorporating edge-based data generation and temporally distinct clock operations based on read commend, thereby improving timing flexibility and allowing sample value to be generated at different clock edges and collected in a coordinated manner.
Claim 5, Chalfin further teaches The method of claim 1, further comprising:
completing, by the first client device, a first plurality of phases within the first simulation environment; and
completing, by the second client device, a second plurality of phases within the second simulation environment, (Col.4, lines 31-41, “… Clock arbitrator 105 is shown issuing a clock credit 200 to each of simulation modules 110A through 110 … Once all the simulation modules have consumed their respective clock credits, then clock arbitrator can issue additional clock credit as necessary.” Col.4, lines 59-61, “A given simulation module includes a DUT 305. DUT 305 includes code that, when executed, simulates the operation of the physical circuit corresponding to DUT 305.” Col.5, lines 8-11, “It is the responsibility of test bench 310 to provide input and clock signals to DUT 305 and to accept outputs produced by DUT 305.” Examiner note: each simulation module executes it DUT within a separate simulation environment when a clock credit is issued by the clock arbitrator. Each module performs repeated execution cycles as credits are granted and consumed is interpreted as phases completed by the respective client device within their simulation environments).
However, Chalfin fails to teach the first plurality of phases and the second plurality of phases each comprise a first phase, and wherein the first phase is completed asynchronously within the first plurality of phases and the second plurality of phases.
Mizrachi teaches the first plurality of phases and the second plurality of phases each comprise a first phase, and wherein the first phase is completed asynchronously within the first plurality of phases and the second plurality of phases ([0053], “Each co-simulator carries out its ingress, execution and egress phases.” [0060], “Using this technique, execution in one co-simulator does not block other co-simulators. As a result, the co-simulators can carry out their respective sub-tasks concurrently …” Examiner note: each co-simulator performs multiple operational phases (i.e., ingress, execution, and egress) that proceed independently of one another. Because the execution of one co-simulator does not block other co-simulators, each co-simulator initial phase (i.e., first phase) can complete at a different time from other co-simulators is interpreted as completed asynchronously within the pluralities of phases of the first and second co-simulators).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chalfin to incorporate the teachings of Mizrachi, and apply asynchronous co-simulation phase execution in order to enable each client device to complete its own simulation phases without blocking other. In this case, Chalfin teaches simulation architecture includes multiple simulation modules and a clock arbitrator that issues primary clock credits to coordinate the time of the modules and test benches provide input and receive output signal values (i.e., samples values) from each module. Mizrachi teaches each co-simulation performs multiple operational phases that execution in each co-simulator does not block the execution of another, thereby allowing asynchronous progression of phase completion across co-simulators. The combination of teaching would provide benefit of improving simulation throughput and computational scalability by allowing the modules to complete their first phase and continue asynchronously within their respective phase sequence, while the clock credit control maintains synchronized overall timing among simulation environments.
Claim 6, Chalfin fails to teach, but Mizrachi teaches The method of claim 5, further comprising obtaining, by the primary client device (fig.3, simulator 24), the first simulation data (updated values of signal from one of co-simulator) from the first client device (fig.3, one of co-simulator 28) and the second simulation data (updated values of signal from another one of co-simulator) from the second client device (fig.3, another one of co-simulator 28) based on the completion of the first phase by both of the first client device and the second client device ([0026], “System 20 comprises a simulator 24 and one or more co-simulators 28.” [0041], “Simulator 24 typically simulates a Verilog design … In the ingress phase the co-simulator reads the values of one or more signals from the simulator. In the execution phase the co-simulator applies the appropriate processing to the signals. In the egress phase the co-simulator provides the processing results, e.g., updated values of the signals, back to the simulator.” [0042], “In some embodiments, the co-simulator reads a given simulator signal by registering, or subscribing, to the signal and requesting the simulator to provide a trigger when the signal value changes.” [0053], “In case of non-blocking assignments, the egress phase has to be performed only after all the co-simulators that were triggered in the same time slot have completed their respective ingress phases.” [0071], “Whenever the co-simulator prepares to schedule a callback, it reads the signal_driven_by_co_simulator signal from the simulator via VPI, … the simulator will call the co-simulator (with VPI value change reason).” Examiner note: the simulator 24 operates as a primary controller coordinating co-simulators 28. Each co-simulator performs a sequence of phases including ingress, execution, and egress. During the ingress phase, the co-simulator read one or more signal values from the simulator, and during the egress phase, the co-simulator provides updated signal values back to the simulator as the first and second simulation data. The egress phase executes only after all co-simulators that were triggered in the same time slot have completed their ingress (first) phases. Therefore, the simulator 24 (i.e., primary client device) obtains the first and second simulation data from the first and second co-simulators 28 based on completion of their first phase (ingress phase).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chalfin to incorporate the teachings of Mizrachi, and apply phase synchronized co-simulation structure in order to enable primary simulator to obtain simulation data from multiple co-simulators after completion of their ingress phase. In this case, Chalfin teaches simulation architecture includes multiple simulation modules and a clock arbitrator that issues primary clock credits to coordinate the time of the modules and test benches provide input and receive output signal values (i.e., samples values) from each module. Mizrachi teaches each co-simulator reads signals from the primary simulator, and during the egress phase, updated signal values are provided back to the primary simulator, the egress phase is executed only after all co-simulators have completed their respective ingress phase, ensuring data return occurs in a coordinated manner across modules. The combination of teaching would provide benefit of improving timing coordination and data exchange accuracy between distributed simulation environments by allowing the primary simulator that controls overall timing to also receive synchronized simulation results only after all participating co-simulators have completed their first phase, thereby enhancing simulation integrity, and overall computational efficiency.
The elements of claims 8-13 and 15-19 are substantially the same as those of claims 1-6.
Therefore, the elements of claims 8-13 and 15-19 are rejected due to the same reasons as outlined above for claims 1-6. Further, the additional limitation of claim 15, “A non-transitory computer readable medium comprising stored instructions, which when executed by one or more processors, cause the one or more processors to:” (see Chalfin, Col.7, lines 38-62).
Claim(s) 7, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chalfin and
Mizrachi and Mavis as applied to claims 1, 8 and 15 above, and further in view of Tokuda US20120072629A1 and Gaillard US6636907B1.
Claim 7, Chalfin and Mizrachi fail to teach, but Mavis teaches the first edge of the primary clock signal is subsequent to the first edge of the first local clock signal and the first edge of the second local clock signal (Fig.8 illustrates the first edge of the release CLKD 148 (i.e., T1 of primary clock signal) is subsequent to the first falling edge of the sample CLKA 142 (e.g., first local clock signal) and the first falling edge of the sample CLKB 144 (e.g., second local clock signal).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chalfin and Mizrachi to incorporate the teachings of Mavis, and apply edge-triggered clocking and temporally distinct sampling operations in order to improve timing accuracy and better emulate circuit-level timing behavior within a simulation environment. The combination of teaching would predictably provide benefit of enabling coordinated simulation while incorporating edge-based data transmission and temporally distinct clock operations, thereby improving timing flexibility and allowing data to be generated at different clock edges and collected in a coordinated manner.
However, Chalfin and Mizrachi and Mavis fail to teach, but Tokuda teaches the primary client device is further configured to receive a ([0020] The communication system includes a master device 100 and slave devices 200.sub.n…” [0022], “In the communication system shown in FIG. 1, the three slave devices 200.sub.0 through 200.sub.2 are connected to the one master device 100.” [0023], “In the communication system, in a case where the states of the sensors included in the slave devices 200.sub.0 through 200.sub.2 change or another case, the slave devices 200.sub.0 through 200.sub.2 issue (generate) request signals as transmission start signals, and transmit the request signals.” [0031], “The master device 100 has the communication arbitration circuit 108. The request signals (req0, req1, req2) from the slave devices 200.sub.0 through 200.sub.2 are input to the communication arbitration circuit 108. The communication arbitration circuit 108 receives the request signals (req0, req1, req2) from the slave devices 200.sub.0 through 200.sub.2, and carries out arbitration of communication between the master device 100 and the slave devices 200.sub.0 through 200.sub.2.” [0034], “For example, ordinarily, the request communication line has an "H" (High) level. In a case where the slave device has data to be read by the master device 100, the slave device changes its own request communication line from the "H" level to an "L" (Low) level. The communication arbitration circuit 108 of the master device 100 recognizes that the transmission request is generated in the slave device in response to the corresponding request communication line being thus changed from the "H" level to the "L" level.” [0060], “The master device 100 receives the request signal from the slave device 200.sub.0, ...” [0058], “The request signals from the slave devices 200.sub.0, 200.sub.1 and 200.sub.2 are indicated as "REQ_0", "REQ_1" and "REQ_2", respectively. The transmission request by the CPU 102 for transmitting to the slave device 200.sub.0 is indicated as "CPU transmission command (to SLAVE0)".” [0049], “It is noted that the master device 100 cannot predict the request signal which will be generated subsequently in the slave devices 200 0 through 200 2. This is because, for example, it is not possible to predict when information to be transmitted will be generated in the slave devices 200 0 through 200 2. Since it is thus not possible to predict a generation of the request signal in the slave devices 200 0 through 200 2, dummy LLI information “ADRS_RXDMY_LLI” is prepared …” Examiner note: the reference teaches a communication system includes a master device (i.e., primary client device), and multiple slave devices (i.e., first and second client devices) that each generates and transmits a request signal (REQ0-REQ2) independently. The master device receives all request signals and arbitrates communication via circuit. Because the master device cannot predict when the request signals will be generated, the request signals are asynchronous relative to the master’s clock timing is interpreted as primary client device receives request from multiple client devices asynchronously with the primary clock signal).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chalfin and Mizrachi and Mavis to incorporate the teachings of Tokuda, and apply an asynchronous multiple request communication architecture in order to enable a primary client device to receive multiple request signals from different client devices operating with independent timing relative to a primary clock signal. In this case, Chalfin teaches simulation architecture includes multiple simulation modules and a clock arbitrator that issues primary clock credits to coordinate the time of the modules and test benches provide input and receive output signal values (i.e., samples values) from each module. Mizrachi teaches each co-simulator reads signals from the primary simulator, and during the egress phase, updated signal values are provided back to the primary simulator, the egress phase is executed only after all co-simulators have completed their respective ingress phase, ensuring data return occurs in a coordinated manner across modules. Mavis teaches multiple sampling systems are clocked by different clock signals and generate data at different and distinct sampling times using edge-triggered elements. Tokuda teaches a communication architecture including a master device and multiple slave devices, and each slave device independently issues request signals to the master device, and the master receives and arbitrates these asynchronous requests using a communication arbitrator. The combination of teaching would provide benefit of improving timing coordination and communication flexibility between multiple devices by allowing a primary client device that manages clock timing to handle asynchronous multi-source request events, thereby enhancing overall responsiveness and scalability of distributed module interactions within a unified clocked environment.
However, Chalfin and Mizrachi and Mavis and Tokuda fail to teach receive request and send request, and a data transfer associated with the receive request and the send request is executed at the first edge of the primary clock signal.
Gaillard teaches receive request and send request, and a data transfer associated with the receive request and the send request is executed at the first edge of the primary clock signal (Col.5, Table 1, “Data can be received by the peripheral on the rising edge of nSTROBE … The bus controller bridge will read the DI bus on the rising edge of nSTROBE when nREADY is active low … A peripheral sets this signal low when it is ready to send or receive data. The state of nREADY is received by the bus controller bridge on the rising edge of nSTROBE … All transactions complete on the rising edge of nSTROBE when nREADY is active (low).” Examiner note: the reference teaches a peripheral device asserts an nREADY signal when it is ready to send or receive data, and the bus controller bridge detects the request and performs read/write transactions on the rising edge (i.e., first edge) of the transfer clock nSTROBE).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chalfin and Mizrachi and Mavis and Tokuda to incorporate the teachings of Gaillard, and apply an edge-triggered data transfer protocol in order to enable a primary client device to execute data transfers associated with receive and send requests at the rising edge of a primary clock signal. In this case, Chalfin teaches simulation architecture includes multiple simulation modules and a clock arbitrator that issues primary clock credits to coordinate the time of the modules and test benches provide input and receive output signal values (i.e., samples values) from each module. Mizrachi teaches each co-simulator reads signals from the primary simulator, and during the egress phase, updated signal values are provided back to the primary simulator, the egress phase is executed only after all co-simulators have completed their respective ingress phase, ensuring data return occurs in a coordinated manner across modules. Mavis teaches multiple sampling systems are clocked by different clock signals and generate data at different and distinct sampling times using edge-triggered elements. Tokuda teaches a communication architecture including a master device and multiple slave devices, and each slave device independently issues request signals to the master device, and the master receives and arbitrates these asynchronous requests using a communication arbitrator. Gaillard teaches that a bus controller receives send and receive requests (nREADY) from peripheral devices and executes associated read/write transactions on the rising edge of the transfer clock (nSTROBE). The combination of teaching would provide benefit of improving timing communication and timing accuracy between distributed modules by allowing the primary client device that handle asynchronous multi-source request events to perform precisely timed data transfer.
The elements of claims 14 and 20 are substantially the same as those of claim 7. Therefore, the elements of claims 14 and 20 are rejected due to the same reasons as outlined above for claim 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen US20030018462A1, discloses simulating a source system having a plurality of source clocks to trigger a plurality of logic elements comprises modeling the plurality of source clocks with a global clock, modeling a first one of the plurality of source clocks with a first clock mask and a first clock state, evaluating at least one of the plurality of logic elements when the global clock generates a global clock pulse and updating the at least one of the plurality of logic elements based on the first clock mask and the first clock state.
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/YI . HAO/
Examiner, Art Unit 2187
/EMERSON C PUENTE/Supervisory Patent Examiner, Art Unit 2187
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