DETAILED ACTION
This Office action is in response to the election filed 28 August 2025. Claims 1-20 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species A - claims 1-14, in the reply filed on 13 October 2025 is acknowledged.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-11, and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0085056 A1 to Zhang et al. (hereinafter “Zhang”).
Regarding independent claim 1, Zhang (Figs. 1A-1B, 20) discloses a three-dimensional (3D) memory device, comprising: a plurality of memory planes 102 (¶ 0026; Fig. 1A), each memory plane comprising a plurality of memory blocks 109 (Fig. 1B; ¶ 0028), each memory block comprising:
a memory stack 146 (¶ 0056; Fig. 20) comprising interleaved conductive layers 144 (¶ 0053; Fig. 20) and first dielectric layers 141 (¶ 0053); and
a plurality of channel structures 150 (labelled in Fig. 12; ¶ 0057) each extending through the memory stack (Fig. 20); and
a separation block 104 (Fig. 20; ¶ 0027) extending laterally to separate each two adjacent memory planes (Fig. 20; Fig. 1A), each separation block comprising:
a dielectric stack comprising interleaved second dielectric layers 142 (Fig. 20; ¶ 0032) and the first dielectric layers 141, wherein the first dielectric layers 141 extend across the memory blocks and the separation block 104, and the second dielectric layers 142 separate the conductive layers 144 of two adjacent memory blocks (Fig. 20; Fig. 1B).
Regarding claim 2, Zhang (Figs. 1A-1B, 20) discloses the 3D memory device of claim 1, wherein each separation block 104 further comprises: a plurality of dummy channel structures 168/169 (¶ 0082) extending in the dielectric stack (Fig. 20).
Regarding claim 3, Zhang (Figs. 1A-1B, 20) discloses the 3D memory device of claim 2, wherein the dummy channel structures 168/169 extend through partial of the dielectric stack (Fig. 20).
Regarding claim 5, Zhang (Figs. 1A-1B, 20) discloses the 3D memory device of claim 1, wherein each memory block further comprises at least one slit structure 160/161 (¶ 0082) extending through the memory stack (Fig. 19; see also Fig. 7 for cross-sectional view).
Regarding claim 6, Zhang (Figs. 1A-1B, 20) discloses the 3D memory device of claim 5, wherein at least one channel structure 150 is disposed between the slit structure 160/161 and the separation block 104 (Fig. 19).
Regarding independent claim 7, Zhang (Figs. 1A-1B, 19, 20) discloses a three-dimensional (3D) memory device, comprising: a plurality of memory blocks 109 (Fig. 1B; ¶ 0028), each memory block comprising:
a memory stack 146 (¶ 0056; Fig. 20) comprising interleaved conductive layers 144 (¶ 0053; Fig. 20) and first dielectric layers 141 (¶ 0053);
a plurality of channel structures 150 (labelled in Fig. 12; ¶ 0057) each extending through the memory stack (Fig. 20); and
a slit structure 160/161 (Fig. 19; ¶ 0082) extending through the memory stack; and
a separation block 104 (Fig. 20; ¶ 0027) extending laterally to separate two adjacent memory blocks (Fig. 20; Fig. 1B), the separation block comprising:
a dielectric stack comprising interleaved second dielectric layers 142 (Fig. 20; ¶ 0032) and the first dielectric layers 141.
Regarding claim 8, Zhang (Figs. 1A-1B, 19, 20) discloses the 3D memory device of claim 7, wherein the slit structure 160/161 is disposed only in the plurality of memory blocks (¶ 0041; Fig. 19).
Regarding claim 9, Zhang (Figs. 1A-1B, 19, 20) discloses the 3D memory device of claim 7, wherein the first dielectric layers 141 extend across the memory blocks and the separation block 104, and the second dielectric layers 142 separate the conductive layers 144 in two adjacent memory blocks (Fig. 20).
Regarding claim 10, Zhang (Figs. 1A-1B, 19, 20) discloses the 3D memory device of claim 7, wherein the separation block 104 further comprises: a plurality of dummy channel structures 168/169 (¶ 0082) each extending in the dielectric stack (Fig. 20).
Regarding claim 11, Zhang (Figs. 1A-1B, 19, 20) discloses the 3D memory device of claim 7, wherein the dummy channel structures 168/169 extend through partial of the dielectric stack (Fig. 20).
Regarding claim 13, Zhang (Figs. 1A-1B, 19, 20) discloses the 3D memory device of claim 10, wherein at least one channel structure 150 is disposed between the slit structure 160/161 and the separation block 104 (Fig. 19).
Regarding claim 14, Zhang (Figs. 1A-1B, 19, 20) discloses the 3D memory device of claim 10, wherein at least one channel structure 150 is disposed between the slit structure 160/161 and the dummy channel structures 168/169 (Fig. 19).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang.
Regarding claim 4, Zhang discloses the 3D memory device of claim 1, however fails to expressly disclose wherein a diameter of the channel structures is larger than a diameter of the dummy channel structures.
Regarding claim 12, Zhang discloses the 3D memory device of claim 10, however fails to expressly disclose wherein a diameter of the channel structures is larger than a diameter of the dummy channel structures.
Regarding claims 4 and 12, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Here, the following limitations are considered mere dimensional limitations: “a diameter of the channel structures is larger than a diameter of the dummy channel structures” as recited in claims 4 and 12. The instant disclosure is silent as to a particular unobvious purpose, unexpected result, or criticality of the above dimensional limitations, and thus are found to be prima facie obvious.
Furthermore, in Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04(IV)(A).
Here, the difference between prior art Zhang and the claimed invention is a recitation of relative dimensions (“a diameter of the channel structures is larger than a diameter of the dummy channel structures”). A device having the claimed relative dimensions would not perform differently than the device of Zhang. Thus, the claimed invention is not patentably distinct from the device as disclosed by Zhang, and it would have been a routine expedient within the skill of one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Zhang to include the above relative dimensions. See also, MPEP 2144.04(IV)(A).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
CANDICE Y. CHAN
Examiner
Art Unit 2813
2 January 2026
/KHAJA AHMAD/Primary Examiner, Art Unit 2813