DETAILED ACTION
The current Office Action is in response to the papers submitted 06/02/2026. Claims 1, 3 – 15, and 17 - 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 - 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "each processing element" in line 3. It is unclear if each processing element is referring to the upstream processing elements, the downstream processing elements, the interconnected processing elements, or additional processing elements of the interconnected processing elements. There is insufficient antecedent basis for this limitation in the claim. For examination each processing element will be treated as refer to both the upstream processing elements and downstream processing elements.
Claim 1 recites the limitation "the same processing element" in line 12. There is no previous mention of a same processing element in the claim. This makes it unclear if the same processing element is one of the interconnected processing elements, upstream processing elements, or downstream processing elements. There is insufficient antecedent basis for this limitation in the claim. For examination the same processing element will be treated as one of the interconnected processing elements.
Claim 1 recites the limitation "the same compute cycle" in line 12. There is no previous mention of a same compute cycle or a compute cycle in the claim. There is insufficient antecedent basis for this limitation in the claim. For examination the limitations will be treated as performing the update of both the forward and back partial results in during a same compute cycle.
Claim 1 recites the limitation of a “compute cycle” in line 12. A compute cycle is only disclosed twice in the specification in paragraphs 0030 and 0038. Both locations define what happens after a compute cycle but fail to properly define what the actual compute cycle is. This makes the scope of the compute cycle indefinite.
Claim 1 appears to add the term “circuits” to replace the deleted term “elements”. However, the addition of circuits fails to show proper amendment markings showing that the term circuits is added to the claim. This makes it unclear if the term circuits was actually meant to be added to the claim or not. For examination the term circuits will be treated as being added into the claim with an underline. No additional amendment markings is needed at this time for the addition of the term circuits.
Claim 14 appears to add multiple lines of amendments to the end of line 6 without amendment markings indicating the additional lines are added to the claim. This makes it unclear if the added limitations are meant to be added to the claim or not. For examination the amendment will be treated as the additional lines are added correctly and no additional markings are needed.
All remaining claims are rejected for being dependent on a rejected base claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3 – 8, and 12 - 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fraser et al. (Pub. No.: US 2019/0080223) referred to as Fraser.
Regarding claim 1, Fraser teaches an array of interconnected processing elements [204-0 – 204-(N-1), Fig 2], including upstream processing elements [204-0 to 204-2, Fig 2] and downstream processing elements [204-(N) to 204-(N-1)], each processing element [204-0 – 204-(N-1), Fig 2] including:
a forward-propagation input port to receive a forward partial result [206-(i-1), Fig 3; Paragraph 0079; The data being received in the buffer shows a port to receive the data];
a forward-propagation processor to update the forward partial result [306-0 through 310-(P-1), Fig 3; Paragraph 0079; The input data 206-(i-1) is processed and updated by one or more of 306-0 through 306-(P-1)];
a forward-propagation output port to transmit the updated forward partial result [206-i, Fig 3; Paragraph 0078; The data path out shows the use of a port];
a back-propagation input port to receive a back-propagation partial result [208-(i+1), Fig 3; Paragraph 0080; Receiving the data shows the use of a port];
a back-propagation processor to update the back-propagation partial result [310-0 through 310-(P-1), Fig 3; Paragraph 0080; The input data 208-(i+1) is processed and updated by one or more of 310-0 through 310-(P-1)]; and
a back-propagation output port to transmit the updated back-propagation partial result [208-I, Fig 3; Paragraph 0080; The death path out shows the use of a port];
wherein the forward-propagation processor [306-0 through 310-(P-1), Fig ] and the back-propagation processor [310-0 through 310-(P-1), Fig 3] concurrently update the forward partial result and the back-propagation partial result, respectively [Paragraphs 0042, 0048, 0050, 0079 – 0080, 0082, and 0084; The multiple processors perform operations concurrently. There is no specific limitation in the claim indicating what concurrently is related to other then the updating of results], within the same processing element during the same compute cycle [Paragraphs 0042, 0048 – 0050, 0079 – 0080, and 0082 – 0084; Each processing element processes forward and back partial results in parallel showing the processing is performed in the same compute cycle a given processing elements computes data].
Regarding claim 3, Fraser teaches wherein the forward-propagation output port transmits the updated forward partial [206-i, Fig 3; Paragraph 0078; The data path out shows the use of a port] result to a downstream one of the processing elements [204-(N) – 204-(N-1), Fig 2; Paragraphs 0079 – 0080; Data from one processing element is passed along to another processing element including upstream and downstream processing elements].
Regarding claim 4, Fraser teaches the back-propagation input port receives the back-propagation partial result from the downstream one of the processing elements [Fig 2; 208-(i+1), Fig 3; Paragraphs 0079 - 0080; Back-propagation data is output from downstream processing elements from another downstream processing element].
Regarding claim 5, Fraser teaches each of the forward-propagation input port [206-(i-1), Fig 3; Paragraph 0079] and the back-propagation input port [208-(i+1), Fig 3; Paragraph 0080] are unidirectional [Figs 2 – 3; Paragraphs 0079 – 0080; Input data passes through the data processing elements in only one direction based on which input the input data enters the processing elements].
Regarding claim 6, Fraser teaches first storage [308, Fig 3] to store the forward partial result [206-I, Fig 3] and second storage [314, Fig 3] to store the back-propagation partial result [208-I, Fig 3].
Regarding claim 7, Fraser teaches memory to store a weight [402, Fig 4; 514, Fig 5] for each of the processing elements [204-0 – 204-(N-1), Fig 2], the forward-propagation processor [306-0 through 310-(P-1), Fig 3; 306-p, Fig 4] to update the forward partial result [206-(i-1), Figs 3 - 4]as a function of the weight [306-0 through Paragraph 0081; The processor updates the input data based on the weight stored in memory 402].
Regarding claim 8, Fraser teaches the back-propagation processor [310-0 through 310-(P-1), Fig 3] in each of the processing elements [204-0 – 204-(N-1), Fig 2] is coupled to the memory to update the weight [316 and 318, Fig 3, Figs 4 – 5; Paragraphs 0081 – 0085; Each back-propagation processor is coupled to a memory containing weights and updates the weights as needed].
Regarding claim 12, Fraser teaches an activation-function processing circuit [406, Fig 4] coupled to a last of the downstream processing elements [204-(N) – 204-(N-1), Fig 2] to apply an activation function to a last of the forward partial results [Figs 2 – 4; Paragraph 0074; Item 406 in 204-(N-1) applies an activation to the last forward partial result 206-(N-2) to get 206-(N-1)].
Regarding claim 13, Fraser teaches a second array of interconnected processing elements [202 and 210], including a second processing circuit coupled to the activation-function processing circuit [Figs 2 - 3; 406, Fig 4; Item 210 is coupled to 406 in 204-(N-1) to receive 206-(N-1)] to receive the last of the forward partial results with the applied activation function [206-(N-1), Fig 2].
Regarding claim 14, Fraser teaches an array of interconnected processing tiles [204-0 – 204-(N-1), Fig 2], including upstream processing tiles [204-0 – 204-2, Fig 2] and downstream processing tiles [204-(N) – 204-(N-1), Fig 2], each processing tile [204-0 – 204-(N-1), Fig 2] including:
a forward-propagation input port to receive input data from an upstream processing tile [206-(i-1), Fig 3; Paragraph 0079; The data being received in the buffer shows a port to receive the data];
processing circuits [204-0 – 204-(N-1), Fig 2] to collectively compute a partial result as a function of the input data from the upstream processing tile [306-0 through 310-(P-1), Fig 3; Paragraph 0079; The input data 206-(i-1) is processed and updated by one or more of 306-0 through 306-(P-1)], wherein the processing circuits [204-0 – 204-(N-1), Fig 2] concurrently update forward partial results and the back-propagation partial results [Paragraphs 0042, 0048, 0050, 0079 – 0080, 0082, and 0084; The multiple processors perform operations concurrently. There is no specific limitation in the claim indicating what concurrently is related to other then the updating of results] within the same processing circuit during the same compute cycle [Paragraphs 0042, 0048 – 0050, 0079 – 0080, and 0082 – 0084; Each processing element processes forward and back partial results in parallel showing the processing is performed in the same compute cycle a given processing elements computes data];
a forward-propagation output port to convey the partial result to a downstream processing tile [206-i, Fig 3; Paragraph 0078; The data path out shows the use of a port]; and
a back-propagation output port [208-i, Fig 3; Paragraph 0080; The data path out shows the use of a port]; and
forward-propagation input switches, each of the forward-propagation input switches [Paragraph 0059; The switch blocks are switches that allow the connections of segments between elements in figures 2 – 5] coupled to the forward-propagation input port [206-(i-1), Fig 3; Paragraph 0079; The data being received in the buffer shows a port to receive the data] of a first of the processing tiles [204-1, Fig 2], the forward-propagation output port [206-i, Fig 3; Paragraph 0078; The data path out shows the use of a port] of a second of the processing tiles [204-0, Fig 2] upstream from the first of the processing tiles [204-1, Fig 2], and the back-propagation output port [208-i, Fig 3; Paragraph 0080; The data path out shows the use of a port] of a third of the processing tiles [204-2, Fig 2] downstream from the first of the processing tiles [204-1, Fig 2];
wherein each of the forward-propagation input switches [Paragraph 0059; The switch blocks are switches that allow the connections of segments between elements in figures 2 – 5] to concurrently route:
the partial result from the forward-propagation output port [206-i, Fig 3; Paragraph 0078; The data path out shows the use of a port] of the second of the processing tiles [204-0, Fig 2] to the forward-propagation input port [206-(i-1), Fig 3; Paragraph 0079; The data being received in the buffer shows a port to receive the data] of the first of the processing tiles [204-1, Fig 2]; and
signals from the back-propagation output port [208-I, Fig 3; Paragraph 0080; The death path out shows the use of a port] of the third of the processing tiles [204-2, Fig 2] downstream from the first of the processing tiles [204-1, Fig 2] past the forward-propagation input port [206-(i-1), Fig 3; Paragraph 0079; The data being received in the buffer shows a port to receive the data] of the first of the processing tiles [Figs 2 – 3; Paragraphs 0042, 0048, 0050, 0059, 0079 – 0080, 0082, and 0084; The processing of signals and sending of the signals between tiles uses the switches and the operations are performed concurrently. There is no specific limitation in the claim indicating what concurrently is related to other then the updating of results. Sending a signal to a particular tile and port upstream or downstream sends the signal past all other tiles and related ports]
Regarding claim 15, Fraser teaches each of the forward-propagation input switches [Paragraph 0059; The switch blocks are switches that allow the connections of segments between elements in figures 2 – 5] to alternatively route the partial result [206-i, Fig 3] from the forward-propagation output port [206-i, Fig 3] of the second of the processing tiles [204-0, Fig 2] or a back-propagation partial result [208-i, Fig 3] from the back-propagation output port [208-i, Fig 3; Paragraph 0080; The death path out shows the use of a port] of the third of the processing tiles [204-2, Fig 2] to the forward-propagation input port [206-(i-1), Fig 3] of the first of the processing tiles [Paragraph 0059; 204-1, Fig 2; The signals 206-0 and 208-2 are routed to 204-1 using switch blocks].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 9 – 11 and 17 - 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fraser et al. (Pub. No.: US 2019/0080223) referred to as Fraser as applied to claims 7 and 14 above, and further in view of Burger et al. (Pub. No.: US 2016/0379115) referred to as Burger.
Regarding claim 9, Fraser teaches the array of interconnected processing elements [204-0 – 204-(N-1), Fig 2] and multiple memories to store weight information [402, Fig 4; 514, Fig 5].
However, Fraser may not specifically disclose the limitation of an array of interconnected processing elements occupies a first die in a stack of dies and memory occupies a second die in the stack of dies.
Burger discloses an array of interconnected processing elements occupies a first die [4504, Fig 45C] in a stack of dies [Fig 45C] and memory occupies a second die [4506b, Fig 45C] in the stack of dies [Fig 45C].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Burger in Fraser, because it increases circuit density which reduces the overall footprint of the circuit, improves performance with shorter interconnects, reduces power consumption due to the shorter interconnects, and improves yields per wafer due to the smaller dies.
Regarding claim 10, Fraser teaches the memory [402, Fig 4; 514, Fig 5].
Burger discloses the memory is coupled to the first die by conductive vias [Fig 45C; Paragraph 0275; The dies in the stacks of dies are connected with conductive vias].
Regarding claim 11, Fraser teaches the array of interconnected processing elements [204-0 – 204-(N-1), Fig 2] and multiple memories to store weight information [402, Fig 4; 514, Fig 5].
Burger discloses the conductive vias are through-silicon vias [Fig 45C; Paragraph 0275; The conductive vias are through-silicon vias].
Regarding claim 17, Fraser teaches the array of interconnected processing tiles [204-0 – 204-(N-1), Fig 2] and multiple memories [304, 308, 312, and 314, Fig 3].
However, Fraser may not specifically disclose the limitations of the array of interconnected processing tiles is instantiated on a base layer of a stack of integrated-circuit dies, the stack including memory dies.
Burger discloses an array of interconnected processing tiles is instantiated on a base layer [4504, 45C] of a stack of integrated-circuit dies [Fig 45C], the stack including memory dies [4506b, Fig 45C].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Burger in Fraser, because it increases circuit density which reduces the overall footprint of the circuit, improves performance with shorter interconnects, reduces power consumption due to the shorter interconnects, and improves yields per wafer due to the smaller dies.
Regarding claim 18, Fraser teaches the memory includes vaults to store partial results [304, 308, 312, and 314, Fig 3; The storage units in the buffers are considered vaults that store the partial result from another processing tile or the partial result sent to another processing tile].
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fraser et al. (Pub. No.: US 2019/0080223) referred to as Fraser as applied to claim 14 above, and further in view of Janedula et al. (Pub. No.: US 2019/0042923) referred to as Janedula.
Regarding claim 19, Fraser teaches the array of interconnected processing tiles [204-0 – 204-(N-1), Fig 2] and forward-propagation input switches [Paragraph 0059; The switch blocks are switches that allow the connections of segments between elements in figures 2 – 5] support nested loops [Figs 3 – 5; The figures shows multiple feedback loops], including a multiply-accumulate loop [404, Fig 4; 506, Fig 5; Items 404 and 506 are part of the feedback loops in figure 3].
However, Fraser may not specifically disclose the limitation of a kernel-stride loop.
Janedula discloses a kernel-stride loop [Paragraphs 0152, 0154, 0176, and 0226; Kernel stride processing is disclosed].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Janedula in Fraser, because the Winograd transform which uses the kernel stride process which reduces the number of multiplication operations needed [Paragraph 0142 and 0176].
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fraser et al. (Pub. No.: US 2019/0080223) referred to as Fraser Janedula et al. (Pub. No.: US 2019/0042923) referred to as Janedula as applied to claim 19 above, and further in view of Zhou (Pub. No.: US 2017/0372447) referred to as Zhou.
Regarding claim 20, Fraser teaches the array of interconnected processing tiles [204-0 – 204-(N-1), Fig 2] and forward-propagation input switches [Paragraph 0059; The switch blocks are switches that allow the connections of segments between elements in figures 2 – 5] along with nested loops [Figs 3 – 5; The figures shows multiple feedback loops].
Janedula discloses a kernel-stride loop [Paragraphs 0152, 0154, 0176, and 0226; Kernel stride processing is disclosed].
However, Fraser in view of Janedula may not specifically disclose the limitation of a second kernel-stride loop orthogonal.
Zhou discloses a second kernel-stride loop orthogonal [Paragraph 0068; The kernels are orthogonal concepts that are processed].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Zhou in Fraser in view of Janedula, because it improves GEMV operations by eliminating the need to translate back and forth between different representations of the same matrix [Paragraphs 0034, 0047, 0060].
Response to Arguments
Applicant's arguments filed 06/02/2026 have been fully considered but they are not persuasive.
The applicant argues the amendments overcome the previous 112(f) claim interpretation and 112(a) and 112(b) rejections. The amendments overcome the previous 112(f) claim interpretation and 112(a) and 112(b) rejections. However, the amendments introduce new 112(b) issues as indicated in the rejections above.
The applicant argues on pages 7 – 8 with regard to claim 1 that Fraser fails to concurrently updating forward and back partial results within the same processing element during the same compute cycle. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The applicant appears to be equating a compute cycle to a single batch. The specification fails to define a compute cycle as a batch. A computer cycle is a unit of time in the art used to designate a period of time when a compute function is performed. The applicant admits on page 8 that Fraser teaches the processors in the processing elements run in parallel. The data each processor is processing for might be different but the act of processing is performed in parallel. This shows the processing, which includes the updating of the partial results, is performed in a single compute cycle. There is no requirement in the amendments that the updating is for the same batch of data as argued.
The applicant argues on page 9 with regard to claim 14 that Fraser fails to teach updating partial results in the same processing circuit during the same compute cycle similarly as argued against claim 1 above. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The examiner has responded to the arguments against claim 1 above showing how Fraser teaches the argued limitation. The same reasoning is applied to claim 12.
The applicant argues on page 9 with regard to claim 14 that Fraser fails to teach the switches based on figure 13 that shows four modes of operation. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The claims require the switches to be coupled to certain elements in the claims. A device being coupled to an item does not mean the device is directly connected to the item as the applicant apparently is arguing. Fraser teaches in paragraph 0059 that switch blocks are used to facilitate the connection between segments in processing. The claim limitation of routing signals past a port does not mean the ports are physically lined up in a certain orientation and the signal is routed physically around a port. Routing a signal to a certain port routes the signal past all other ports since the signal is not routed to the other ports. The switch block routes the signals to the segments and therefor past any port segment the signal is not routed to. If the applicant wants to switches to be in specific locations, not just coupled to certain devices, and routing signals in specific directions the limitations need to be added to the claims and show proper support in the specification.
The applicant argues on pages 10 – 11 that all remaining dependent claims are allowable for being dependent on a base claim that was argued allowable above. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The examiner has responded to all arguments above regarding the base claims showing how the prior art teaches the current limitations in the base claims. The rejections of the remaining dependent claims are maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/ Primary Examiner, Art Unit 2138
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