DETAILED ACTION
The current Office Action is in response to the papers submitted 01/20/2026. Claims 1, 3 – 15, and 17 - 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
an activation-function processing element…to apply in claim 12
a second processing element…to receive in claim 13
processing elements to collectively compute in claim 14
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12 – 15 and 17 - 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As described below, the disclosure does not provide adequate structure to perform the claimed functions of applying an activation function, receiving the last of the forward partial results, and collectively compute a partial result as a function. The specification does not demonstrate that applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Claims 12 – 15 and 17 - 20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim limitations “an activation-function processing element…to apply an activation function to a last of the forward partial results”, “a second processing element…to receive the last of the forward partial results with the applied activation function”, and “processing elements to collectively compute a partial result as a function of the input data from the upstream processing tile” recited in claims 12 – 14 invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed functions. In particular, the specification states the claimed functions with no mention of any specific mention of how they are performed. There is no disclosure of any particular structure, either explicitly or inherently, to perform the applying of an activation function, what activation function applied, how the last of the forward partial result are received, or how the processing elements collectively compute a partial result based on function of the input data. The use of the terms “apply”, “receive”, and “compute” are not adequate structure for performing the claimed functions because they does not describe a particular structure for performing the functions. As would be recognized by those of ordinary skill in the art, the terms “apply”, “receive”, and “compute” refers common processes performed in computer systems and can be performed in any number of ways in hardware, software or a combination of the two. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which filter structure or structures perform(s) the claimed functions.
Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
All remaining claims are rejected for being dependent on a rejected base claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3 – 8, and 12 - 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fraser et al. (Pub. No.: US 2019/0080223) referred to as Fraser.
Regarding claim 1, Fraser teaches an array of interconnected processing elements [204-0 – 204-(N-1), Fig 2], including upstream processing elements [204-0 – 204-2, Fig 2] and downstream processing elements [204-(N) – 204-(N-1), Fig 2], each processing element [204-0 – 204-(N-1), Fig 2] including:
a forward-propagation input port to receive a forward partial result [206-(i-1), Fig 3; Paragraph 0079; The data being received in the buffer shows a port to receive the data];
a forward-propagation processor to update the forward partial result [306-0 through 310-(P-1), Fig 3; Paragraph 0079; The input data 206-(i-1) is processed and updated by one or more of 306-0 through 306-(P-1)];
a forward-propagation output port to transmit the updated forward partial result [206-i, Fig 3; Paragraph 0078; The data path out shows the use of a port];
a back-propagation input port to receive a back-propagation partial result [208-(i+1), Fig 3; Paragraph 0080; Receiving the data shows the use of a port];
a back-propagation processor to update the back-propagation partial result [310-0 through 310-(P-1), Fig 3; Paragraph 0080; The input data 208-(i+1) is processed and updated by one or more of 310-0 through 310-(P-1)]; and
a back-propagation output port to transmit the updated back-propagation partial result [208-I, Fig 3; Paragraph 0080; The death path out shows the use of a port];
wherein the forward-propagation processor [306-0 through 310-(P-1), Fig ] and the back-propagation processor [310-0 through 310-(P-1), Fig 3] concurrently update the forward partial result and the back-propagation partial result, respectively [Paragraphs 0042, 0048, 0050, 0079 – 0080, 0082, and 0084; The multiple processors perform operations concurrently. There is no specific limitation in the claim indicating what concurrently is related to other then the updating of results].
Regarding claim 3, Fraser teaches wherein the forward-propagation output port transmits the updated forward partial [206-i, Fig 3; Paragraph 0078; The data path out shows the use of a port] result to a downstream one of the processing elements [204-(N) – 204-(N-1), Fig 2; Paragraphs 0079 – 0080; Data from one processing element is passed along to another processing element including upstream and downstream processing elements].
Regarding claim 4, Fraser teaches the back-propagation input port receives the back-propagation partial result from the downstream one of the processing elements [Fig 2; 208-(i+1), Fig 3; Paragraphs 0079 - 0080; back-propagation data is output from downstream processing elements up to upstream processing elements].
Regarding claim 5, Fraser teaches each of the forward-propagation input port [206-(i-1), Fig 3; Paragraph 0079] and the back-propagation input port [208-(i+1), Fig 3; Paragraph 0080] are unidirectional [Figs 2 – 3; Paragraphs 0079 – 0080; Input data passes through the data processing elements in only one direction based on which input the input data enters the processing elements].
Regarding claim 6, Fraser teaches first storage [308, Fig 3] to store the forward partial result [206-I, Fig 3] and second storage [314, Fig 3] to store the back-propagation partial result [208-I, Fig 3].
Regarding claim 7, Fraser teaches memory to store a weight [402, Fig 4; 514, Fig 5] for each of the processing elements [204-0 – 204-(N-1), Fig 2], the forward-propagation processor [306-0 through 310-(P-1), Fig 3; 306-p, Fig 4] to update the forward partial result [206-(i-1), Figs 3 - 4]as a function of the weight [306-0 through Paragraph 0081; The processor updates the input data based on the weight stored in memory 402].
Regarding claim 8, Fraser teaches the back-propagation processor [310-0 through 310-(P-1), Fig 3] in each of the processing elements [204-0 – 204-(N-1), Fig 2] is coupled to the memory to update the weight [316 and 318, Fig 3, Figs 4 – 5; Paragraphs 0081 – 0085; Each back-propagation processor is coupled to a memory containing weights and updates the weights as needed].
Regarding claim 12, Fraser teaches an activation-function processing element [406, Fig 4] coupled to a last of the downstream processing elements [204-(N) – 204-(N-1), Fig 2] to apply an activation function to a last of the forward partial results [Figs 2 – 4; Paragraph 0074; Item 406 in 204-(N-1) applies an activation to the last forward partial result 206-(N-2) to get 206-(N-1)].
Regarding claim 13, Fraser teaches a second array of interconnected processing elements [202 and 210], including a second processing element coupled to the activation-function processing element [Figs 2 - 3; 406, Fig 4; Item 210 is coupled to 406 in 204-(N-1) to receive 206-(N-1)] to receive the last of the forward partial results with the applied activation function [206-(N-1), Fig 2].
Regarding claim 14, Fraser teaches an array of interconnected processing tiles [204-0 – 204-(N-1), Fig 2], including upstream processing tiles [204-0 – 204-2, Fig 2] and downstream processing tiles [204-(N) – 204-(N-1), Fig 2], each processing tile [204-0 – 204-(N-1), Fig 2] including:
a forward-propagation input port to receive input data from an upstream processing tile [206-(i-1), Fig 3; Paragraph 0079; The data being received in the buffer shows a port to receive the data];
processing elements to collectively compute a partial result as a function of the input data from the upstream processing tile [306-0 through 310-(P-1), Fig 3; Paragraph 0079; The input data 206-(i-1) is processed and updated by one or more of 306-0 through 306-(P-1)];
a forward-propagation output port to convey the partial result to a downstream processing tile [206-i, Fig 3; Paragraph 0078; The data path out shows the use of a port]; and
a back-propagation output port [208-i, Fig 3; Paragraph 0080; The data path out shows the use of a port]; and
forward-propagation input switches, each of the forward-propagation input switches [Paragraph 0059; The switch blocks are switches that allow the connections of segments between elements in figures 2 – 5] coupled to the forward-propagation input port [206-(i-1), Fig 3; Paragraph 0079; The data being received in the buffer shows a port to receive the data] of a first of the processing tiles [204-1, Fig 2], the forward-propagation output port [206-i, Fig 3; Paragraph 0078; The data path out shows the use of a port] of a second of the processing tiles [204-0, Fig 2] upstream from the first of the processing tiles [204-1, Fig 2], and the back-propagation output port [208-i, Fig 3; Paragraph 0080; The data path out shows the use of a port] of a third of the processing tiles [204-2, Fig 2] downstream from the first of the processing tiles [204-1, Fig 2];
wherein each of the forward-propagation input switches [Paragraph 0059; The switch blocks are switches that allow the connections of segments between elements in figures 2 – 5] to concurrently route:
the partial result from the forward-propagation output port [206-i, Fig 3; Paragraph 0078; The data path out shows the use of a port] of the second of the processing tiles [204-0, Fig 2] to the forward-propagation input port [206-(i-1), Fig 3; Paragraph 0079; The data being received in the buffer shows a port to receive the data] of the first of the processing tiles [204-1, Fig 2]; and
signals from the back-propagation output port [208-I, Fig 3; Paragraph 0080; The death path out shows the use of a port] of the third of the processing tiles [204-2, Fig 2] downstream from the first of the processing tiles [204-1, Fig 2] past the forward-propagation input port [206-(i-1), Fig 3; Paragraph 0079; The data being received in the buffer shows a port to receive the data] of the first of the processing tiles [Figs 2 – 3; Paragraphs 0042, 0048, 0050, 0059, 0079 – 0080, 0082, and 0084; The processing of signals and sending of the signals between tiles uses the switches and the operations are performed concurrently. There is no specific limitation in the claim indicating what concurrently is related to other then the updating of results. Sending a signal to a particular tile and port upstream or downstream sends the signal past all other tiles and related ports]
Regarding claim 15, Fraser teaches each of the forward-propagation input switches [Paragraph 0059; The switch blocks are switches that allow the connections of segments between elements in figures 2 – 5] to alternatively route the partial result [206-i, Fig 3] from the forward-propagation output port [206-i, Fig 3] of the second of the processing tiles [204-0, Fig 2] or a back-propagation partial result [208-i, Fig 3] from the back-propagation output port [208-i, Fig 3; Paragraph 0080; The death path out shows the use of a port] of the third of the processing tiles [204-2, Fig 2] to the forward-propagation input port [206-(i-1), Fig 3] of the first of the processing tiles [Paragraph 0059; 204-1, Fig 2; The signals 206-0 and 208-2 are routed to 204-1 using switch blocks].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 9 – 11 and 17 - 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fraser et al. (Pub. No.: US 2019/0080223) referred to as Fraser as applied to claims 7 and 14 above, and further in view of Burger et al. (Pub. No.: US 2016/0379115) referred to as Burger.
Regarding claim 9, Fraser teaches the array of interconnected processing elements [204-0 – 204-(N-1), Fig 2] and multiple memories to store weight information [402, Fig 4; 514, Fig 5].
However, Fraser may not specifically disclose the limitation of an array of interconnected processing elements occupies a first die in a stack of dies and memory occupies a second die in the stack of dies.
Burger discloses an array of interconnected processing elements occupies a first die [4504, Fig 45C] in a stack of dies [Fig 45C] and memory occupies a second die [4506b, Fig 45C] in the stack of dies [Fig 45C].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Burger in Fraser, because it increases circuit density which reduces the overall footprint of the circuit, improves performance with shorter interconnects, reduces power consumption due to the shorter interconnects, and improves yields per wafer due to the smaller dies.
Regarding claim 10, Fraser teaches the memory [402, Fig 4; 514, Fig 5].
Burger discloses the memory is coupled to the first die by conductive vias [Fig 45C; Paragraph 0275; The dies in the stacks of dies are connected with conductive vias].
Regarding claim 11, Fraser teaches the array of interconnected processing elements [204-0 – 204-(N-1), Fig 2] and multiple memories to store weight information [402, Fig 4; 514, Fig 5].
Burger discloses the conductive vias are through-silicon vias [Fig 45C; Paragraph 0275; The conductive vias are through-silicon vias].
Regarding claim 17, Fraser teaches the array of interconnected processing tiles [204-0 – 204-(N-1), Fig 2] and multiple memories [304, 308, 312, and 314, Fig 3].
However, Fraser may not specifically disclose the limitations of the array of interconnected processing tiles is instantiated on a base layer of a stack of integrated-circuit dies, the stack including memory dies.
Burger discloses an array of interconnected processing tiles is instantiated on a base layer [4504, 45C] of a stack of integrated-circuit dies [Fig 45C], the stack including memory dies [4506b, Fig 45C].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Burger in Fraser, because it increases circuit density which reduces the overall footprint of the circuit, improves performance with shorter interconnects, reduces power consumption due to the shorter interconnects, and improves yields per wafer due to the smaller dies.
Regarding claim 18, Fraser teaches the memory includes vaults to store partial results [304, 308, 312, and 314, Fig 3; The storage units in the buffers are considered vaults that store the partial result from another processing tile or the partial result sent to another processing tile].
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fraser et al. (Pub. No.: US 2019/0080223) referred to as Fraser as applied to claim 14 above, and further in view of Janedula et al. (Pub. No.: US 2019/0042923) referred to as Janedula.
Regarding claim 19, Fraser teaches the array of interconnected processing tiles [204-0 – 204-(N-1), Fig 2] and forward-propagation input switches [Paragraph 0059; The switch blocks are switches that allow the connections of segments between elements in figures 2 – 5] support nested loops [Figs 3 – 5; The figures shows multiple feedback loops], including a multiply-accumulate loop [404, Fig 4; 506, Fig 5; Items 404 and 506 are part of the feedback loops in figure 3].
However, Fraser may not specifically disclose the limitation of a kernel-stride loop.
Janedula discloses a kernel-stride loop [Paragraphs 0152, 0154, 0176, and 0226; Kernel stride processing is disclosed].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Janedula in Fraser, because the Winograd transform which uses the kernel stride process which reduces the number of multiplication operations needed [Paragraph 0142 and 0176].
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fraser et al. (Pub. No.: US 2019/0080223) referred to as Fraser Janedula et al. (Pub. No.: US 2019/0042923) referred to as Janedula as applied to claim 19 above, and further in view of Zhou (Pub. No.: US 2017/0372447) referred to as Zhou.
Regarding claim 20, Fraser teaches the array of interconnected processing tiles [204-0 – 204-(N-1), Fig 2] and forward-propagation input switches [Paragraph 0059; The switch blocks are switches that allow the connections of segments between elements in figures 2 – 5] along with nested loops [Figs 3 – 5; The figures shows multiple feedback loops].
Janedula discloses a kernel-stride loop [Paragraphs 0152, 0154, 0176, and 0226; Kernel stride processing is disclosed].
However, Fraser in view of Janedula may not specifically disclose the limitation of a second kernel-stride loop orthogonal.
Zhou discloses a second kernel-stride loop orthogonal [Paragraph 0068; The kernels are orthogonal concepts that are processed].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Zhou in Fraser in view of Janedula, because it improves GEMV operations by eliminating the need to translate back and forth between different representations of the same matrix [Paragraphs 0034, 0047, 0060].
Response to Arguments
Applicant's arguments filed 01/20/2026 have been fully considered but they are not persuasive.
The applicant argues on pages 7 – 10 that the claims avoid the 112(f) interpretation and thus overcome the related 112(a) and 112(b) rejections since a processing element is not a mere placeholder but recites definite hardware structure recognized in the art such as 310 in figure 3. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
310 is not a specific structure but rather identifies a generic processing element with no specific hardware structure. The applicant argues in part the processing element denotes devices such as MAC units, registers, multipliers, adders, and associated logic to perform computations in interconnected arrays. This shows the structure is not properly defined. It is unclear if the processing element a single unit comprising MAC units, registers, multipliers, adders, and associated logic together or if the processing unit is only one of MAC units, registers, multipliers, adders, and associated logic of the processing element is something else. There is no clear description in the specification defining the specific structure of the processing element let alone the specific algorithm the processing elements perform.
There is also a lack of specific algorithm disclosed that defines the functions of the processing elements as required under 112(f). The related 112(a) and 112(b) rejections are based on the 112(f) interpretation. The specific structure and algorithms performed by the processing elements are not properly defined. The 112(f) and related 112(a) and 112(b) are maintained.
The applicant argues on pages 10 – 12 regarding claims 1 – 8 and 12 – 13 that Fraser fails to teach the concurrently updating the forward partial result and the back-propagation partial result, respectively since Fraser discloses pipelined processing across different batch which include a delay of processing the same batch while processing multiple batches simultaneously. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
There is no limitation in the claims that the concurrent processing is for the same batch as argued. The claims do not disclose a link between the forward partial result and the back-propagation partial result requiring the forward partial result and the back-propagation partial result to be in the same batch as argued. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., concurrently update partial results for the same batch/input) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The applicant argues on pages 12 – 13 with regard to claims 14 – 16 that Fraser fails to teach a switch and the switch routing a signal around a tile’s forward input. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
Paragraphs 0055 – 0059 disclose the use of switches as in a switch matrix or switch blocks that are used to make the connections between interconnected devices in the system. The limitation of routing signals past a port is treated as not sending the signal to the port. Paragraphs 0042, 0048, 0050, 0079 – 0080, 0082, and 0084 disclose how processing between the tiles is performed concurrently in parallel. Figure 2 shows the output 208-2 of the third time 204-2 downstream from the first tile 204-1 is routed past the input of the first time 206-0. Past does not require a physical location distance association rather the limitation denotes not going to a certain location. The switches from paragraphs 0055 – 0059 control the signal routing in figure 2. This shows the signal 208-2 passes the input that 206-0 goes to since 208-1 goes into another different input in 204-1.
The applicant argues on pages 13 – 14 the remaining dependent claims are allowable since the additional prior art introduced fails to overcome the arguments above regarding Fraser in the base claims. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The examiner has responded to the arguments above and updated the rejections above to show how Fraser teaches the argued limitations. The rejections of the dependent claims are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/ Primary Examiner, Art Unit 2138