Technology areas: Computing & Software • Semiconductors, Circuits & Optics
31 pending office actions • 11 art units • 29 examiners • 0 of 31 (0%) have an AI response strategy ready • 99 patents granted in the last 365 days
Rambus Inc. is managing 32 pending office actions in the Computing & Software technology area. These actions are distributed among 29 distinct examiners, indicating a high level of individual examiner involvement. The portfolio spans 11 distinct art units, showing a variety of technical focuses within the computing sector.
Jerome Larry Leboeuf is the busiest examiner, overseeing 2 pending office actions. With 32 actions across 11 art units, the company's prosecution efforts are spread across several specialized USPTO groups. This distribution suggests that while the 29 distinct examiners provide a range of individual perspectives, the 11 art units provide some level of technical clustering. Practitioners should note that the 32 pending office actions are handled by a group of examiners that is nearly as large as the action count itself, requiring a tailored approach for almost every filing within the 11 art units.
Based on the USPTO statutory response window for each pending office action. 6 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 6 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 + other | 1 (3%) |
| §103 only | 10 (32%) |
| §102 only | 3 (10%) |
| §112 only | 3 (10%) |
| Double-patenting only | 3 (10%) |
| Multi-statute (no §101) | 11 (35%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| LEBOEUF, JEROME LARRY | 2 | 85.4% | +6.4% |
| BELKHAYAT, ZAKARIA MOHAMMED | 2 | 88.5% | +19.4% |
| VERBRUGGE, KEVIN | 1 | 88.9% | -2.6% |
| CRAWFORD, JASON | 1 | 85.0% | +9.1% |
| NAM, HYUN | 1 | 86.6% | -0.5% |
| TRUVAN, LEYNNA THANH | 1 | 76.5% | +20.1% |
| HARRINGTON, CHERI L. | 1 | 69.6% | +27.0% |
| CHEN, XIAOCHUN L | 1 | 91.9% | -0.5% |
| KING, DANIEL JOHN | 1 | 98.5% | +2.1% |
| RUIZ, ARACELIS | 1 | 87.1% | +12.6% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 7 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18809247 | MEMORY COMPONENT WITH ADJUSTABLE CORE-TO-INTERFACE DATA RATE RATIO | BELKHAYAT, ZAKARIA MOHAMMED | 30d overdue |
| 18701574 | STACKED MEMORY DEVICE WITH INTERFACE DIE | BELKHAYAT, ZAKARIA MOHAMMED | 33d |
| 19231757 | MEMORY SYSTEM WITH MULTIPLE OPEN ROWS PER BANK | VERBRUGGE, KEVIN | — |
| 19098780 | Failover Methods and Systems in Three-Dimensional Memory Device | CRAWFORD, JASON | — |
| 19106370 | CONFIGURABLE MEMORY DEVICE | NAM, HYUN | — |
| 19018436 | MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT | RUIZ, ARACELIS | — |
| 19017028 | CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE | LEBOEUF, JEROME LARRY | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18810360 | APPARATUS AND METHOD FOR SELECTIVE REFRESH SUPPRESSION | LEBOEUF, JEROME LARRY | 22d |
| 18919066 | MEMORY MODULE WITH REDUCED READ/WRITE TURNAROUND OVERHEAD | ROCHE, JOHN B | 28d |
| 18219842 | MEMORY COMPRESSION | SAIN, GAUTAM | 42d |
| 18994560 | MULTI-CHANNEL MEMORY STACK WITH SHARED DIE | CHEN, XIAOCHUN L | — |
| 18994396 | Memory with Interleaved Preset | KING, DANIEL JOHN | — |
| 19011869 | HIERARCHICAL BANK GROUP TIMING | NGUYEN, VAN THU T | — |
| 19009148 | BOOSTED WRITEBACK VOLTAGE | HIDALGO, FERNANDO N | — |
| 18990536 | DATA-BUFFER CONTROLLER/CONTROL-SIGNAL REDRIVER | STORMES, JOSEPH FIDELIS | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 5 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18809247 | MEMORY COMPONENT WITH ADJUSTABLE CORE-TO-INTERFACE DATA RATE RATIO | BELKHAYAT, ZAKARIA MOHAMMED | 30d overdue |
| 18701574 | STACKED MEMORY DEVICE WITH INTERFACE DIE | BELKHAYAT, ZAKARIA MOHAMMED | 33d |
| 18994817 | LATENCY-CONTROLLED INTEGRITY AND DATA ENCRYPTION (IDE) | TRUVAN, LEYNNA THANH | — |
| 19021723 | DYNAMICALLY CHANGING DATA ACCESS BANDWIDTH BY SELECTIVELY ENABLING AND DISABLING DATA LINKS | HARRINGTON, CHERI L. | — |
| 19018436 | MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT | RUIZ, ARACELIS | — |
| Art Unit | Apps |
|---|---|
| 2139 | 4 |
| 2827 | 3 |
| 2824 | 2 |
| 2184 | 2 |
| 2435 | 1 |
| 2112 | 1 |
| 2181 | 1 |
| 2138 | 1 |
| 2137 | 1 |
| 2132 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 19231757 | MEMORY SYSTEM WITH MULTIPLE OPEN ROWS PER BANK | VERBRUGGE, KEVIN | 2139 | §102Other | Non-Final OA | — | Pending | Jun 09, 2025 |
| 19098780 | Failover Methods and Systems in Three-Dimensional Memory Device | CRAWFORD, JASON | — | DP | Non-Final OA | — | Pending | Apr 02, 2025 |
| 19106370 | CONFIGURABLE MEMORY DEVICE | NAM, HYUN | — | §103 | Non-Final OA | — | Pending | Feb 25, 2025 |
| 18994817 | LATENCY-CONTROLLED INTEGRITY AND DATA ENCRYPTION (IDE) | TRUVAN, LEYNNA THANH | 2435 | §103 | Non-Final OA | — | Pending | Jan 15, 2025 |
| 19021723 | DYNAMICALLY CHANGING DATA ACCESS BANDWIDTH BY SELECTIVELY ENABLING AND DISABLING DATA LINKS | HARRINGTON, CHERI L. | — | §103Other | Non-Final OA | — | Pending | Jan 15, 2025 |
| 18994560 | MULTI-CHANNEL MEMORY STACK WITH SHARED DIE | CHEN, XIAOCHUN L | — | §102§103 | Non-Final OA | — | Pending | Jan 14, 2025 |
| 18994396 | Memory with Interleaved Preset | KING, DANIEL JOHN | — | §102§103§112 | Non-Final OA | — | Pending | Jan 14, 2025 |
| 19018436 | MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT | RUIZ, ARACELIS | 2139 | §103 | Final Rejection | — | Pending | Jan 13, 2025 |
| 19017028 | CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE | LEBOEUF, JEROME LARRY | 2827 | §102Other | Non-Final OA | — | Pending | Jan 10, 2025 |
| 19017200 | CONTROLLER THAT RECEIVES A CYCLIC REDUNDANCY CHECK (CRC) CODE FOR BOTH READ AND WRITE DATA TRANSMITTED VIA BIDIRECTIONAL DATA LINK | CHASE, SHELLY A | 2112 | §112 | Non-Final OA | — | Pending | Jan 10, 2025 |
| 19011869 | HIERARCHICAL BANK GROUP TIMING | NGUYEN, VAN THU T | — | §102§103Other | Non-Final OA | — | Pending | Jan 07, 2025 |
| 19009148 | BOOSTED WRITEBACK VOLTAGE | HIDALGO, FERNANDO N | — | §103§112Other | Non-Final OA | — | Pending | Jan 03, 2025 |
| 18990536 | DATA-BUFFER CONTROLLER/CONTROL-SIGNAL REDRIVER | STORMES, JOSEPH FIDELIS | — | §102§103§112 | Non-Final OA | — | Pending | Dec 20, 2024 |
| 18980698 | LOAD REDUCED MEMORY MODULE | NGUYEN, VIET Q | — | §102 | Non-Final OA | — | Pending | Dec 13, 2024 |
| 18869501 | 3D MEMORY DEVICE WITH LOCAL COLUMN DECODING | RADKE, JAY W | — | §112 | Non-Final OA | — | Pending | Nov 26, 2024 |
| 18959973 | ASYMMETRIC-CHANNEL MEMORY SYSTEM | FRANKLIN, RICHARD B | 2181 | §103Other | Final Rejection | 21d | Pending | Nov 26, 2024 |
| 18868859 | CHANNEL-SHARED DATA STROBE | HOANG, HUAN | 2827 | §103§112 | Non-Final OA | — | Pending | Nov 25, 2024 |
| 18956309 | MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION | HO, HOAI V | — | DP | Non-Final OA | — | Pending | Nov 22, 2024 |
| 18943434 | MULTI-PORT MEMORY DEVICE WITH BUILT-IN CONFIGURABLE LOGIC BLOCK TO PERFORM A PARALLEL COMPUTING OPERATION | REECE, CHRISTOPHER LANE | 2824 | §103 | Final Rejection | — | Pending | Nov 11, 2024 |
| 18919066 | MEMORY MODULE WITH REDUCED READ/WRITE TURNAROUND OVERHEAD | ROCHE, JOHN B | 2184 | §102§103Other | Final Rejection | 28d | Pending | Oct 17, 2024 |
| 18919179 | FOLDED MEMORY MODULES | HASSAN, AURANGZEB | 2184 | §103 | Final Rejection | — | Pending | Oct 17, 2024 |
| 18895130 | DATA BUFFER FOR MEMORY DEVICES WITH MEMORY ADDRESS REMAPPING | PHAM, LY D | 2827 | §102§103 | Final Rejection | — | Pending | Sep 24, 2024 |
| 18810360 | APPARATUS AND METHOD FOR SELECTIVE REFRESH SUPPRESSION | LEBOEUF, JEROME LARRY | 2824 | §102§103 | Final Rejection | 22d | Pending | Aug 20, 2024 |
| 18809247 | MEMORY COMPONENT WITH ADJUSTABLE CORE-TO-INTERFACE DATA RATE RATIO | BELKHAYAT, ZAKARIA MOHAMMED | 2139 | §103 | Non-Final OA | 30d overdue | Pending | Aug 19, 2024 |
| 18807548 | Clock Generation for Timing Communications with Ranks of Memory Devices | BROWN, MICHAEL J | — | DP | Non-Final OA | — | Pending | Aug 16, 2024 |
| 18795900 | USING DYNAMIC BURSTS TO SUPPORT FREQUENCY-AGILE MEMORY INTERFACES | SURYAWANSHI, SURESH | — | §101§102§112 | Non-Final OA | — | Pending | Aug 06, 2024 |
| 18786296 | CONTEXT-BASED COMPRESSION IN A MEMORY SYSTEM | KROFCHECK, MICHAEL C | 2138 | §103§112 | Non-Final OA | — | Pending | Jul 26, 2024 |
| 18701574 | STACKED MEMORY DEVICE WITH INTERFACE DIE | BELKHAYAT, ZAKARIA MOHAMMED | 2139 | §103 | Final Rejection | 33d | Pending | Apr 15, 2024 |
| 18598142 | MEMORY DEVICE FLUSH BUFFER OPERATIONS | THAMMAVONG, PRASITH | 2137 | §103 | Non-Final OA | — | Pending | Mar 07, 2024 |
| 18687116 | COMMON DATA STROBE AMONG MULTIPLE MEMORY DEVICES | DARE, RYAN A | 2132 | §112 | Non-Final OA | — | Pending | Feb 27, 2024 |
| 18219842 | MEMORY COMPRESSION | SAIN, GAUTAM | 2135 | §103§112 | Final Rejection | 42d | Pending | Jul 10, 2023 |
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