CTFR 17/846,129 CTFR 83782 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Arguments Applicant’s arguments with respect to claim(s) 1-7 have been considered but are moot on grounds of new rejection and interpretation of prior art. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim(s) 1, 2 and 4-7 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang (US 2022/0359461 A1) . In regards to claim 1, Chang (Figs. 4A, 5A-5C, 6A-9D and associated text and items) discloses microelectronic assembly (Figs. 5A-5C) , comprising: a first integrated circuit (IC) die (items 42, 506) coupled to at least two second IC die(s) (items 401(a)-401(c), 502, 511, 512, 513, or 514, items 504, 521, 522, 523 or 524) by interconnects (items 419, 413, 427, 425, 516, 526, plurality of dielectric layer, metal lines, vias, paragraph 52, shown but not labeled on item 506, Fig. B, paragraph 56, 535 plus pads shown but not labeled) on a first surface (top surface) of the first IC die (items 42, 506) and second surfaces (side surfaces) of the second IC die(s) (items 401(a)-401(c), 502, 511, 512, 513, or 514, items 504, 521, 522, 523 or 524) such that the first surface (top surface) is in contact with the second surfaces (side surface) , wherein: the second surfaces (side surface) are coplanar, the interconnects (items 419, 413, 427, 425, 516, 526, plurality of dielectric layer, metal lines, vias, paragraph 52, shown but not labeled on item 506, Fig. B, paragraph 56, 535 plus pads shown but not labeled) comprise dielectric-dielectric bonds and metal-metal bonds (paragraphs 46, 48, 52, 56) , the metal-metal bonds include first bond-pads (item 425) in the first IC die (items 42, 506) and second bond-pads (items 419, 516, 526) in the second IC die(s) (items 401(a)-401(c), 502, 511, 512, 513, or 514, items 504, 521, 522, 523 or 524) , the first IC die (items 42, 506) comprises a substrate (items 421, paragraph 47) attached to a metallization stack (items 413 plus 414 plus 419, 424 plus 425, paragraphs 47, 52) along a planar interface that is orthogonal to the first surface (top surface) , the metallization stack (items 413 plus 414 plus 419 or 424 plus 425, paragraphs 47, 52) comprises a plurality of layers of conductive traces (item 414 or 424 plus 425, paragraph 52) in a dielectric material (item 413, 423, paragraph 47, 52) , and the first bond-pads (items 419, 516, 526) comprise portions of the conductive traces (items 414, 419, 424 plus 425) exposed on the first surface (top surface) . In regards to claim 2, Chang (Figs. 4A, 5A-5C, 6A-9D and associated text) discloses wherein: the second IC dies (items 502, 504) are spaced apart, and the microelectronic assembly further comprises another dielectric material (item 530,) between adjacent ones of the second IC (items 502, 504) . In regards to claim 4, Chang (Figs. 4A, 5A-5C, 6A-9D and associated text and items) discloses wherein the first IC die (items 506) extends into the second IC dies (items 502, 504) beyond respective saw-streets of the second IC dies (items 502, 504) . In regards to claim 5, Chang (Figs. 4A, 5A-5C, 6A-9D and associated text) discloses wherein: the substrate (items 421, paragraph 47, 52) is a first substrate (items 421, paragraph 47, 52) , and the metallization stack (items 424 plus 425) is a first metallization stack ((items 424 plus 425) , the second IC dies (items 502, 504) comprise respective second metallization stacks (items 414, 419) and second substrates (item 411, paragraph 52) , the second substrates (item 411, paragraph 52) are attached to the second metallization stacks (items 414, 419) along respective planar interfaces that are parallel to the second surface (side surface) , and the second metallization stacks (items 414, 419) comprise conductive traces (items 414, 419) coupled by conductive vias (items 414) to the second bond-pads (items 419, 516, 526) . In regards to claim 6, Chang (Figs. 4A, 5A-5C, 6A-9D and associated text) discloses wherein a conductive pathway (items 414, 419, 515, 516, paragraph 52) comprises conductive traces (items 414, 419, 515, 516, paragraph 52) in respective second metallization stacks (items 414, 419, 515, 516, paragraph 52) of the second IC die (items 502, 504) , conductive traces in the first metallization stack (items 424, 425) of the first IC die (items 506) , and the interconnects (items 424, 425, 516, 526, plurality of dielectric layer, metal lines, vias, paragraph 52, shown but not labeled on item 506, Fig. B, paragraph 56, 535 plus pads shown but not labeled) . In regards to claim 7, Chang (Figs. 4A, 5A-5C, 6A-9D and associated text) discloses wherein the conductive pathway (items 424, 425) further comprises active circuitry (items 424, 425, paragraph 47) in the first IC die (items 506) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0359461 A1) . In regards to claim 3, Chang (Figs. 4A, 5A-5C, 6A-9D and associated text) does not specifically disclose wherein the second IC dies are approximately 26 millimeters wide and 33 millimeters long, and the first IC dies extend at least 5 millimeters into the second IC dies as measured from respective edges of the second IC dies. It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include second IC dies that are approximately 26 millimeters wide and 33 millimeters long, and first IC dies that extend at least 5 millimeters into the second IC dies as measured from respective edges of the second IC dies for the purpose of package/assembly size and spacing, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chang (US 2022/0352092 A1, Figs. 1-5, 10 and associated text) and Chang et al. (US 2022/0320047 A1, Figs. 1-7A and associated text) discloses the same limitations as Chang used in the above rejection and could have both been used as primary references . Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TELLY D. GREEN Examiner Art Unit 2898 /TELLY D GREEN/Primary Examiner, Art Unit 2898 June 6, 2026 Application/Control Number: 17/846,129 Page 2 Art Unit: 2898 Application/Control Number: 17/846,129 Page 3 Art Unit: 2898 Application/Control Number: 17/846,129 Page 4 Art Unit: 2898 Application/Control Number: 17/846,129 Page 5 Art Unit: 2898 Application/Control Number: 17/846,129 Page 6 Art Unit: 2898 Application/Control Number: 17/846,129 Page 7 Art Unit: 2898
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