DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 3, Sub-species BB, Figs. 5C, 5D, claims 1-7 and 11-16 in the reply filed on December 23, 2025 is acknowledged. Claims 8-10 and 17-20 have been withdrawn by the Applicant. However, after further inspection, the Examiner notes that claims 11-16 do not belong to the elected Sub-species BB due to the fact that Sub-species BB does not include the package substrate of Sub-species CC. Sub-species BB also only includes two second IC and five first IC die. Sub-species CC includes four second IC die and fourteen first IC die in a different arrangement, as seen from a topographical view, and includes a package substrate. Therefore claims 11-16 are withdrawn along with claims 8-10 and 17-20. Action on the merits is as follows:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0359461 A1) as evidence by or in view of Burton (US 2020/0219843 A1 now US 11,569,198 B2).
In regards to claim 1, Chang (Figs. 4A, 5A-5C, 6A-9D and associated text) discloses microelectronic assembly (Figs. 5A-5C), comprising: a first integrated circuit (IC) die (items 401(a)-401(c), 502, 511, 512, 513, or 514, items 504, 521, 522, 523 or 524) coupled to at least one second IC die(s) (items 42, 506) by interconnects (items 419, 413, 427, 425, 516, 526, plurality of dielectric layer, metal lines, vias, paragraph 52, shown but not labeled on item 506, Fig. B, paragraph 56, 535 plus pads shown but not labeled) on a first surface (side surface) of the first IC die (items 401(a)-401(c), 502, 511, 512, 513, or 514, items 504, 521, 522, 523 or 524) and second surfaces (top surface) of the second IC die(s) (items 42, 506) such that the first surface (side surface) is in contact with the second surfaces (top surface), wherein: the second surfaces (top surface) are coplanar, the interconnects (items 419, 413, 427, 425, 516, 526, plurality of dielectric layer, metal lines, vias, paragraph 52, shown but not labeled on item 506, Fig. B, paragraph 56, 535 plus pads shown but not labeled) comprise dielectric-dielectric bonds and metal-metal bonds (paragraphs 46, 48, 52, 56), the metal-metal bonds include first bond-pads (items 419, 516, 526) in the first IC die (items 502, 511, 512, 513, or 514, items 504, 521, 522, 523 or 524) and second bond-pads (item 425, shown but not labeled in Fig. 5B) in the second IC die(s) (items 42, 506), the first IC die (items 401(a)-401(c), 502, 511, 512, 513, or 514, items 504, 521, 522, 523 or 524) comprises a substrate (items 411, paragraph 52) attached to a metallization stack (items 413 plus 414 plus 419, paragraph 52) along a planar interface that is orthogonal to the first surface (side surface), the metallization stack comprises a plurality of layers of conductive traces (item 414, paragraph 52) in a dielectric material (item 413, paragraph 52), and the first bond-pads (items 419, 516, 526) comprise portions of the conductive traces (items 414, 419) exposed on the first surface (side surface).
Chang does not specifically disclose at least two second IC dies.
As evidenced by Burton (Figs. 2A, 2B, 3 and associated text), die can be monolithic (item 254) or disaggregated (items 204A, 204B, 304A, 304B).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Burton for the purpose of device density and design choice, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art (Nerwin v. Erlichman, 168 USPQ 177, 179).
In regards to claim 2, Chang (Figs. 4A, 5A-5C, 6A-9D and associated text) as modified by Burton (Figs. 2A, 2B, 3 and associated text) discloses wherein: the second IC dies (items 42, 506, Chang, items 204A, 204B, 304A, 304B, Burton) are spaced apart, and the microelectronic assembly further comprises another dielectric material (encapsulation/mold shown, but not labeled, paragraph 40) between adjacent ones of the second IC dies (items 42, 506, Chang, items 204A, 204B, 304A, 304B, Burton).
In regards to claim 3, Chang (Figs. 4A, 5A-5C, 6A-9D and associated text) as modified by Burton (Figs. 2A, 2B, 3 and associated text) does not specifically disclose wherein the second IC dies are approximately 26 millimeters wide and 33 millimeters long, and the first IC dies extend at least 5 millimeters into the second IC dies as measured from respective edges of the second IC dies.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include second IC dies that are approximately 26 millimeters wide and 33 millimeters long, and first IC dies that extend at least 5 millimeters into the second IC dies as measured from respective edges of the second IC dies for the purpose of package/assembly size and spacing, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 4, Chang (Figs. 4A, 5A-5C, 6A-9D and associated text) as modified by Burton (Figs. 2A, 2B, 3 and associated text) discloses wherein the first IC die (items 401(a)-401(c), 502, 511, 512, 513, or 514, items 504, 521, 522, 523 or 524) extends into the second IC dies (items 42, 506, Chang, items 204A, 204B, 304A, 304B, Burton) beyond respective saw-streets of the second IC dies (items 42, 506, Chang, items 204A, 204B, 304A, 304B, Burton).
In regards to claim 5, Chang (Figs. 4A, 5A-5C, 6A-9D and associated text) as modified by Burton (Figs. 2A, 2B, 3 and associated text) discloses wherein: the substrate is a first substrate (items 411, paragraph 52), and the metallization stack (items 413 plus 414 plus 419) is a first metallization stack (items 413 plus 414 plus 419), the second IC dies (items 42, 506, Chang) comprise respective second metallization stacks and second substrates (item 421, paragraph 52), the second substrates (item 421, paragraph 52) are attached to the second metallization stacks (items 423 plus 428 plus 424, paragraph 52) along respective planar interfaces that are parallel to the second surface (top surface), and the second metallization stacks (items 423 plus 428 plus 424, paragraph 52) comprise conductive traces (items 428 plus 424, paragraph 52) coupled by conductive vias (items 424 plus 428, paragraph 52) to the second bond-pads (item 425, shown but not labeled in Fig. 5B).
In regards to claim 6, Chang (Figs. 4A, 5A-5C, 6A-9D and associated text) as modified by Burton (Figs. 2A, 2B, 3 and associated text) discloses wherein a conductive pathway (items 423 plus 428 plus 424, paragraph 52) comprises conductive traces (items 423 plus 428 plus 424, paragraph 52) in respective second metallization stacks (items 423 plus 428 plus 424, paragraph 52) of the second IC die (items 42, 506, Chang), conductive traces in the first metallization stack (items 413 plus 414 plus 419) of the first IC die (items 401(a)-401(c), 502, 511, 512, 513, or 514, items 504, 521, 522, 523 or 524), and the interconnects (items 419, 413, 427, 425, 516, 526, plurality of dielectric layer, metal lines, vias, paragraph 52, shown but not labeled on item 506, Fig. B, paragraph 56, 535 plus pads shown but not labeled).
In regards to claim 7, Chang (Figs. 4A, 5A-5C, 6A-9D and associated text) as modified by Burton (Figs. 2A, 2B, 3 and associated text) discloses wherein the conductive pathway (items 413 plus 414 plus 419) further comprises active circuitry (items 413 plus 414 plus 419) in the first IC die (items 401(a)-401(c), 502, 511, 512, 513, or 514, items 504, 521, 522, 523 or 524).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chang (US 2022/0352092 A1, Figs. 1-5, 10 and associated text) and Chang et al. (US 2022/0320047 A1, Figs. 1-7A and associated text) discloses the same limitations as Chang used in the above rejection and could have both been used as primary references.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 January 8, 2026