DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 6-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheah et al. (US 2013/0341803, of record).
Regarding claim 1, Cheah et al. discloses, as shown in Figures 1A-2E, an integrated circuit (IC) die comprising:
a metallization stack (125,127,129,131,133,135) comprising a dielectric material, a plurality of layers of conductive traces (no label) in the dielectric material (no label) and conductive vias (no label) through the dielectric material (Figures 1A-1B, 2A-2B, [0020], no label but inherently having conductive traces, vias in the dielectric material); and
a substrate (124,126,128,180,132,134) attached to the metallization stack along a planar interface (108),
wherein:
the metallization stack comprises bond-pads (no label) on a first surface (top surface between 125 and 123, see Figures 1A, 2A, and 3F-3I), a second surface (right side of 120), a third surface (left side of 120), a fourth surface (bottom side of 120), and a fifth surface (upper side of 120) [Figures 1C, 2D-2E, 3H-3I],
the first surface (top surface) is parallel to the planar interface between the metallization stack and the substrate,
the second surface (right side of 120) is parallel to the third surface (left side of 120) and orthogonal to the first surface, and
the fourth surface (bottom side of 120) is parallel to the fifth surface (top side of 120) and orthogonal to the first surface and the second surface.
Regarding claim 2, Cheah et al. discloses the first surface, the second surface, the third surface, the fourth surface and the fifth surface are flat and planar with surface roughness less than 10 Angstroms and TTV less than 3 micrometers (planarized surface).
Regarding claim 3, Cheah et al. discloses, wherein:
the conductive traces are parallel to the planar interface, and
the bond-pads (136) on the second surface, the third surface, the fourth surface and the fifth surface comprise portions of the conductive traces exposed on respective surfaces [Figures 1B-1C, 2B-2C, 3H-3I].
Regarding claim 6, Cheah et al. discloses the substrate comprises a region including active circuitry proximate to the planar interface with the metallization stack [0021]-[0022], etc.
Regarding claim 7, Cheah et al. discloses, as shown in Figures 1A-3I (especially Figures 1A-2E and 3D-3I), a microelectronic assembly comprising:
a first IC die (stack 120 having 122-134) comprising a metallization stack (123,125,127,129,131,133,135) and a substrate (122,124,126,128,130,132,134) attached to the metallization stack along a planar interface (horizontal interface between 123,125,127,129,131,133,135 and 122,124,126,128,130,132,134);
a second IC die (right side of 120 (100,201,221,332), see Figures 1C, 2A-2E, 3H-3I) coupled to the first IC die by first interconnects on a first surface of the metallization stack of the first IC die, the first surface being orthogonal to the planar interface; and
a third IC die (left side of 120 (100,200,332), see Figures 1C, 2D-2E, 3H-3I) coupled to the first IC die by second interconnects on a second surface of the metallization stack of the first IC die, the second surface being parallel to the first surface and orthogonal to the planar interface [Figure 13],
wherein:
the metallization stack (123,125,127,129,131,133,135) comprises a dielectric material (no label), a plurality of conductive traces (no label) in the dielectric material and conductive vias (no label) through the dielectric material, coupled to the plurality of conductive traces (Figures 1A-1B, 2A-2B, [0020], no label but inherently having conductive traces, vias in the dielectric material), and
the plurality of conductive traces are parallel to the planar interface.
Regarding claim 8, Cheah et al. discloses conductive pathways between the second IC die and the third IC die are through the first IC die [Figures].
Regarding claim 9, Cheah et al. discloses the second IC die comprises another metallization stack and another substrate attached to the another metallization stack along another planar interface, the another planar interface being parallel to the planar interface of the first IC die [Figure 2A].
Regarding claim 10, Cheah et al. discloses the third IC die comprises another metallization stack and another substrate attached to the another metallization stack along another planar interface, the another planar interface being orthogonal to the planar interface of the first IC die [Figures 1A-2E and 3D-3I].
Regarding claim 11, Cheah et al. discloses the first interconnects and the second interconnects comprise portions of conductive traces in the first IC die exposed on the first surface of the first IC die [Figures 1A-2E and 3D-3I].
Regarding claim 12, Cheah et al. discloses the microelectronic assembly further comprising a fourth IC die (top side of 120 (100,200,332) coupled to the first IC die by fourth interconnects on a third surface of the first IC die, the third surface being orthogonal to the first surface and the second surface and parallel to the planar interface [Figures 1A-2E and 3D-3I].
Regarding claim 13, Cheah et al. discloses the microelectronic assembly further comprising a fourth IC die (bottom side of 120 (100,200,332) in coupled to the first IC die by fourth interconnects on a third surface of the first IC die, the third surface being orthogonal to the first surface, the second surface and the planar interface [Figures 1A-2E and 3D-3I].
Regarding claim 14, Cheah et al. discloses the first IC die comprises active circuitry in the substrate, the active circuitry being proximate to the planar interface [0020]-[0022], etc.
Regarding claim 15, Cheah et al. discloses at least the first IC die comprises through-substrate vias (TSVs) in the substrate [Figures 1A-2E and 3D-3I].
Regarding claim 16, Cheah et al. discloses, as shown in Figures 1A-3I (especially Figures 1A-2E and 3D-3I), a microelectronic assembly, comprising:
a package substrate (146,246,340);
a first IC die (stack 120 having 122-134) coupled to the package substrate by interconnects along a first surface, the first IC die comprising a metallization stack (123,125,127,129,131,133,135) and a substrate (122,124,126,128,130,132,134) attached to the metallization stack along a planar interface parallel to the first surface (Figures 6, 16);
a second IC die (right side of 120 (100,201,221,332), see Figures 1C, 2A-2E, 3H-3I) coupled to the metallization stack of the first IC die by interconnects on a second surface (104) of the metallization stack of the first IC die, the second surface being orthogonal to the planar interface and the first surface; and
a third IC die (left side of 120 (100,201,221,332), see Figures 1C, 2A-2E, 3H-3I) coupled to the metallization stack of the first IC die by interconnects on a third surface (604) of the metallization stack of the first IC die, the third surface being parallel to the second surface and orthogonal to the planar interface and the first surface.
Regarding claim 17, Cheah et al. discloses the microelectronic assembly further comprising a fourth IC die (122), see Figures 1C, 2A-2E, 3H-3I) coupled to a fourth surface (top) of the first IC die, the fourth surface being parallel to the first surface and the planar interface and orthogonal to the second surface and the third surface.
Regarding claim 18, Cheah et al. discloses the microelectronic assembly further comprising a fifth IC die (top side of 120 (100,201,221,332) coupled to a fifth surface of the first IC die, the fifth surface being orthogonal to the first surface, the planar interface, the second surface and the third surface.
Regarding claim 19, Cheah et al. discloses the microelectronic assembly further comprising a sixth IC die (bottom side of 120 (100,201,221,332), see Figures 1C, 2A-2E, 3H-3I) coupled to a sixth surface of the first IC die, the sixth surface being parallel to the fifth surface and orthogonal to the first surface, the planar interface, the second surface and the third surface.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (US 2013/0341803, of record) in view of Chang (US 2022/0352092, of record).
Regarding claim 4, Cheah et al. discloses the claimed invention including the assembly as explained in the above rejection. Cheah et al. does not disclose the dielectric material comprises a compound including silicon and at least one of oxygen and nitrogen. However, Chang discloses a dielectric material comprises a compound including silicon and at least one of oxygen and nitrogen. Note [0054] of Chang. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the dielectric material of Cheah et al. comprising a compound including silicon and at least one of oxygen and nitrogen, such as taught by Chang since this compound is commonly used as the dielectric material.
Further, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the dielectric material having the materials as that claimed by Applicant, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 20, Cheah et al. discloses the claimed invention including the assembly as explained in the above rejection. Cheah et al. does not disclose the second IC die, the third IC die, the fourth IC die, fifth IC die, and the sixth IC die are coupled to the first IC die by metal-metal bonds and dielectric-dielectric bonds. However, Chang discloses an assembly having a first IC die coupled to a second IC die by metal-metal bonds and dielectric-dielectric bonds. Note Figure 5 and [0044] of Chang. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to couple one IC die to another IC die of Cheah et al. by metal-metal bonds and dielectric-dielectric bonds in order to further improve the contact conductive and reduce the overall dimension.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (US 2013/0341803).
Cheah et al. discloses the claimed invention including the assembly as explained in the above rejection. Cheah et al. does not disclose a linear dimension of a largest one of the bond-pads and a pitch between adjacent bond-pads. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, length, pitch, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, length, pitch, thickness, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Response to Arguments
Applicant's arguments filed 06/09/2026 have been fully considered but they are not persuasive.
It is argued, at page 6 of the Remarks, that Cheah et al. vertical side chip interconnections 104 are not on surfaces of metallization stacks (125,127) and that the interconnections 104 are instead on surfaces of the die backside metal routing (138). This argument is not convincing because Cheah et al. discloses, as shown in Figures 1A-2E and 3D-3I (see the markup Figure 1 below), the metallization stack comprises bond-pads (no label or at 136, 236) on the surface of the metallization stacks (123,125,127,129,131,133,135). Therefore, Applicant’s claims 1, 7, and 16 does not distinguish over the Cheah et al. reference.
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Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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