DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-9, 12-18 and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0407920 A1, of record), and further in view of Kim et al. (US 2020/0185314 A1, newly cited, hereinafter Kim’314).
Re Claim 1, Chen teaches a semiconductor package (Fig. 7) comprising:
a first substrate (701, Fig. 7, para [0085]) including at least one insulating layer (marked “insulating layer” in annotated Fig. 7 below), a connection pad (marked “pad” in annotated Fig. 7 below), a first redistribution layer (marked “1st redistribution layer” in annotated Fig. 7 below) embedded in the at least one insulating layer;
a chip structure (101+113+301, Figs. 6 and 7, paras [0020], [0033] and para [0044]) including a first semiconductor chip (101) disposed on the first substrate (701) and including a first through-electrode (111, Figs. 6 and 7, para [0028]), a second semiconductor chip (113) disposed on the first semiconductor chip (101) and electrically connected (see Figs. 6 and 7) to the first semiconductor chip (101) by the first through-electrode (111), and a first encapsulant (301, Figs. 6 and 7, para [0044]) at least partially surrounding the second semiconductor chip (113, see Fig. 7);
a first connection bump (507, Figs. 6 and 7, para [0059]) disposed between the first substrate (701) and the chip structure (101+113+301) and electrically connecting (see Fig. 7) the first through-electrode (111) to the first redistribution layer (701);
a second connection bump (703, Fig. 7, para [0087]) disposed below the first substrate (701) and electrically connected to the connection pad (see Fig. 7);
a second encapsulant (509+712, see Figs. 6 and 7, paras [0061] and [0084]) encapsulating the chip structure (101+113+301) on the first substrate (701);
a second redistribution layer (706, Fig. 7, para [0085]) disposed on the second semiconductor chip (113);
a second substrate (709, Fig. 7, para [0091]) disposed on the second redistribution layer (706);
a third semiconductor chip (711, Fig. 7, para [0093]) disposed on the second substrate (709); and
a connection structure (708, Fig. 7, para [0068]) penetrating the second encapsulant (509+712),
wherein the first semiconductor chip (101) has a first upper surface (top surface of 101) on which a first upper pad (107, see Figs. 6 and 7, para [0021]) is disposed and a first lower surface (bottom surface of 101) on which a first lower pad (marked “1st lower pad” in annotated Fig. 7 below) electrically connected to the first upper pad (107) through the first through-electrode (111) is disposed,
wherein the second semiconductor chip (113) has a second lower surface (bottom surface of 113) on which a second lower pad (123, Figs. 6 and 7, para [0033]) electrically connected (see Figs. 6 and 7) to the first upper pad (107) is disposed,
wherein the second lower surface of the second semiconductor chip (bottom surface of 113) is in direct contact (see Fig. 7) with the first upper surface of the first semiconductor chip (top surface of 101).
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Chen does not disclose the full details of the redistribution structure 701 in Fig. 7, particularly, how the different metallization layers are interconnected within the RDL structure. Hence, it does not disclose:
a redistribution via penetrating through the at least one insulating layer to electrically connect the connection pad to the first redistribution layer;
wherein the redistribution via has a side surface in contact with the at least one insulating layer, and
wherein the redistribution via has a tapered shape along an entirety of the side surface toward the first redistribution layer.
Since, Chen does not disclose the full details of the redistribution layer (RDL) structure, one of ordinary skill would look into related art to learn the detailed electrical connection within a RDL structure. Related art, Kim’314 teaches a detailed RDL structure (11, Figs. 1G-1H, paras [0035] – [0040]) which will be then electrically connected to a chip structure (200, see Fig. 4F). Kim’314 discloses a redistribution via (marked “via” in annotated Fig. 1G below) penetrating through the at least one insulating layer (140, Figs. 1G-1H) to electrically connect the connection pad (144, Figs. 1G-1H) to the first redistribution layer (marked “1st RDL” in annotated Fig. 1G below), wherein the redistribution via has a side surface (side surface of “via”) in contact with the at least one insulating layer (see Figs. 1G-1H), and the redistribution via has a tapered shape (see Figs. 1G-1H) along an entirety of the side surface (side surface of “via”) toward the first redistribution layer (140).
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It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the semiconductor device of Chen, by incorporating the detailed RDL structure as taught by Kim’314, so as to have a fully functional device with a complete RDL structure, providing electrical connections between different redistribution layers, redistribution vias and connection pads, and providing a conducting path between the top and bottom layers of the RDL structure of Chen.
Additionally, Chen also does not disclose a connection pad protruding above a topmost layer of the at least one insulating layer of the RDL. Chen shows that the chip structure (101+113+301, Figs. 6 and 7) is connected to the RDL substrate (701, Fig. 7) via copper pillars (507, Figs. 6-7).
Related art Kim’314 discloses an alternate way (Fig. 4F) of connecting a chip structure (200) to a RDL substrate (11, Figs. 1G-H and 4F), where the lower connection pad (210, Fig. 4F) of the chip structure (200) is connected to the top connection pad (144, Figs. 1G-H and 4F) of the RDL substrate (11) via solder balls (220, Fig. 4F), such that the connection pad (144) protrudes above a topmost layer of the at least one insulating layer of the RDL (140, Fig. 4F), as recited in the claim limitation. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use a known alternate connection structure for connecting a chip structure and a RDL substrate, where the connection is made via solder balls as shown by Kim’314 instead of copper pillars as disclosed by Chen. The use of a known chip-connection structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 2, Chen modified by Kim’314 teaches the semiconductor package of claim 1, wherein the first semiconductor chip (101, Chen) has a width greater than a width of the second semiconductor chip (113, Chen) in a first direction (horizontal width of 101 is greater than that of 113, see Fig. 7, Chen), wherein the first direction is parallel to an upper surface of the first substrate (see Fig. 7, Chen).
Re Claim 3, Chen modified by Kim’314 teaches the semiconductor package of claim 1, wherein the first encapsulant (301, Chen) contacts (see Figs. 6 and 7, Chen) at least a portion of the first upper surface of the first semiconductor chip (a portion of top surface of 101, see Figs. 6 and 7) and at least a portion of a side surface of the second semiconductor chip (side surface of 113, see Figs. 6 and 7).
Re Claim 7, Chen modified by Kim’314 teaches the semiconductor package of claim 1, wherein the second encapsulant (509+712, Chen) fills a space (see Figs. 6 and 7, Chen) between the chip structure (101+113+301, Chen) and the first substrate (701) and at least partially surrounds the first connection bump (507, see Figs. 6 and 7).
Re Claim 8, Chen modified by Kim’314 teaches the semiconductor package of claim 1, wherein the second encapsulant (509+712, Chen) contacts a side surface and an upper surface of the chip structure (101+113+301, see Fig. 7, Chen).
Re Claim 9, Chen modified by Kim’314 teaches the semiconductor package of claim 1, wherein the second encapsulant (509+712, Chen) has an interface with an upper and side surfaces of the first encapsulant (301, see Figs. 6 and 7, Chen), and wherein the interface contacts the upper and side surfaces of the first encapsulant (see Fig. 7, Chen).
Re Claim 12, Chen teaches a semiconductor package comprising:
a substrate (701, Fig. 7, para [0085]) including at least one insulating layer (marked “insulating layer” in annotated Fig. 7 above), a connection pad (marked “pad” in annotated Fig. 7 above), a redistribution layer (marked “1st redistribution layer” in annotated Fig. 7 above) embedded in the at least one insulating layer;
a chip structure (101+113+301, Figs. 6 and 7, paras [0020], [0033] and para [0044]) including a plurality of semiconductor chips (101+113) disposed on an upper surface of the substrate (top surface of 701) and stacked in a direction perpendicular to the upper surface of the substrate (see Fig. 7), and a first encapsulant (301, Figs. 6 and 7, para [0044]) surrounding a side surface of one or more semiconductor chips of the plurality of semiconductor chips (see Fig. 7);
a connection bump (507, Figs. 6 and 7, para [0059]) disposed between the substrate (701) and the chip structure (101+113+301) and electrically connecting the plurality of semiconductor chips to the redistribution layer (see Fig. 7); and
a second encapsulant (509+712, see Figs. 6 and 7, paras [0061] and [0084]) encapsulating the chip structure (101+113+301) on the substrate (701),
wherein the chip structure (101+113+301) has a lower surface (bottom surface of 101) spaced apart (see Fig. 7) from the upper surface of the substrate (top surface of 701),
wherein the second encapsulant (509+712) fills a space (see Fig. 7) between the lower surface of the chip structure (bottom surface of 101) and the upper surface of the substrate (top surface of 701) and surrounds a side surface of the connection bump (507, see Fig. 7),
the plurality of semiconductor chips (101+113) include a first semiconductor chip (101) and a second semiconductor chip (113) disposed on the first semiconductor chip (101),
the plurality of semiconductor chips (101+113) include a memory chip and a processor chip (the semiconductor chips can be logic dies, memory dies or CPU dies, para [0032]),
the second semiconductor chip (113) directly contacts the first semiconductor chip (101, see Fig. 7),
a width of the first semiconductor chip (101) is greater than a width of the second semiconductor chip (113, see Figs. 6 and 7).
Chen does not disclose the full details of the redistribution structure 701 in Fig. 7, particularly, how the different metallization layers are interconnected within the RDL structure. Hence, it does not disclose:
a redistribution via penetrating through the at least one insulating layer to electrically connect the connection pad to the first redistribution layer;
wherein the redistribution via has a side surface in contact with the at least one insulating layer, and
the redistribution via has a tapered shape along an entirety of the side surface toward the first redistribution layer.
Since, Chen does not disclose the full details of the redistribution layer (RDL) structure, one of ordinary skill would look into related art to learn the detailed electrical connection within a RDL structure. Related art, Kim’314 teaches a detailed RDL structure (11, Figs. 1G-1H, paras [0035] – [0040]) which will be then electrically connected to a chip structure (200, see Fig. 4F). Kim’314 discloses a redistribution via (marked “via” in annotated Fig. 1G above) penetrating through the at least one insulating layer (140, Figs. 1G-1H) to electrically connect the connection pad (144, Figs. 1G-1H) to the first redistribution layer (marked “1st RDL” in annotated Fig. 1G below), wherein the redistribution via has a side surface (side surface of “via”) in contact with the at least one insulating layer (see Figs. 1G-1H), and the redistribution via has a tapered shape (see Figs. 1G-1H) along an entirety of the side surface (side surface of “via”) toward the first redistribution layer (140).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the semiconductor device of Chen, by incorporating the detailed RDL structure as taught by Kim’314, so as to have a fully functional device with a complete RDL structure, providing electrical connections between different redistribution layers, redistribution vias and connection pads, and providing a conducting path between the top and bottom layers of the RDL structure of Chen.
Additionally, Chen also does not disclose a connection pad protruding above a topmost layer of the at least one insulating layer of the RDL. Chen shows that the chip structure (101+113+301, Figs. 6 and 7) is connected to the RDL substrate (701, Fig. 7) via copper pillars (507, Figs. 6-7).
Related art Kim’314 discloses an alternate way (Fig. 4F) of connecting a chip structure (200) to a RDL substrate (11, Figs. 1G-H and 4F), where the lower connection pad (210, Fig. 4F) of the chip structure (200) is connected to the top connection pad (144, Figs. 1G-H and 4F) of the RDL substrate (11) via solder balls (220, Fig. 4F), such that the connection pad (144) protrudes above a topmost layer of the at least one insulating layer of the RDL (140, Fig. 4F), as recited in the claim limitation. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use a known alternate connection structure for connecting a chip structure and a RDL substrate, where the connection is made via solder balls as shown by Kim’314 instead of copper pillars as disclosed by Chen. The use of a known chip-connection structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 13, Chen modified by Kim’314 teaches the semiconductor package of claim 12, but Chen does not explicitly state that the first (301, Chen) and second encapsulants (509+712, Chen) include the same type of insulating material.
Chen discloses that the first encapsulant 301 can be a molding compound resin like polyimide (para [0046]). Regarding the second encapsulant (509+712), Chen discloses that the layer 509 can also be made of polyimide (para [0061]). Chen does not explicitly state the material for the layer 712, but discloses that the encapsulation process of 712 is similar to the encapsulation process for layer 301, see para [0084]. Therefore, it would be obvious to one of ordinary skill that the material for the layer 712 can also be molding compound resin like polyimide, similar to 301, as that would streamline the manufacturing process and reduce cost by utilizing the same material for all the encapsulants.
Re Claim 14, Chen modified by Kim’314 teaches the semiconductor package of claim 12, wherein an upper surface of the chip structure (top surface of 101+113+301, Chen) includes an upper surface of the first encapsulant (top surface of 301, see Fig. 7, Chen) and an upper surface of an uppermost semiconductor chip (top surface of 113, see Fig. 7) among the plurality of semiconductor chips (101+113).
Re Claim 15, Chen modified by Kim’314 teaches the semiconductor package of claim 12, wherein the chip structure (101+113+301, Chen) has an upper surface (top surface of 113, see Fig. 7, Chen) opposite to the lower surface of the chip structure (bottom surface of 101, see Fig. 7) and a side surface extending between the lower surface of the chip structure and the upper surface of the chip structure (side surface of 101, see Fig. 7), and
wherein the second encapsulant (509+712, Chen) covers (see Fig. 7, Chen) the upper surface (top surface of 113) and the side surface of the chip structure (side surface of 101).
Re Claim 16, Chen modified by Kim’314 teaches the semiconductor package of claim 12, but Chen does not explicitly disclose that the chip structure (101+113+301) has a height between 200 µm and 1000 µm in the direction perpendicular to the upper surface of the substrate.
Chen discloses that the depth of the TSVs within the semiconductor chip 101, can be between 20 and 200 µm, para [0028], and one of ordinary skill in the art would realize that the depth of TSVs is comparable to the height of the semiconductor chip. Considering, a height of one semiconductor chip to be 150 µm, the total height of the chip structure would be 150 x 2 = 300 µm, within the claimed range. The claimed thickness of the semiconductor chips would have been obvious to optimize and ascertainable through routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Re Claim 17, Chen modified by Kim’314 teaches the semiconductor package of claim 12, wherein one or more semiconductor chips (101, Chen) of the plurality of semiconductor chips (101+113, Chen) include a through-electrode (111, Figs. 6 and 7, para [0028], Chen), and
wherein the plurality of semiconductor chips (101+113) are electrically connected to each other through the through-electrode (111, see Fig. 7, Chen).
Re Claim 18, Chen teaches A semiconductor package comprising:
a substrate (701, Fig. 7, para [0085]) including at least one first insulating layer (marked “1st insulating layer” in annotated Fig. 7 below), a connection pad (marked “pad” in annotated Fig. 7 below), a first redistribution layer (marked “1st redistribution layer” in annotated Fig. 7 below) embedded in the at least one first insulating layer;
a chip structure (101+113+301, Figs. 6 and 7, paras [0020], [0033] and para [0044]) including a plurality of semiconductor chips (101+113) disposed on an upper surface of the substrate (top surface of 701) and stacked in a direction, perpendicular to the upper surface of the substrate (see Fig. 7), and a first encapsulant (301, Figs. 6 and 7, para [0044]) surrounding a side surface of one or more semiconductor chips of the plurality of semiconductor chips (see Fig. 7);
a connection bump (507, Figs. 6 and 7, para [0059]) disposed between the substrate (701) and the chip structure (101+113+301) and electrically connecting the plurality of semiconductor chips to the connection pad (see Fig. 7);
a second encapsulant (509+712, see Figs. 6 and 7, paras [0061] and [0084]) covering (see Fig. 7) an upper surface (top surface of 113) and a lower surface of the chip structure (bottom surface of 101);
a redistribution structure (706, Fig. 7, para [0068]) including a second insulating layer (marked “2nd insulating layer” in annotated Fig. 7 below, 706 comprises of a series of conductive layers embedded within a series of dielectric layers, para [0073]) disposed on the second encapsulant (509+712), and a second redistribution layer disposed on the second insulating layer (marked “2nd redistribution layer” in annotated Fig. 7 below); and
a connection structure (708, Fig. 7, para [0068]) penetrating through the second encapsulant (509+712) to electrically connect (see Fig. 7) the first redistribution layer (701) to the second redistribution layer (“2nd redistribution layer”),
wherein the plurality of semiconductor chips (101+113) include a memory chip and a processor chip (the semiconductor chips can be logic dies, memory dies or CPU dies, para [0032]).
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Chen does not disclose the full details of the redistribution structure 701 in Fig. 7, particularly, how the different metallization layers are interconnected within the RDL structure. Hence, it does not disclose:
a first redistribution via penetrating through the at least one insulating layer to electrically connect the connection pad to the first redistribution layer;
wherein the first redistribution via has a side surface in contact with the at least one first insulating layer, and
wherein the first redistribution via has a tapered shape along an entirety of the side surface toward the first redistribution layer.
Since, Chen does not disclose the full details of the redistribution layer (RDL) structure, one of ordinary skill would look into related art to learn the detailed electrical connection within a RDL structure. Related art, Kim’314 teaches a detailed RDL structure (11, Figs. 1G-1H, paras [0035] – [0040]) which will be then electrically connected to a chip structure (200, see Fig. 4F). Kim’314 discloses a redistribution via (marked “via” in annotated Fig. 1G above) penetrating through the at least one insulating layer (140, Figs. 1G-1H) to electrically connect the connection pad (144, Figs. 1G-1H) to the first redistribution layer (marked “1st RDL” in annotated Fig. 1G below), wherein the redistribution via has a side surface (side surface of “via”) in contact with the at least one insulating layer (see Figs. 1G-1H), and the redistribution via has a tapered shape (see Figs. 1G-1H) along an entirety of the side surface (side surface of “via”) toward the first redistribution layer (140).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the semiconductor device of Chen, by incorporating the detailed RDL structure as taught by Kim’314, so as to have a fully functional device with a complete RDL structure, providing electrical connections between different redistribution layers, redistribution vias and connection pads, and providing a conducting path between the top and bottom layers of the RDL structure of Chen.
Additionally, Chen also does not disclose a connection pad protruding above a topmost layer of the at least one insulating layer of the RDL. Chen shows that the chip structure (101+113+301, Figs. 6 and 7) is connected to the RDL substrate (701, Fig. 7) via copper pillars (507, Figs. 6-7).
Related art Kim’314 discloses an alternate way (Fig. 4F) of connecting a chip structure (200) to a RDL substrate (11, Figs. 1G-H and 4F), where the lower connection pad (210, Fig. 4F) of the chip structure (200) is connected to the top connection pad (144, Figs. 1G-H and 4F) of the RDL substrate (11) via solder balls (220, Fig. 4F), such that the connection pad (144) protrudes above a topmost layer of the at least one insulating layer of the RDL (140, Fig. 4F), as recited in the claim limitation. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use a known alternate connection structure for connecting a chip structure and a RDL substrate, where the connection is made via solder balls as shown by Kim’314 instead of copper pillars as disclosed by Chen. The use of a known chip-connection structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 20, Chen modified by Kim’314 teaches the semiconductor package of claim 18, further comprising:
a cover layer (705, Fig. 7, para [0068], Chen) covering the second redistribution layer (“2nd redistribution layer”, Chen) and disposed on the redistribution structure (706, Chen) and having an opening exposing at least a portion of the second redistribution layer (marked “openings” in annotated Fig. 7 above, exposing portions of “2nd redistribution layer” , Chen).
Re Claim 21, Chen modified by Kim’314 teaches the semiconductor package of claim 18, further comprising a third semiconductor chip (711, Fig. 7, para [0091] , Chen) disposed on the redistribution structure (706, Chen).
Re Claim 22, Chen modified by Kim’314 teaches the semiconductor package of claim 18, wherein the plurality of semiconductor chips (101+113, Chen) include a first chip (101), and a second chip (113) disposed on the first chip (101) and directly contacting the first chip (see Fig. 7, Chen), and a width of the first semiconductor chip is greater than a width of the second semiconductor chip (horizontal width of 101 is greater than that of 113, see Fig. 7, Chen).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0407920 A1, of record) and Kim et al. (US 2020/0185314 A1, newly cited, hereinafter Kim’314), and further in view of Kim et al. (US 2020/0135683 A1, of record, hereinafter Kim’683).
Re Claim 4, Chen modified by Kim’314 teaches the semiconductor package of claim 1, wherein the second semiconductor chip (113, Chen) has a second upper surface (top surface of 113).
Chen does not disclose a second upper pad, and wherein the second semiconductor chip further includes a second through-electrode electrically connecting the second upper pad to the second lower pad.
However, Chen discloses a stacked semiconductor device and one of ordinary skill would realize that further chips can be stacked on the device of Chen, thus increasing the functional capabilities of the device while reducing footprint and improving power efficiency. Related art from Kim’683 teaches a stacked chip structure (Fig. 5) with three stacked layers, which will further increase the operational capabilities while reducing areal footprint, and thereby having a further optimized chip structure with improved efficiency.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to have a third semiconductor chip stacked on the second semiconductor chip of Chen, as taught by Kim’683 as that would further increase the operational capabilities of the semiconductor device of Chen while reducing areal footprint, and thereby having a further optimized chip structure with improved efficiency. One of ordinary skill would also realize that there will be necessary electrical modifications within the second semiconductor chip to provide electrical and signal communications to the third semiconductor chip above.
Thus, Chen modified by Kim’683 teaches:
a second upper pad (227P, Fig. 5, para [0061], Kim’683) disposed on the second upper surface (top surface of 220a, Fig. 5, para [0053], Kim’683, similar to, top surface of 113 of Chen), and wherein the second semiconductor chip (220a of Kim’683, similar to, 113 of Chen) further includes a second through-electrode (225, Fig. 5, para [0058], Kim’683) electrically connecting the second upper pad (227P, Kim’683) to the second lower pad (226P, Fig. 5, para [0061], Kim’683, similar to, 123 in Figs. 6 and 7 of Chen).
Re Claim 5, Chen modified by Kim’314 and Kim’683 teaches the semiconductor package of claim 4, wherein the chip structure further includes a third semiconductor chip (220b, Fig. 5, para [0053], Kim’683) disposed on the second semiconductor chip (220a of Kim’683, similar to, 113 of Chen) and disposed below the second redistribution layer (706, Chen), the third semiconductor chip (220b, Kim’683) having a third lower surface (bottom surface of 220b, Fig. 5, Kim’683) on which a third lower pad (228P, Fig. 5, para [0061], Kim’683) electrically connected to the second upper pad (227P, Kim’683) is disposed, and
wherein the third lower surface of the third semiconductor chip (bottom surface of 220b, Fig. 5, Kim’683) is in direct contact (see Fig. 5, Kim’683) with the second upper surface of the second semiconductor chip (top surface of 220a, Kim’683)
Re Claim 6, Chen modified by Kim’314 and Kim’683 teaches the semiconductor package of claim 5, wherein a third upper surface of the third semiconductor chip (top surface of 220b, Kim’683) is exposed from the first encapsulant (240a, Fig. 5, para [0053], Kim’683, similar to, 301 in Figs. 6 and 7 of Chen).
Claims 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0407920 A1, of record) and Kim et al. (US 2020/0185314 A1, newly cited, hereinafter Kim’314), and further in view of Chen et al. (US 2015/0262909 A1, of record, hereinafter “Chen2”).
Re Claim 19, Chen modified by Kim’314 teaches the semiconductor package of claim 18, wherein the redistribution structure (706, Chen) further includes a redistribution via (via within 706, see Fig. 7) penetrating through the insulating layer (“insulating layer”) to electrically connect the second redistribution layer (“2nd redistribution layer”) to the connection structure (708).
Chen does not teach that a width of a lower portion of the redistribution via is different from a width of an upper portion of the redistribution via.
However, Chen does disclose that a conduction via can be tapered as shown in Fig. 7, where the conduction via within layer 705 is tapered. Additionally, in a related semiconductor art Chen2 discloses that it can be advantageous to have the vias tapered as the stress applied to the RDLs by the through-vias is reduced, and hence the breakage of the RDLs is reduced, and the reliability of the resulting package is improved (para [0042]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the redistribution vias of Chen so that they are tapered, as taught by Chen2, because tapered vias reduce stress applied to the RDLs, and hence the breakage of the RDLs is reduced, and the reliability of the resulting package is improved (para [0042], Chen2).
Response to Arguments
Applicant’s arguments with respect to claims 1, 12 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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