DETAILED ACTION
This action is in response to communications filed on 01/16/2026. Claims 1, 11, 14-16, and 20 have been amended, no new claims have been added nor cancelled. Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Provisional Non-Statutory Double Patenting (Claims 1, 5-11, and 15-19)
Applicant has requested that the rejections of claims 1, 5-11, and 15-19 under non-statutory double patenting be held in abeyance until the final scope of the claims of at least one of the present application or the co-pending application is resolved.
Per MPEP 804(I)(B)(1), “A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims, or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only compliance with objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. ”.
The reply filed on 01/16/2026 is not fully responsive to the prior Office action because of the following omission(s) or matter(s):
The request presented by the applicant to hold in abeyance the NSDP rejections does not conform to the requirements of the complete response to the NSDP rejection set forth above because the applicant has not effectively shown in the filed response that the claims subject to the rejection are patentably distinct from the reference claims, nor filed a terminal disclaimer.
Nonetheless, per MPEP 714.03, the Examiner may treat an amendment not fully responsive to a non-final Office action by accepting the amendment as an adequate reply to the non-final Office action to avoid abandonment. Accordingly, the present claim set of the instant application has been evaluated with the currently-pending claims of application number 17/990,005 filed 10/30/2025. The changes to the claims appear to be insignificant and appear to only be minor changes in wording to explicitly state what is already implied by the claims, which is not enough to overcome the rejections. The rejections to claims 1, 5-11, and 15-19 under provisional nonstatutory double patenting are maintained.
Provisional Statutory Double Patenting (Claim 20)
The applicant has amended claim 20 to incorporate the additional limitation “a control interface configured to control operation of the feedback representation” such that claim 20 is no longer coextensive in cope with claim 18 of copending application 17/990,005.
The amendment to the claim distinguishes the scope of claim 20 of the instant application from that claimed in claim 18 of the reference application such that the rejection under 35 U.S.C. § 101 for provisional statutory double patenting is no longer applicable. The rejection has been withdrawn.
Rejections under 35 U.S.C. § 103 (Claims 1-2, 407, 11-12, 14-16, and 20)
Applicant has amended claim 1 in response to the previously set forth rejections under 35 U.S.C. § 103 in view of Verma and Varambally. Applicant argues that the references alone and in combination fail to disclose or suggest the features of providing simulated feedback by a feedback representation associated with a node in response to an output generated at that node.
Applicant's arguments filed 01/16/2026 have been fully considered but they are not persuasive, for the reasoning set forth below:
Applicant argues that Verma does not disclose reinjecting outputs of the circuit back into the circuit as a simulated feedback, nor any structure or logic associated with a node that provides such feedback. Applicant further argues that equating Verma’s test bench stimulus to initiate circuit operation is not the same as, nor comparable to, a feedback representation that provides feedback to the circuit.
As set forth in the rejection stated previously, Verma alone is not relied upon to disclose the feedback mechanism; however Varambally is relied upon to incorporate the feedback representation to provide feedback to a DUT (See at least Varambally Figure 1). One cannot show nonobviousness by attacking references individually where the rejections are based on a combination of references. The argument presented by the applicant fails to consider the combination of references of both Verma and Varambally together and merely attacks the Verma reference for what is not disclosed, though this deficiency has already been fully acknowledged by the Examiner per the previous action.
Applicant argues that the Verma reference teaches away from the claimed feedback mechanism by disclosing bypassing simulation of a design block when a matching input stimulus has been previously simulated.
Verma does not teach away from the claimed invention but rather presents a solution where simulating input may be bypassed in addition to leveraging input simulations that can be dynamically generated. Verma does not implicitly or explicitly teach that the testbench providing stimulus should not be informed by test output, but merely offers an embodiment where a test bench is received to provide various test stimulus. ((Verma, ¶3) " The logical design can be functionally verified, for example, utilizing a design verification tool, which can simulate the functionality of the logical design in response to various test stimulus. The design verification tool also may simulate a test bench, which can generate different test stimulus and provide the test stimulus to the simulated logical design."); ((Verma, ¶19) " The design verification tool 300 can receive a test bench 302 capable of defining test stimulus, for example, clock signals, activation signals, power signals, control signals, and data signals that, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 in a verification environment, such as a simulation environment or an emulation environment."). Verma in fact notes that the test bench itself may be subject to modification based on insights gained from previously recorded coverage events, indicating that the test bench is not so limited by the disclosure to be unchangeable in response to feedback ((Verma, ¶4) " The design verification tool also can record coverage events that occurred during simulation with the test bench, which can identify how well the test stimulus exercised the functionality of the logical design. The designer can review the recorded coverage events to identify holes or gaps in coverage for the test bench, and generate new test benches that can attempt to exercise the functionality in the logical design differently to fill the holes or gaps in the coverage. Both debugging and coverage can motivate designers to undergo the time-consuming process of iteratively simulating the logical design with different test stimulus before considering the logical design functionally verified."). As stated previously, Verma alone is not even relied upon to disclose the feedback mechanism. Rather, the combination of Verma and Varambally are relied upon to disclose the features of claim 1 including the feedback mechanism. As noted in the previous action, it would have been obvious to combine the references because there exists a teaching, motivation, or suggestion in the prior art to combine such references. Verma explicitly states that test bench components may in fact be dynamically generated, though Verma does not present any articulated approach as to how the dynamic generation may occur. ((Verma, ¶19) "The design verification tool 300 can receive a test bench 302 capable of defining test stimulus, for example, clock signals, activation signals, power signals, control signals, and data signals that, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 in a verification environment, such as a simulation environment or an emulation environment. In some embodiments, the test bench 302 can be written in an object-oriented programming language, for example, System Verilog or the like, which, when executed during elaboration, can dynamically generate test bench components for verification of the circuit design 301."). Varambally is relied upon to disclose how the testbench provided inputs can be generated using feedback such that full coverage is achieved for scenarios tested in design verification ((Varambally, Page 2, Col 1, ¶3) " This can be done with a machine learning based approach which will enable a more exhaustive testing of corner cases. The key to do this is to use functional coverage and test result as a feedback to the system. Coverage metrics can convey device configurations used, cases covered and more importantly, scenarios not yet covered in verification. Inputs are then automatically modelled to hit non covered scenarios."). Although a prima facie case of obvious may be rebutted by showing that the art teaches away from the claimed invention, this burden has not been met by the applicant by the arguments presented because there is no articulated reasoning as to why the references would have not been combinable. Rather, the applicant has merely stated that a singular reference fails to disclose a claimed element in the same way as presented in the claims. Accordingly, the applicant’s argument that Verma alone teaches away from the claimed invention is irrelevant because the prior art’s teachings together are in fact supportive of a combination that would have resulted in the claimed invention, as presented herein.
Applicant argues that Varambally fails to remedy the deficiencies of Verma because Varambally’s feedback is fundamentally different from the feedback recited in claim 1. Particularly, applicant notes that Varambally’s feedback is applied offline, between simulation runs, to influence future regressions and Varambally’s feedback does not disclose providing feedback to the circuit under test, does not disclose associating feedback logic with a node of a circuit, and does not disclose injecting simulated feedback into a running simulation in response to a node output.
Examiner disagrees and reiterates that the applicant fails to consider the references in combination and appears to attack Varambally individually. The feedback is provided to inform the modification of the test bench which feeds the stimulus to the circuit. Accordingly, the feedback is considered when providing inputs to the circuit under test, particularly as ML based inputs. Further, the feedback logic is depicted as being associated with a node of the circuit in Figure 1. Under broadest reasonable interpretation, a node is understood to be a connection point between components and it can clearly be seen in Figure 1 that a connection point exists between the left edge of the device under test and the test bench, wherein the testbench comprises logic employed as part of the feedback loop indicated by the connection between the multiple components with in/out arrows. Stimulus is generated via simulation (Varambally, Page 2, Col 2, ¶2) as input to a device under test, wherein the stimulus is determined based on the output of the device under test. With these concepts provided by Varambally, taken in combination with that disclosed by Verma, the claimed features of Claim 1 are effectively disclosed. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e. arguing that the feedback is applied offline vs in a running simulation) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant further argues that even if the references Verma and Varambally were combined, the resulting system would at most generate improved or modified input stimuli for future simulations based on prior results and would still lack a feedback representation associated with a node that provides simulated feedback to the circuit in response to an output generated at that node.
By imparting the testbench configuration of Varambally into the testbench connected to the circuit disclosed by Verma, a feedback representation is effectively associated with a node that provides simulated feedback to the circuit in response to the output generated at the node by the circuit.
Applicant further argues that the combination of references undermines Verma’s stated objective of bypassing simulation based learned results and that the Office’s rejection rests on impermissible hindsight reconstruction. Applicant further argues that the modification does not have an articulated motivation.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). Verma clearly suggests that the testbench of the system may be modified according to output results and Varambally likewise clearly discloses a mechanism by which to update a test bench for generating stimulus, wherein the update is based on device under test output and enables the generation of input stimulus back to the device under test. The motivation to combine has been articulated previously in this response as well as in the previous action, contrary to applicant’s statement that no articulated motivation has been presented.
Applicant states that the Office’s rejection rests on an improper interpretation of the claim language in which the “feedback representation” is effectively read out of the claim and replaced with a generic test bench or stimulus source.
Under broadest reasonable interpretation, a feedback representation could be any component that represents the feedback symbolically, graphically, or otherwise. The feedback representation is not defined by the claim in any manner such that would be improper to interpret this language broadly as such. For example, a feedback representation may be broadly interpreted as the cumulative element connected through data lines that exhibit a feedback loop. This interpretation can clearly be seen in Varambally Figure 1, where there is a box element that is representative of computational structures and wherein such elements in the boxed structure receive and output data. This block of elements connected by the corresponding data lines that effectively provide simulated feedback to a device under test in response to the circuit’s output. Even when read in light of the specification, it is not abundantly clear what structural components may comprise the feedback representation such that the meaning of such vague language could be clearly interpreted otherwise. The specification notes that the feedback representation emulates required communications from the external component to the I/O module [0009], a feedback representation is configured to emulate operation of an external component or external interface [0014], the feedback can be configured based on a behavioral model [0016], etc. and it appears that the feedback representation is described in the specification by what it does and not by what it actually is. Additionally, in the drawings, the feedback representation is represented by a box component. Accordingly, the interpretation employed by the examiner is reasonable based on the description and features of the feedback representation actually claimed.
For the reasons stated in this response, in conjunction with the updated rejection of this office action, the claims 1-2, 4-7, 11-12, 14-16, and 20 remain rejected under 35 U.S.C. § 103.
Rejections under 35 U.S.C. § 103 (Claims 3 and 13)
Applicant argues that because claims 3 and 13 depend from claims 1 and 11 respectively, they should be allowable over the prior art according to the amendments and arguments set forth previously.
As discussed above and in this action, the examiner is not convinced by the arguments presented and asserts that the proposed combination of Verma and Varambally applied to the independent claims 1 and 11 sufficiently disclose the entirety of the claimed features. The additional features of the dependent claims are disclosed as stated in this action, in view of Koker. Accordingly, the rejections are maintained.
Rejections under 35 U.S.C. § 103 (Claims 8-10 and 17-19)
Applicant argues that because claims 8-10 and 17019 depend from claims 1 and 11 respectively, they should be allowable over the prior art according to the amendments and arguments set forth previously.
As discussed above and in this action, the examiner is not convinced by the arguments presented and asserts that the proposed combination of Verma and Varambally applied to the independent claims 1 and 11 sufficiently disclose the entirety of the claimed features. The additional features of the dependent claims are disclosed as stated in this action, in view of Irissou. Accordingly, the rejections are maintained.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 5-11, and 15-19 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-10, and 13-17 of copending Application No. 17/990,005 (reference application, see currently pending claims filed 10/30/2025). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the reference claims. That is to say, the examined claims are generic to the reference claims. The examined claims reference a feedback representation, whereas the reference claims reference a mixed signal feedback representation, which is understood to be encompassed by an unspecified feedback representation, as presented in the instant application. The reference claims further introduce a limitation “to generate a simulated circuit” which is likewise anticipated by the examined claims. The addition to the examined claims of “by the feedback representation” is insufficient to demonstrate a patentably distinguishable feature because the presently examined claims merely explicitly state what is implicitly given by the corresponding reference claim. This difference is minor and amounts to a difference in claim wording wherein the added limitation does not add a non-obvious technical step or effect, when read in light of the specifications. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant Application (17/846,341)
Reference Application (17/990,005)
1. A method comprising: receiving a circuit representation comprising a node and a feedback representation associated with the node; simulating a circuit in the circuit representation; and in response to the simulated circuit generating an output at the node associated with the feedback representation, providing simulated feedback to the simulated circuit at the node by the feedback representation.
1. A method comprising: receiving a circuit representation comprising a node and a mixed signal feedback representation associated with the node; simulating operation of a circuit in the circuit representation to generate a simulated circuit; and in response to the simulated circuit generating an output at the node associated with the mixed signal feedback representation, providing simulated mixed signal feedback to the simulated circuit at the node.
5. The method of claim 1, wherein the simulated feedback is based on the feedback representation, the method further comprising configuring the feedback representation to control the simulated feedback.
4. The method of claim 1, wherein the simulated mixed signal feedback is based on the mixed signal feedback representation, the method further comprising configuring the mixed-signal feedback representation to control the simulated mixed signal feedback.
6. The method of claim 5, wherein configuring the feedback representation comprises configuring the feedback representation based on a behavioral model or a machine learning model.
5. The method of claim 4, wherein configuring the mixed signal feedback representation comprises configuring the mixed signal feedback representation based on a behavioral model or a machine learning model.
7. The method of claim 5, wherein configuring the feedback representation comprises configuring the feedback representation to produce errors, distortions, or random data in the simulated feedback.
6. The method of claim 4, wherein configuring the mixed signal feedback representation comprises configuring the mixed signal feedback representation to produce errors, distortions, or random data in the simulated mixed signal feedback.
8. The method of claim 5, wherein the circuit representation includes a control interface operable to configure the feedback representation, the method further comprising including the feedback representation and the control interface in a request for manufacture of the circuit representation.
7. The method of claim 4, wherein the circuit representation includes a control interface operable to configure the mixed signal feedback representation, the method further comprising including the mixed signal feedback representation and the control interface in a request for manufacture of the circuit representation.
9. The method of claim 8, wherein the control interface is operable to selectively bypass the feedback representation.
8. The method of claim 7, wherein the control interface is operable to selectively bypass the mixed signal feedback representation.
10. The method of claim 1, further comprising including the feedback representation in a request for manufacture of the circuit representation.
9. The method of claim 1, further comprising including the mixed signal feedback representation in a request for manufacture of the circuit representation.
11. A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to: receive a circuit representation comprising a node and a feedback representation associated with the node; simulate a circuit in the circuit representation; and in response to the simulated circuit generating an output at the node associated with the feedback representation, provide simulated feedback to the simulated circuit at the node by the feedback representation.
10. A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to: receive a circuit representation comprising a node and a mixed signal feedback representation associated with the node; simulate operation of a circuit in the circuit representation to generate a simulated circuit; and in response to the simulated circuit generating an output at the node associated with the mixed signal feedback representation, provide simulated mixed signal feedback to the simulated circuit at the node.
15. The non-transitory computer readable medium of claim 11, wherein the simulated feedback is based on the feedback representation, the instructions further comprising executable instructions for configuring the feedback representation to control the simulated feedback.
13. The non-transitory computer readable medium of claim 10, wherein the simulated mixed signal feedback is based on the mixed signal feedback representation, the set of executable instructions further comprising instructions for configuring the mixed signal feedback representation to control the mixed signal simulated feedback.
16. The non-transitory computer readable medium of claim 15, wherein the executable instructions for configuring the feedback representation comprise instructions for configuring the feedback representation based on a behavioral model or a machine learning model.
14. The non-transitory computer readable medium of claim 13, wherein the instructions for configuring the mixed signal feedback representation comprise instructions for configuring the mixed signal feedback representation based on a behavioral model or a machine learning model.
17. The non-transitory computer readable medium of claim 15, wherein the circuit representation includes a control interface operable to configure the feedback representation, the instructions further comprising instructions for including the feedback representation and the control interface in a request for manufacture of the circuit representation.
15. The non-transitory computer readable medium of claim 13, wherein the circuit representation includes a control interface operable to configure the mixed signal feedback representation, the set of executable instructions further comprising instructions for including the mixed signal feedback representation and the control interface in a request for manufacture of the circuit representation.
18. The non-transitory computer readable medium of claim 17, wherein the control interface is operable to selectively bypass the feedback representation.
16. The non-transitory computer readable medium of claim 15, wherein the control interface is operable to selectively bypass the mixed signal feedback representation.
19. The non-transitory computer readable medium of claim 11, wherein the instructions further comprise instructions for including the feedback representation in a request for manufacture of the circuit representation
17. The non-transitory computer readable medium of claim 10, wherein the set of executable instructions further comprise instructions for including the mixed signal feedback representation in a request for manufacture of the circuit representation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-7, 11-12, 14-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Verma (US 20180225394 A1), hereinafter referred to as Verma, in view of Varambally et al (Varambally, S., and Sehgal, N., “Optimising Design Verification Using Machine Learning: An Open Source Solution”, December 2020, arXiv),hereinafter referred to as Varambally.
Regarding claim 1, Verma discloses (except the limitations surrounded by brackets ([[..]])) A method comprising: A methodology is disclosed including the features of the claimed invention ((Verma, ¶47) "Any of the operations, processes, and/or methods described herein may be performed by an apparatus, a device, and/or a system substantially similar to those as described herein and with reference to the illustrated figures."); (See also claim 1, method claim)
receiving a circuit representation comprising a node A circuit design is received, wherein the circuit is described in terms of exchange of data signals between components and a node is interpreted as a connection point between components ((Verma, ¶18) "The design verification tool 300 can receive the circuit design 301, which can describe an electronic device both in terms of an exchange of data signals between components in the electronic device, such as hardware registers, flip-flops, combinational logic, or the like, and in terms of logical operations that can be performed on the data signals in the electronic device.") and a [[feedback representation]] associated with the node; A test bench is received wherein the test bench defines test stimulus as input signals that prompt operation of the circuit design ((Verma, ¶19) "The design verification tool 300 can receive a test bench 302 capable of defining test stimulus, for example, clock signals, activation signals, power signals, control signals, and data signals that, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 in a verification environment, such as a simulation environment or an emulation environment. ")
simulating a circuit in the circuit representation; and The electronic circuit corresponding to the circuit design is simulated ((Verma, ¶17) "The simulation system can implement the design verification tool 300 with one or more processors configured to simulate an electronic system corresponding to the circuit design 301."); ((Verma, ¶28) "In some embodiments, the functional verification unit 320 can include a simulator to simulate the functional operations performed by the circuit design 301 in response to test stimulus generated by the test bench 302.")
[[in response to]] the simulated circuit generating an output at the node associated with the [[feedback representation]], During functional verification operations (simulation), the design block (circuit) generates an output in response to the input stimulus (feedback representation) ((Verma, ¶24) "When populated, the input-output mapping can identify input stimulus received by the selected design block during functional verification operations, which can be paired with an output generated by the selected design block in response to the input stimulus during functional verification.") providing simulated [[feedback]] to the simulated circuit at the node [[by the feedback representation]]. The test bench provides input test stimulus to the design block ((Verma, ¶41) "In the verification environment, the test bench may generate test stimulus that, when provided to the circuit design, can prompt the circuit design to perform functional operations, which can be recorded by the design verification tool."). The test bench is described as being simulated and therefore the output generated by the test bench is considered simulated input ((Verma, ¶3) "The design verification tool also may simulate a test bench, which can generate different test stimulus and provide the test stimulus to the simulated logical design.")
Verma does not explicitly disclose; however, Varambally discloses feedback representation, feedback, (See Figure 1 that depicts a series of lines making a feedback loop with the testbench included as a symbolic feedback representation so as to provide a stimulus to the DUT as feedback) and in response to Input stimuli is modified based on the response of the model under test ((Varambally, Col 1, ¶3) "The key to do this is to use functional coverage and test result as a feedback to the system"); by the feedback representation Stimulus is provided to the device under test by the feedback loop comprising the test bench element representing the logic defined therein, see Figure 1.
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Verma and Varambally are both analogous arts because they both pertain to the same field of endeavor of improvements to design verification technologies. It would have been obvious to one of ordinary skill to which said subject matter pertains at the time the invention was filed to have implemented the teachings of Varambally into the method disclosed by Verma because some teaching, suggestion, or motivation would have led one having skill in the art to combine the prior art references to arrive at the claimed invention. Verma discloses that test stimuli are defined by a test bench and that the test bench components (understood to include test stimuli) can be dynamically generated. ((Verma, ¶19) "The design verification tool 300 can receive a test bench 302 capable of defining test stimulus, for example, clock signals, activation signals, power signals, control signals, and data signals that, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 in a verification environment, such as a simulation environment or an emulation environment. In some embodiments, the test bench 302 can be written in an object-oriented programming language, for example, System Verilog or the like, which, when executed during elaboration, can dynamically generate test bench components for verification of the circuit design 301."). Verma does not particularly disclose how the test bench components may be dynamically generated; however, Varambally discloses that stimuli of test benches can be generated based on a plurality of sources ((Varambally, Page 1, Col 1, ¶3- Col 1, ¶1) " A testbench comprising of random stimulus generation, signal monitoring and checking is built using a HVL. Constrained Random Verification generates a random stimulus given a unique input seed for each simulation. The simulations are repeated in regressions with random seeds until full coverage closure is achieved") and that the particular approach is desirable in order to enable a more exhaustive testing ((Varambally, Col 1, ¶3) "Abstracting the need to comprehend the design for verification requires automatic updating of constraints. This can be done with a machine learning based approach which will enable a more exhaustive testing of corner cases. The key to do this is to use functional coverage and test result as a feedback to the system."). Therefore, because Verma suggested that stimuli could be dynamically generated and Varambally discloses that the stimuli could be generated based on the output of the model under test so as to achieve more exhaustive testing, one having skill in the art would be motivated to combine the prior art references to arrive at the claimed invention so as to utilize the more comprehensive approach as disclosed by Varambally.
Regarding claim 2, the proposed combination discloses The method of claim 1, as stated previously. The proposed combination further in view of Varambally discloses wherein the node is located at an external interface of the circuit representation. The points/lines of connection (nodes) and communication (interface) between the test bench and the device under test are depicted as being external to the device under test (as a component of the circuit representation) in Figure 1. ((Varambally, Figure 1)
Regarding claim 4, the proposed combination discloses The method of claim 1, wherein providing simulated feedback to the simulated circuit at the node further comprises as stated previously. The proposed combination further in view of Verma discloses simulating operation of a virtualized component. Functional operations are simulated for the circuit design in response to receiving test stimulus from the test bench.((Verma, ¶28) "In some embodiments, the functional verification unit 320 can include a simulator to simulate the functional operations performed by the circuit design 301 in response to test stimulus generated by the test bench 302."). The circuit design can be simulated or emulated, thereby indicating that the circuit design under test is virtualized ((Verma, ¶28) "Referring back to FIG. 3, the design verification tool 300 can include a functional verification unit 320 to implement a verification environment, which can simulate, emulate, and/or prototype the circuit design 301 and the test bench 302 based on the compiled code from the design compiler 312."). The circuit design describes an electronic device in terms of components ((Verma, ¶18) "The design verification tool 300 can receive the circuit design 301, which can describe an electronic device both in terms of an exchange of data signals between components in the electronic device, such as hardware registers, flip-flops, combinational logic, or the like, and in terms of logical operations that can be performed on the data signals in the electronic device.").
Regarding claim 5, the proposed combination discloses The method of claim 1, as stated previously. The proposed combination in further view of Verma discloses (except the limitations surrounded by brackets ([[..]])) [[wherein the simulated feedback is based on the feedback representation, the method further comprising configuring the feedback representation]] to control the simulated feedback. The input stimulus causes a response (control) of the design block such that the design block generates output ((Verma, ¶24) "When populated, the input-output mapping can identify input stimulus received by the selected design block during functional verification operations, which can be paired with an output generated by the selected design block in response to the input stimulus during functional verification.")
The proposed combination in further view of Verma does not disclose; however, in further view of Varambally discloses wherein the simulated feedback is based on the feedback representation, ML-based stimulus is depicted as being part of the feedback loop in Figure 1, thereby indicating that the simulated feedback is based on the representation (See Fig 1) the method further comprising configuring the feedback representation. A multiplexer is used to switch the source of the stimulus provided by the test bench, thereby indicating that the stimulus (feedback representation) can be configured ((Varambally, Page 2, Col 2, ¶4) "Random stimulus is used in the training phase and a multiplexer is used to switch to the ML based inputs received through feedback from the model during the verification test phase.")
Regarding claim 6, the proposed combination discloses The method of claim 5 wherein configuring the feedback representation comprises as stated previously. The proposed combination in further view of Varambally discloses configuring the feedback representation based on a behavioral model or a machine learning model. The multiplexer outputs random stimulus or ML-based stimulus depending on the configuration indicated by the select line of the multiplexer ((Varambally, Page 2, Col 2, ¶4) "Random stimulus is used in the training phase and a multiplexer is used to switch to the ML based inputs received through feedback from the model during the verification test phase.").
Regarding claim 7, the proposed combination discloses The method of claim 5, wherein configuring the feedback representation comprises as stated previously. The proposed combination in further view of Varambally discloses configuring the feedback representation to produce errors, distortions, or random data in the simulated feedback. The multiplexer outputs random stimulus or ML-based stimulus depending on the configuration indicated by the select line of the multiplexer ((Varambally, Page 2, Col 2, ¶4) "Random stimulus is used in the training phase and a multiplexer is used to switch to the ML based inputs received through feedback from the model during the verification test phase.").
Regarding claim 11, Verma discloses (except the limitations surrounded by brackets ([[..]])) A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to: ((Verma, ¶50) " Operating instructions or commands may be implemented or embodied in tangible forms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. "Computer-readable storage medium" ( or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device ")
receive a circuit representation comprising a node A circuit design is received, wherein the circuit is described in terms of exchange of data signals between components and a node is interpreted as a connection point between components ((Verma, ¶18) "The design verification tool 300 can receive the circuit design 301, which can describe an electronic device both in terms of an exchange of data signals between components in the electronic device, such as hardware registers, flip-flops, combinational logic, or the like, and in terms of logical operations that can be performed on the data signals in the electronic device.") and a [[feedback representation]] associated with the node; A test bench is received wherein the test bench defines test stimulus as input signals that prompt operation of the circuit design ((Verma, ¶19) "The design verification tool 300 can receive a test bench 302 capable of defining test stimulus, for example, clock signals, activation signals, power signals, control signals, and data signals that, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 in a verification environment, such as a simulation environment or an emulation environment. ")
simulate a circuit in the circuit representation; and The electronic circuit corresponding to the circuit design is simulated ((Verma, ¶17) "The simulation system can implement the design verification tool 300 with one or more processors configured to simulate an electronic system corresponding to the circuit design 301."); ((Verma, ¶28) "In some embodiments, the functional verification unit 320 can include a simulator to simulate the functional operations performed by the circuit design 301 in response to test stimulus generated by the test bench 302.")
[[in response to]] the simulated circuit generating an output at the node associated with the [[feedback]] representation, During functional verification operations (simulation), the design block (circuit) generates an output in response to the input stimulus (feedback representation) ((Verma, ¶24) "When populated, the input-output mapping can identify input stimulus received by the selected design block during functional verification operations, which can be paired with an output generated by the selected design block in response to the input stimulus during functional verification.") provide simulated [[feedback]] to the simulated circuit at the node, [[by the feedback representation]]. The test bench provides input test stimulus to the design block ((Verma, ¶41) "In the verification environment, the test bench may generate test stimulus that, when provided to the circuit design, can prompt the circuit design to perform functional operations, which can be recorded by the design verification tool."). The test bench is described as being simulated and therefore the output generated by the test bench is considered simulated input ((Verma, ¶3) "The design verification tool also may simulate a test bench, which can generate different test stimulus and provide the test stimulus to the simulated logical design.")
Verma does not explicitly disclose; however, Varambally discloses feedback representation, feedback, (See Figure 1 that depicts a series of lines making a feedback loop as a feedback representation so as to provide a stimulus to the DUT as feedback) and in response to Input stimuli is modified based on the response of the model under test ((Varambally, Col 1, ¶3) "The key to do this is to use functional coverage and test result as a feedback to the system"). by the feedback representation Stimulus is provided to the device under test by the feedback loop comprising the test bench element representing the logic defined therein, see Figure 1.
Verma and Varambally are both analogous arts because they both pertain to the same field of endeavor of improvements to design verification technologies. It would have been obvious to one of ordinary skill to which said subject matter pertains at the time the invention was filed to have implemented the teachings of Varambally into the method disclosed by Verma because some teaching, suggestion, or motivation would have led one having skill in the art to combine the prior art references to arrive at the claimed invention. Verma discloses that test stimuli are defined by a test bench and that the test bench components (understood to include test stimuli) can be dynamically generated. ((Verma, ¶19) "The design verification tool 300 can receive a test bench 302 capable of defining test stimulus, for example, clock signals, activation signals, power signals, control signals, and data signals that, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 in a verification environment, such as a simulation environment or an emulation environment. In some embodiments, the test bench 302 can be written in an object-oriented programming language, for example, System Verilog or the like, which, when executed during elaboration, can dynamically generate test bench components for verification of the circuit design 301."). Verma does not particularly disclose how the test bench components may be dynamically generated; however, Varambally discloses that stimuli of test benches can be generated based on a plurality of sources and that this particular approach is desirable in order to enable a more exhaustive testing ((Varambally, Col 1, ¶3) "Abstracting the need to comprehend the design for verification requires automatic updating of constraints. This can be done with a machine learning based approach which will enable a more exhaustive testing of corner cases. The key to do this is to use functional coverage and test result as a feedback to the system."). Therefore, because Verma suggested that stimuli could be dynamically generated and Varambally discloses that the stimuli could be generated based on the output of the model under test, one having skill in the art would be motivated to combine the prior art references to arrive at the claimed invention so as to utilize a more comprehensive approach as disclosed by Varambally.
Regarding claim 12, the proposed combination discloses The non-transitory computer readable medium of claim 11, as stated previously. The proposed combination in further view of Varambally discloses wherein the node is located at an external interface of the circuit representation. The points/lines of connection (nodes) and communication (interface) between the test bench and the device under test are depicted as being external to the device under test (as a component of the circuit representation) in Figure 1. ((Varambally, Figure 1)
Regarding claim 14, the proposed combination discloses The non-transitory computer readable medium of claim 11, wherein the executable instructions for providing simulated feedback to the simulated circuit at the node include instructions for as stated previously. The proposed combination in further view of Verma discloses simulating operation of a virtualized component. Functional operations are simulated for the circuit design in response to receiving test stimulus from the test bench.((Verma, ¶28) "In some embodiments, the functional verification unit 320 can include a simulator to simulate the functional operations performed by the circuit design 301 in response to test stimulus generated by the test bench 302."). The circuit design can be simulated or emulated, thereby indicating that the circuit design under test is virtualized ((Verma, ¶28) "Referring back to FIG. 3, the design verification tool 300 can include a functional verification unit 320 to implement a verification environment, which can simulate, emulate, and/or prototype the circuit design 301 and the test bench 302 based on the compiled code from the design compiler 312."). The circuit design describes an electronic device in terms of components ((Verma, ¶18) "The design verification tool 300 can receive the circuit design 301, which can describe an electronic device both in terms of an exchange of data signals between components in the electronic device, such as hardware registers, flip-flops, combinational logic, or the like, and in terms of logical operations that can be performed on the data signals in the electronic device.").
Regarding claim 15, the proposed combination discloses The non-transitory computer readable medium of claim 11, as stated previously. The proposed combination in further view of Verma discloses (except the limitations surrounded by brackets ([[..]])) [[wherein the simulated feedback is based on the feedback representation, the instructions further comprising executable instructions for configuring the feedback representation]] to control the simulated feedback. The input stimulus (feedback representation) causes a response (control) of the design block such that the design block generates output ((Verma, ¶24) "When populated, the input-output mapping can identify input stimulus received by the selected design block during functional verification operations, which can be paired with an output generated by the selected design block in response to the input stimulus during functional verification.")
The proposed combination in further view of Verma does not disclose; however, in further view of Varambally discloses wherein the simulated feedback is based on the feedback representation, ML-based stimulus is depicted as being part of the feedback loop in Figure 1, thereby indicating that the simulated feedback is based on the representation (See Fig 1) the method further comprising configuring the feedback representation. A multiplexer is used to switch the source of the stimulus provided by the test bench, thereby indicating that the stimulus (feedback representation) can be configured ((Varambally, Page 2, Col 2, ¶4) "Random stimulus is used in the training phase and a multiplexer is used to switch to the ML based inputs received through feedback from the model during the verification test phase.")
Regarding claim 16, the proposed combination discloses The non-transitory computer readable medium of claim 15 wherein the executable instructions for configuring the feedback representation comprise instructions for as stated previously. The proposed combination discloses in further view of Varambally configuring the feedback representation based on a behavioral model or a machine learning model. The multiplexer takes random stimulus or ML-based stimulus depending on the configuration indicated by the select line of the multiplexer ((Varambally, Page 2, Col 2, ¶4) "Random stimulus is used in the training phase and a multiplexer is used to switch to the ML based inputs received through feedback from the model during the verification test phase.").
Regarding claim 20, Verma discloses (except the limitations surrounded by brackets ([[..]])) An emulation model comprising: A verification tool may perform an emulation, wherein one having ordinary skill in the art would recognize the need of a corresponding emulation model by which to perform the emulation. ((Verma, ¶17) " Referring to FIG. 3, the design verification tool 300 can be implemented in an emulation system, a simulation system, a combination thereof, or the like, which can functionally verify the circuit design 301. The emulation system can implement the design verification tool 300 with one or more hardware emulators configured to emulate an electronic system corresponding to the circuit design 301").
a circuit representation comprising a node; A circuit design comprises a description of an electronic device in terms of exchange of data signal between components in the electronic device. Examiner has interpreted a node as a point of connection between components wherein data may be exchanged. ((Verma, ¶18) "The design verification tool 300 can receive the circuit design 301, which can describe an electronic device both in terms of an exchange of data signals between components in the electronic device, such as hardware registers, flip-flops, combinational logic, or the like, and in terms of logical operations that can be performed on the data signals in the electronic device.")
a [[feedback representation]] associated with the node of the circuit representation, A test bench defines test stimulus as input signals that prompt operation of the circuit design ((Verma, ¶19) "The design verification tool 300 can receive a test bench 302 capable of defining test stimulus, for example, clock signals, activation signals, power signals, control signals, and data signals that, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 in a verification environment, such as a simulation environment or an emulation environment. ") [[wherein the feedback representation is configured to provide feedback]] to a circuit in the circuit representation The circuit design can model an electronic device in terms of a hardware description language that describes the circuitry details ((Verma, ¶18) " The circuit design 301 can model the electronic device at a register transfer level (RTL), for example, with code in a hardware description language (HDL), such as Very high speed integrated circuit Hardware Design Language (VHDL), System C, or the like."). Portions of the circuit design are described as design blocks, understood in the art to be sub-circuits of a larger circuit design ((Verma, ¶20) "The preprocessing system 310 also can identify portions of the circuit design 301 that correspond to design blocks, and select one or more of the design blocks to utilize for machine learning during functional verification of the circuit design 301.") [[in response to]] the circuit generating a signal The design blocks are associated with an input-output mapping, thereby indicating that the circuit generates an output signal ((Verma, ¶24) "When populated, the input-output mapping can identify input stimulus received by the selected design block during functional verification operations, which can be paired with an output generated by the selected design block in response to the input stimulus during functional verification.") [[at the node; and]]
[[a control interface configured to control operation of the feedback representation]]
Verma does not disclose; however Verma in view of Varambally discloses feedback representation The design block (circuit) generates an output in response to the input stimulus through a feedback loop(feedback representation) that is associated with the exchange of data between the test bench and the DUT (node) ((Verma, ¶24) "When populated, the input-output mapping can identify input stimulus received by the selected design block during functional verification operations, which can be paired with an output generated by the selected design block in response to the input stimulus during functional verification.") wherein the feedback representation is configured to provide feedback Figure 1 depicts a feedback loop containing a multiplexer that is used to configure the stimulus provided to the DUT. in response to… at the node; and . Stimulus is output from the test bench subsequently to receiving output from the DUT at the data exchange point between the two components, as depicted in Figure 1.
a control interface configured to control operation of the feedback representation The circuit representation comprises a switch/multiplexer as a mechanism by which to control the feedback data being input to the device under test, wherein the multiplexer is used to switch between inputs that are provided as feedback ((Varambally, Col 2, ¶4) "The above figure shows the environment used to evaluate the model. The Supervised Learning is accomplished using an ANN model. Random stimulus is used in the training phase and a multiplexer is used to switch to the ML based inputs received through feedback from the model during the verification test phase.")
Verma and Varambally are both analogous arts because they both pertain to the same field of endeavor of improvements to design verification technologies. It would have been obvious to one of ordinary skill to which said subject matter pertains at the time the invention was filed to have implemented the teachings of Varambally into the method disclosed by Verma because some teaching, suggestion, or motivation would have led one having skill in the art to combine the prior art references to arrive at the claimed invention. Verma discloses that test stimuli are defined by a test bench and that the test bench components (understood to include test stimuli) can be dynamically generated. ((Verma, ¶19) "The design verification tool 300 can receive a test bench 302 capable of defining test stimulus, for example, clock signals, activation signals, power signals, control signals, and data signals that, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 in a verification environment, such as a simulation environment or an emulation environment. In some embodiments, the test bench 302 can be written in an object-oriented programming language, for example, System Verilog or the like, which, when executed during elaboration, can dynamically generate test bench components for verification of the circuit design 301."). Verma does not particularly disclose how the test bench components may be dynamically generated; however, Varambally discloses that stimuli of test benches can be generated based on a plurality of sources ((Varambally, Page 1, Col 1, ¶3- Col 1, ¶1) " A testbench comprising of random stimulus generation, signal monitoring and checking is built using a HVL. Constrained Random Verification generates a random stimulus given a unique input seed for each simulation. The simulations are repeated in regressions with random seeds until full coverage closure is achieved") and that the particular approach is desirable in order to enable a more exhaustive testing ((Varambally, Col 1, ¶3) "Abstracting the need to comprehend the design for verification requires automatic updating of constraints. This can be done with a machine learning based approach which will enable a more exhaustive testing of corner cases. The key to do this is to use functional coverage and test result as a feedback to the system."). Therefore, because Verma suggested that stimuli could be dynamically generated and Varambally discloses that the stimuli could be generated based on the output of the model under test so as to achieve more exhaustive testing, one having skill in the art would be motivated to combine the prior art references to arrive at the claimed invention so as to utilize the more comprehensive approach as disclosed by Varambally.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Verma in view of Varambally as applied to claims 2 and 12 above, and further in view of Koker et al (US 20220188967 A1), hereinafter referred to as Koker.
Regarding claim 3 the proposed combination of Verma in view of Varambally discloses The method of claim 2, as stated previously. The proposed combination does not alone disclose; however, the proposed combination in view of Koker discloses wherein the external interface is an intra-die, inter-die, stack-to- stack, or socket-to-socket interface. A multi-chip module is disclosed as having a plurality of semiconductor dies and a plurality of die-to-die interconnects ((Koker, Claim 1) "A multi-chip module comprising: a plurality of semiconductor dies and a plurality of die-to-die interconnects, the plurality of semiconductor dies comprising: a first semiconductor die including: a plurality of graphics processing resources including a graphics multiprocessor coupled with a first cache memory; an interconnect fabric coupled with the first cache memory, wherein the first cache memory is associated with the graphics multiprocessor; and a second cache memory coupled with the interconnect fabric; and a die interface configurable to couple with one or more of a plurality semiconductor dies, the plurality of semiconductor dies including a second semiconductor die that includes a third cache memory and a third semiconductor die that includes a high bandwidth memory (HBM).")
Koker is analogous art because it pertains to the same field of endeavor of improvements in circuit design technologies. It would have been obvious to one of ordinary skill to which said subject matter pertains at the time the invention was filed to have incorporated a multi-chip-module as disclosed by Koker as the particular electronic component in the circuit design as disclosed by Verma because some teaching, suggestion, or motivation in the prior art references would have led one having ordinary skill in the art to do so in order to arrive at the claimed invention. Verma discloses that the circuit design may comprise arrays of FPGAs or processors, or a combination thereof but does not describe the components of the circuit design in more detail ((Verma, ¶28) "The functional verification unit 320 can include a hardware emulator to emulate the circuit design 301 with programmable hardware, such as arrays of field programmable gate array (FPGA) chips, arrays of processors, a combination thereof, or the like."). Koker discloses a computing system that can comprise a multi-chip module that comprises multiple parallel processors ((Koker, ¶56) "In one embodiment, the one or more parallel processor(s) 112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In another embodiment, the one or more parallel processor(s) 112 incorporate circuitry optimized for general purpose processing, while preserving the underlying computational architecture, described in greater detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processor(s) 112, memory hub 105, processor(s) 102, and I/O hub 107 can be integrated into a system on chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system in package (SIP) configuration. In one embodiment at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.") and further specifies that a multi-chip module can comprise multiple dies interconnected through die-to-die interconnect (Koker, Claim 1). Therefore, because Verma suggests a potential configuration for the circuit design to include an array of processors and Koker provides an architecture for describing a processing cluster array that provides particular details as to how the components of the circuit design are interconnected, it would have accordingly been obvious to apply the specific architecture disclosed by Koker as the generic electronic device represented by the circuit design as disclosed by Verma.
Regarding claim 13, the proposed combination of Verma in view of Varambally discloses The non-transitory computer readable medium of claim 12, as stated previously. The proposed combination does not alone disclose; however, the proposed combination in view of koker discloses wherein the external interface is an intra-die, inter-die, stack-to-stack, or socket-to-socket interface. A multi-chip module is disclosed as having a plurality of semiconductor dies and a plurality of die-to-die interconnects ((Koker, Claim 1) "A multi-chip module comprising: a plurality of semiconductor dies and a plurality of die-to-die interconnects, the plurality of semiconductor dies comprising: a first semiconductor die including: a plurality of graphics processing resources including a graphics multiprocessor coupled with a first cache memory; an interconnect fabric coupled with the first cache memory, wherein the first cache memory is associated with the graphics multiprocessor; and a second cache memory coupled with the interconnect fabric; and a die interface configurable to couple with one or more of a plurality semiconductor dies, the plurality of semiconductor dies including a second semiconductor die that includes a third cache memory and a third semiconductor die that includes a high bandwidth memory (HBM).")
Koker is analogous art because it pertains to the same field of endeavor of improvements in circuit design technologies. It would have been obvious to one of ordinary skill to which said subject matter pertains at the time the invention was filed to have incorporated a multi-chip-module as disclosed by Koker as the particular electronic component in the circuit design as disclosed by Verma because some teaching, suggestion, or motivation in the prior art references would have led one having ordinary skill in the art to do so in order to arrive at the claimed invention. Verma discloses that the circuit design may comprise arrays of FPGAs or processors, or a combination thereof but does not describe the components of the circuit design in more detail ((Verma, ¶28) "The functional verification unit 320 can include a hardware emulator to emulate the circuit design 301 with programmable hardware, such as arrays of field programmable gate array (FPGA) chips, arrays of processors, a combination thereof, or the like."). Koker discloses a computing system that can comprise a multi-chip module that comprises multiple parallel processors ((Koker, ¶56) "In one embodiment, the one or more parallel processor(s) 112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In another embodiment, the one or more parallel processor(s) 112 incorporate circuitry optimized for general purpose processing, while preserving the underlying computational architecture, described in greater detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processor(s) 112, memory hub 105, processor(s) 102, and I/O hub 107 can be integrated into a system on chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system in package (SIP) configuration. In one embodiment at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.") and further specifies that a multi-chip module can comprise multiple dies interconnected through die-to-die interconnect (Koker, Claim 1). Therefore, because Verma suggests a potential configuration for the circuit design to include an array of processors and Koker provides an architecture for describing a processing cluster array that provides particular details as to how the components of the circuit design are interconnected, it would have accordingly been obvious to apply the specific architecture disclosed by Koker as the generic electronic device represented by the circuit design as disclosed by Verma.
Claims 8-10, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Verma in view of Varambally as applied to claims 1, 5, 11, and 15 above, and further in view of Irissou et al (US 20180011959 A1), hereinafter referred to as Irissou.
Regarding claim 8, the proposed combination discloses The method of claim 5, as stated previously. The proposed combination in further view of Varambally discloses (except the limitations surrounded by brackets ([[..]])) wherein the circuit representation includes a control interface operable to configure the feedback representation, The circuit representation comprises a switch/multiplexer as a mechanism by which to control the feedback data being input to the device under test, wherein the multiplexer is used to switch between inputs that are provided as feedback ((Varambally, Col 2, ¶4) "The above figure shows the environment used to evaluate the model. The Supervised Learning is accomplished using an ANN model. Random stimulus is used in the training phase and a multiplexer is used to switch to the ML based inputs received through feedback from the model during the verification test phase.") [[the method further comprising including the feedback representation and the control interface in a request for manufacture of the circuit representation.]]
The proposed combination in further view of Varambally discloses (except the limitations surrounded by brackets ([[..]])) [[the method further comprising including]] the feedback representation and the control interface [[in a request for manufacture of the circuit representation.]] The circuit design is described as comprising a feedback representation (as the feedback loop) and a multiplexer (as the control interface), as depicted in Figure 1.
The proposed combination in further view of Varambally does not disclose; however, the proposed combination in view of Irissou discloses the method further comprising including … in a request for manufacture of the circuit representation. A request is made via a foundry interface tool such that the foundry implements circuit designs as prototypes ((Irissou, ¶234) "Upon determining that the pre-determined number of designs are received from one or more of the user accounts 1 through N, the shuttle manager tool 404 sends a request via the foundry interface tool 406 and the computer network 110 to the fabrication computing devices 1 and 2 of the one or more foundry entities for implementing the pre-determined number of designs on the shuttle to manufacture prototypes of SoCs based on the designs. For example, the shuttle manager tool 404 sends the request via the foundry interface tool 406, and the fabrication entity account 1 to the fabrication computing device 1 that is operated by a first foundry entity. As another example, the shuttle manager tool 404 sends the request via the foundry interface tool 406, and the fabrication entity account 2 to the fabrication computing device 2 that is operated by a second foundry entity.")
Irissou is analogous art because it pertains to the same field of endeavor of improvements in electronic design automation technologies. It would have been obvious to one of ordinary skill to which said subject matter pertains at the time the invention was filed to have combined the art of the proposed combination in further view of the teachings of Irissou because some teaching, suggestion, or motivation in the prior art references would have led one having skill in the art to do so in order to arrive at the claimed invention. Verma suggests that part of the design flow of designing and fabricating electronic systems includes a step at a foundry that manufactures the designed electronic system but does not provide particular details of this step ((Verma, ¶2) "Designing and fabricating electronic systems typically involves many steps, known as a design flow. The particular steps of a design flow often are dependent upon the type of electronic system being designed, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system."). Rather, Verma emphasizes improvements on the design verification process of design and manufacture of electronic systems. Irissou discloses a comprehensive system and method for engineering circuit design development which includes specialized software tools to enable design fabrication. Irissou particularly points out that once an IC design is complete and validated by computer modeling that the designer should further validate the design by fabricating a prototype of the IC on a semiconductor wafer ((Irissou, ¶5) "Once a design for an integrated circuit (IC) is complete and validated by computer modeling using various software tools, the designer should validate the design by fabricating a prototype of the IC on a semiconductor wafer. "). Irissou further describes that a prototype can be generated by providing a request to a foundry to manufacture the prototype of the provided design (Irissou, ¶234). Therefore, Verma suggests that circuit designs be manufactured as part of the circuit design process and provides a method for design verification and Irissou further suggests that designs should be further validated by prototyping after performing software validation and provides a system by which to do so. Accordingly, it would have been obvious to one having skill in the art to combine the prior art references to arrive at the claimed invention, per the suggestions and motivations recited in the prior art references.
Regarding claim 9, the proposed combination discloses The method of claim 8, as stated previously. The proposed combination in further view of Varambally discloses wherein the control interface is operable to selectively bypass the feedback representation The multiplexer device may select the random stimulus or alternatively the ML-based stimulus which is part of the feedback representation. By using the random stimulus in the training phase, the multiplexer effectively bypasses the ML based stimulus which steps from the feedback loop ((Varambally, Col 2, ¶4) "The above figure shows the environment used to evaluate the model. The Supervised Learning is accomplished using an ANN model. Random stimulus is used in the training phase and a multiplexer is used to switch to the ML based inputs received through feedback from the model during the verification test phase.")
Regarding claim 10, the proposed combination discloses The method of claim 1, as stated previously. The proposed combination in further view of Varambally discloses (except the limitations surrounded by brackets ([[..]])) [[further comprising including]] the feedback representation [[in a request for manufacture]] of the circuit representation. The circuit design (representation) is described as comprising a feedback representation (as the feedback loop).
The proposed combination in further view of Varambally does not disclose; however the proposed combination in view of Irissou discloses further comprising including …in a request for manufacture A request is made via a foundry interface tool such that the foundry implements circuit designs as prototypes ((Irissou, ¶234) "Upon determining that the pre-determined number of designs are received from one or more of the user accounts 1 through N, the shuttle manager tool 404 sends a request via the foundry interface tool 406 and the computer network 110 to the fabrication computing devices 1 and 2 of the one or more foundry entities for implementing the pre-determined number of designs on the shuttle to manufacture prototypes of SoCs based on the designs. For example, the shuttle manager tool 404 sends the request via the foundry interface tool 406, and the fabrication entity account 1 to the fabrication computing device 1 that is operated by a first foundry entity. As another example, the shuttle manager tool 404 sends the request via the foundry interface tool 406, and the fabrication entity account 2 to the fabrication computing device 2 that is operated by a second foundry entity.")
Irissou is analogous art because it pertains to the same field of endeavor of improvements in electronic design automation technologies. It would have been obvious to one of ordinary skill to which said subject matter pertains at the time the invention was filed to have combined the art of the proposed combination in further view of the teachings of Irissou because some teaching, suggestion, or motivation in the prior art references would have led one having skill in the art to do so in order to arrive at the claimed invention. Verma suggests that part of the design flow of designing and fabricating electronic systems includes a step at a foundry that manufactures the designed electronic system but does not provide particular details of this step ((Verma, ¶2) "Designing and fabricating electronic systems typically involves many steps, known as a design flow. The particular steps of a design flow often are dependent upon the type of electronic system being designed, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system."). Rather, Verma emphasizes improvements on the design verification process of design and manufacture of electronic systems. Irissou discloses a comprehensive system and method for engineering circuit design development which includes specialized software tools to enable design fabrication. Irissou particularly points out that once an IC design is complete and validated by computer modeling that the designer should further validate the design by fabricating a prototype of the IC on a semiconductor wafer ((Irissou, ¶5) "Once a design for an integrated circuit (IC) is complete and validated by computer modeling using various software tools, the designer should validate the design by fabricating a prototype of the IC on a semiconductor wafer. "). Irissou further describes that a prototype can be generated by providing a request to a foundry to manufacture the prototype of the provided design (Irissou, ¶234). Therefore, Verma suggests that circuit designs be manufactured as part of the circuit design process and provides a method for design verification and Irissou further suggests that designs should be further validated by prototyping after performing software validation and provides a system by which to do so. Accordingly, it would have been obvious to one having skill in the art to combine the prior art references to arrive at the claimed invention, per the suggestions and motivations recited in the prior art references.
Regarding claim 17, the proposed combination discloses The non-transitory computer readable medium of claim 15, as stated previously. The proposed combination in view of Varambally discloses (except the limitations surrounded by brackets ([[..]])) wherein the circuit representation includes a control interface operable to configure the feedback representation, The circuit representation comprises a switch/multiplexer as a mechanism by which to control the feedback data being input to the device under test, wherein the multiplexer is used to switch between inputs that are provided as feedback ((Varambally, Col 2, ¶4) "The above figure shows the environment used to evaluate the model. The Supervised Learning is accomplished using an ANN model. Random stimulus is used in the training phase and a multiplexer is used to switch to the ML based inputs received through feedback from the model during the verification test phase.") [[the instructions further comprising instructions for including the feedback representation and the control interface in a request for manufacture of the circuit representation.]]
The proposed combination in further view of Varambally discloses (except the limitations surrounded by brackets ([[..]])) [[the instructions further comprising instructions for including]] the feedback representation and the control interface [[in a request for manufacture of the circuit representation.]]
The circuit design is described as comprising a feedback representation (as the feedback loop) and a multiplexer (as the control interface), as depicted in Figure 1.
The proposed combination in further view of Varambally does not disclose; however, the proposed combination in view of Irissou discloses the instructions further comprising instructions for including…in a request for manufacture of the circuit representation. A request is made via a foundry interface tool such that the foundry implements circuit designs as prototypes ((Irissou, ¶234) "Upon determining that the pre-determined number of designs are received from one or more of the user accounts 1 through N, the shuttle manager tool 404 sends a request via the foundry interface tool 406 and the computer network 110 to the fabrication computing devices 1 and 2 of the one or more foundry entities for implementing the pre-determined number of designs on the shuttle to manufacture prototypes of SoCs based on the designs. For example, the shuttle manager tool 404 sends the request via the foundry interface tool 406, and the fabrication entity account 1 to the fabrication computing device 1 that is operated by a first foundry entity. As another example, the shuttle manager tool 404 sends the request via the foundry interface tool 406, and the fabrication entity account 2 to the fabrication computing device 2 that is operated by a second foundry entity.")
Irissou is analogous art because it pertains to the same field of endeavor of improvements in electronic design automation technologies. It would have been obvious to one of ordinary skill to which said subject matter pertains at the time the invention was filed to have combined the art of the proposed combination in further view of the teachings of Irissou because some teaching, suggestion, or motivation in the prior art references would have led one having skill in the art to do so in order to arrive at the claimed invention. Verma suggests that part of the design flow of designing and fabricating electronic systems includes a step at a foundry that manufactures the designed electronic system but does not provide particular details of this step ((Verma, ¶2) "Designing and fabricating electronic systems typically involves many steps, known as a design flow. The particular steps of a design flow often are dependent upon the type of electronic system being designed, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system."). Rather, Verma emphasizes improvements on the design verification process of design and manufacture of electronic systems. Irissou discloses a comprehensive system and method for engineering circuit design development which includes specialized software tools to enable design fabrication. Irissou particularly points out that once an IC design is complete and validated by computer modeling that the designer should further validate the design by fabricating a prototype of the IC on a semiconductor wafer ((Irissou, ¶5) "Once a design for an integrated circuit (IC) is complete and validated by computer modeling using various software tools, the designer should validate the design by fabricating a prototype of the IC on a semiconductor wafer. "). Irissou further describes that a prototype can be generated by providing a request to a foundry to manufacture the prototype of the provided design (Irissou, ¶234). Therefore, Verma suggests that circuit designs be manufactured as part of the circuit design process and provides a method for design verification and Irissou further suggests that designs should be further validated by prototyping after performing software validation and provides a system by which to do so. Accordingly, it would have been obvious to one having skill in the art to combine the prior art references to arrive at the claimed invention, per the suggestions and motivations recited in the prior art references.
Regarding claim 18, the proposed combination discloses The non-transitory computer readable medium of claim 17, as stated previously. The proposed combination in further view of Varambally discloses wherein the control interface is operable to selectively bypass the feedback representation. The multiplexer device may select the random stimulus or alternatively the ML-based stimulus which is part of the feedback representation. By using the random stimulus in the training phase, the multiplexer effectively bypasses the ML based stimulus which steps from the feedback loop ((Varambally, Col 2, ¶4) "The above figure shows the environment used to evaluate the model. The Supervised Learning is accomplished using an ANN model. Random stimulus is used in the training phase and a multiplexer is used to switch to the ML based inputs received through feedback from the model during the verification test phase.")
Regarding claim 19, the proposed combination discloses The non-transitory computer readable medium of claim 11, as stated previously. The proposed combination in further view of Varambally discloses (except the limitations surrounded by brackets ([[..]])) [[wherein the instructions further comprise instructions for including]] the feedback representation [[in a request for manufacture]] of the circuit representation. The circuit design (representation) is described as comprising a feedback representation (as the feedback loop).
The proposed combination in further view of Varambally does not disclose; however the proposed combination in view of Irissou discloses wherein the instructions further comprise instructions for including…in a request for manufacture A request is made via a foundry interface tool such that the foundry implements circuit designs as prototypes ((Irissou, ¶234) "Upon determining that the pre-determined number of designs are received from one or more of the user accounts 1 through N, the shuttle manager tool 404 sends a request via the foundry interface tool 406 and the computer network 110 to the fabrication computing devices 1 and 2 of the one or more foundry entities for implementing the pre-determined number of designs on the shuttle to manufacture prototypes of SoCs based on the designs. For example, the shuttle manager tool 404 sends the request via the foundry interface tool 406, and the fabrication entity account 1 to the fabrication computing device 1 that is operated by a first foundry entity. As another example, the shuttle manager tool 404 sends the request via the foundry interface tool 406, and the fabrication entity account 2 to the fabrication computing device 2 that is operated by a second foundry entity.")
Irissou is analogous art because it pertains to the same field of endeavor of improvements in electronic design automation technologies. It would have been obvious to one of ordinary skill to which said subject matter pertains at the time the invention was filed to have combined the art of the proposed combination in further view of the teachings of Irissou because some teaching, suggestion, or motivation in the prior art references would have led one having skill in the art to do so in order to arrive at the claimed invention. Verma suggests that part of the design flow of designing and fabricating electronic systems includes a step at a foundry that manufactures the designed electronic system but does not provide particular details of this step ((Verma, ¶2) "Designing and fabricating electronic systems typically involves many steps, known as a design flow. The particular steps of a design flow often are dependent upon the type of electronic system being designed, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system."). Rather, Verma emphasizes improvements on the design verification process of design and manufacture of electronic systems. Irissou discloses a comprehensive system and method for engineering circuit design development which includes specialized software tools to enable design fabrication. Irissou particularly points out that once an IC design is complete and validated by computer modeling that the designer should further validate the design by fabricating a prototype of the IC on a semiconductor wafer ((Irissou, ¶5) "Once a design for an integrated circuit (IC) is complete and validated by computer modeling using various software tools, the designer should validate the design by fabricating a prototype of the IC on a semiconductor wafer. "). Irissou further describes that a prototype can be generated by providing a request to a foundry to manufacture the prototype of the provided design (Irissou, ¶234). Therefore, Verma suggests that circuit designs be manufactured as part of the circuit design process and provides a method for design verification and Irissou further suggests that designs should be further validated by prototyping after performing software validation and provides a system by which to do so. Accordingly, it would have been obvious to one having skill in the art to combine the prior art references to arrive at the claimed invention, per the suggestions and motivations recited in the prior art references.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gogri et al (Gogri, S., Hu, J., Tyagi, A. Quinn, M., Ramachandran, S., Batool, F., and Jagadeesh, A., “Machine Learning-Guided Stimulus Generation for Functional Verification”, March 2020, Proceedings of the Design and Verification Conference, pp 2-5) discloses a machine-learning guided stimulus generation that attains verification coverage with reduced simulations.
Barros et al (Barros, J., Schulz, V., and Lettnin, D., “An Adaptive Closed-loop verification Approach in UVM-SystemC for AMS Circuits”, 2018, 31st Symposium on Integrated Circuits and Systems Design (SBCCI), pp 1-6) discloses an adaptive approach for the functional verification of AMS circuits using a feedback connection between the scoreboard and driver.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.G.L./Examiner, Art Unit 2187
/EMERSON C PUENTE/Supervisory Patent Examiner, Art Unit 2187
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