DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed June 22nd, 2022. Claims 1-56 are pending, of which claims 1-56 are currently rejected.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/29/2022 is in compliance with the provisions of 37 CFR 1.97. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Objections
Claim 26 is objected to:
Claim 26 lines 1-2 “the first data type” should be “the first datatype” in order to avoid confusion.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation “a first datatype” on line 1-2. It is unclear if this mention of a first datatype is the same as the first datatype as recited in claim 14 on line 3. For examination purposes, the first datatype as recited in claim 19 lines 1-2 will be construed to be “the first datatype” of claim 14 line 3. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-56 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Claim language recites conversion from a first datatype to a second datatype for a matrix multiply-accumulate operation.
Below are the limitations of claim 1 that recite an abstract idea under mathematical concepts:
to transform one or more operands of a first datatype to one or more operands of a second datatype and causing a matrix multiply-accumulate (MMA) operation to be performed on the one or more operands of the second datatype.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include:
A processor
One or more circuits
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer, as to the arithmetic logic unit and the processor. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 1 does not amount to significantly more than the abstract idea.
Claim 1 is not eligible.
Regarding claim 2, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 2 that recite an abstract idea under mathematical concepts:
wherein the one or more operands of the first datatype are to be transformed
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there additional elements not reciting mathematical concepts are:
by causing a first portion of the one or more operands of the first datatype to be stored as the one or more operands of the second datatype and a second portion of the one or more operands of the first datatype to be stored as one or more other operands of the second datatype.
There is an insignificant extra-solution activity that must be made of note:
to be stored as the one or more operands of the second datatype
to be stored as one or more other operands of the second datatype.
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer, as to the arithmetic logic unit and the processor. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 1 does not amount to significantly more than the abstract idea.
In regards to the insignificant extra-solution activity found in this limitation “to be stored as one or more operands of the second datatype”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “to be stored as one or more other operands of the second datatype”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
Claim 2 is not eligible.
Regarding claim 3, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 3 that recite an abstract idea under mathematical concepts:
wherein the MMA operation…to perform one or more mathematical operations specific to the second datatype.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, additional elements not reciting mathematical concepts are:
if performed by the one or more circuits.
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer, as to the arithmetic logic unit and the processor. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 1 does not amount to significantly more than the abstract idea.
Claim 3 is not eligible.
Regarding claim 4, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 4 that recite an abstract idea under mathematical concepts:
wherein the one or more operands of a first datatype comprise one or more first sets of data and the one or more operands of the second datatype comprise one or more second sets of data transformed from the one or more first sets of data by combining one or more subsets of the one or more first sets of data.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 1.
Claim 4 is not eligible.
Regarding claim 5, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 5 that recite an abstract idea under mathematical concepts:
wherein the MMA operation…is to generate one or more outputs of the first datatype.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, additional elements not reciting mathematical concepts are:
if performed by the one or more circuits.
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer, as to the arithmetic logic unit and the processor. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 5 does not amount to significantly more than the abstract idea.
Claim 5 is not eligible.
Regarding claim 6, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 6 that recite an abstract idea under mathematical concepts:
to transform the one or more operands of the first datatype by causing one or more first bits to be stored as a first set of bits in the one or more operands of the second datatype, one or more second bits to be stored as a second set of bits in the one or more operands of the second datatype, and one or more third bits to be stored as a third set of bits in the one or more operands of the second datatype.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, the additional elements not reciting mathematical concepts are:
by causing one or more first bits to be stored as a first set of bits in the one or more operands of the second datatype
one or more second bits to be stored as a second set of bits in the one or more operands of the second datatype
one or more third bits to be stored as a third set of bits in the one or more operands of the second datatype
There is an insignificant extra-solution activity that must be made of note:
by causing one or more first bits to be stored as a first set of bits in the one or more operands of the second datatype
one or more second bits to be stored as a second set of bits in the one or more operands of the second datatype
one or more third bits to be stored as a third set of bits in the one or more operands of the second datatype
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer, as to the arithmetic logic unit and the processor. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 1 does not amount to significantly more than the abstract idea.
In regards to the insignificant extra-solution activity found in this limitation “by causing one or more first bits to be stored as a first set of bits in the one or more operands of the second datatype”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “one or more second bits to be stored as a second set of bits in the one or more operands of the second datatype”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “one or more third bits to be stored as a second set of bits in the one or more operands of the second datatype”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
Claim 6 is not eligible.
Regarding claim 7, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Claim language recites conversion from a first datatype to a second datatype for a matrix multiply-accumulate operation.
Below are the limitations of claim 7 that recite an abstract idea under mathematical concepts:
to convert one or more operands of a first datatype to one or more operands of a second datatype and causing a matrix multiply-accumulate (MMA) operation to be performed on the one or more operands of the second datatype.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include:
A system
One or more processors
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer, as to the arithmetic logic unit and the processor. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 1 does not amount to significantly more than the abstract idea.
Claim 7 is not eligible.
Regarding claim 8, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Claim language recites conversion from a first datatype to a second datatype for a matrix multiply-accumulate operation.
Below are the limitations of claim 8 that recite an abstract idea under mathematical concepts:
wherein the one or more operands of the first datatype comprise one or more sets of data with a set of dimensions and the MMA operation, if performed by the one or more processors, is to generate one or more other sets of data of the first datatype with a subset of the set of dimensions.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 7.
Claim 8 is not eligible.
Regarding claim 9, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 9 that recite an abstract idea under mathematical concepts:
wherein the one or more operands of the first datatype comprise one or more first sets of data with a set of dimensions and the one or more operands of the second datatype comprise one or more second sets of data each with a subset of the set of dimensions, the one or more second sets of data to be used by the MMA operation.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 7.
Claim 9 is not eligible.
Regarding claim 10, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 10 that recite an abstract idea under mathematical concepts:
wherein causing the MMA operation to be performed on the one or more operands of the second datatype causes the one or more processors to generate one or more sets of data of the first datatype.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 7.
Claim 10 is not eligible.
Regarding claim 11, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 11 that recite an abstract idea under mathematical concepts:
to convert the one or more operands of the first datatype by causing one or more first bits to be stored as a first set of bits in the one or more operands of the second datatype, one or more second bits to be stored as a second set of bits in the one or more operands of the second datatype, and one or more third bits to be stored as a third set of bits in the one or more operands of the second datatype.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, the additional elements not reciting mathematical concepts are:
by causing one or more first bits to be stored as a first set of bits in the one or more operands of the second datatype
one or more second bits to be stored as a second set of bits in the one or more operands of the second datatype
one or more third bits to be stored as a third set of bits in the one or more operands of the second datatype
There is an insignificant extra-solution activity that must be made of note:
by causing one or more first bits to be stored as a first set of bits in the one or more operands of the second datatype
one or more second bits to be stored as a second set of bits in the one or more operands of the second datatype
one or more third bits to be stored as a third set of bits in the one or more operands of the second datatype
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer, as to the arithmetic logic unit and the processor. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 11 does not amount to significantly more than the abstract idea.
In regards to the insignificant extra-solution activity found in this limitation “by causing one or more first bits to be stored as a first set of bits in the one or more operands of the second datatype”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “one or more second bits to be stored as a second set of bits in the one or more operands of the second datatype”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “one or more third bits to be stored as a second set of bits in the one or more operands of the second datatype”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
Claim 11 is not eligible.
Regarding claim 12, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 12 that recite an abstract idea under mathematical concepts:
to convert the one or more operands of the first datatype by calculating one or more differences between each of the one or more operands of the first data type and each of the one or more operands of the second datatype and storing the one or more differences in another one or more operands of the second datatype.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, the additional elements not reciting mathematical concepts are:
and storing the one or more differences in another one or more operands of the second datatype.
There is an insignificant extra-solution activity that must be made of note:
and storing the one or more differences in another one or more operands of the second datatype.
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer, as to the arithmetic logic unit and the processor. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 12 does not amount to significantly more than the abstract idea.
In regards to the insignificant extra-solution activity found in this limitation “and storing the one or more differences in another one or more operands of the second datatype”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
Claim 12 is not eligible.
Regarding claim 13, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 13 that recite an abstract idea under mathematical concepts:
wherein the MMA operation has a shape and the one or more operands of the second datatype comprise one or more sets of data to satisfy the shape.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 7.
Claim 13 is not eligible.
Claims 14-18 recite a machine-readable medium upon which instructions are stored for performing the method practiced by the apparatus of claims 7, 11, and 12 respectively.
Claim 14-20 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to non-statutory subject matter. During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, 367 F.3d 1359, 1369, 70 U.S.P.Q.2d 1827, 1834 (Fed. Cir. 2004). Independent claim 20 recites a “machine-readable medium”, while the instant specification at paragraph [0343] defines a “computer- readable storage medium” as one that is non-transitory. It is unclear if the medium as recited in the claim is the same as the medium as recited in the instant specification. Since there is no explicit disavowal of transitory signals per se, the “machine-readable medium” as claimed in claims 14-20 falls under signals per se. Signals per se is not a “process,” a “machine,” a “manufacture,” or a “composition of matter” as defined in 35 U.S.C. § 101. At Step 2A, claims 14-20 are not directed to a statutory category of invention. Therefore, claim 14-20 are not eligible.
Claims 21-24 are directed towards the method practiced by the apparatus of claims 1, 6, and 2 respectively. Claims 21-24 are directed to the statutory category of method, thus also satisfying Step 1. As explained above, the additional elements at best are the equivalent of merely adding the words “apply it” to the judicial exception.
As disclosed in the claim in light of the specification, described are mere instructions to apply an exception, invoking the computing elements merely as a tool to perform an existing process. See MPEP 2105.06(f). Mere instructions to apply an exception cannot provide an inventive concept. The claims are not eligible.
Regarding claim 23, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 23 that recite an abstract idea under mathematical concepts:
further comprising transforming the one or more operands of the first datatype by calculating one or more differences between each of the one or more operands of the first datatype and each of the one or more operands of the second data type and storing the one or more differences in another one or more operands of the second datatype to be usable as input to the MMA operation.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, the additional elements not reciting mathematical concepts are:
storing the one or more differences in another one or more operands of the second datatype to be usable as input to the MMA operation.
There is an insignificant extra-solution activity that must be made of note:
storing the one or more differences in another one or more operands of the second datatype to be usable as input to the MMA operation.
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer, as to the arithmetic logic unit and the processor. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 12 does not amount to significantly more than the abstract idea.
In regards to the insignificant extra-solution activity found in this limitation “storing the one or more differences in another one or more operands of the second datatype to be usable as input to the MMA operation”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
Claim 23 is not eligible.
Claim 25 is directed towards the method practiced by the instructions stored on the computer readable medium of claim 20. Claims 25 is directed to the statutory category of method, thus also satisfying Step 1. As explained above, the additional elements at best are the equivalent of merely adding the words “apply it” to the judicial exception.
As disclosed in the claim in light of the specification, described are mere instructions to apply an exception, invoking the computing elements merely as a tool to perform an existing process. See MPEP 2105.06(f). Mere instructions to apply an exception cannot provide an inventive concept. The claims are not eligible.
Regarding claim 26, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 20 that recite an abstract idea under mathematical concepts:
further comprising generating one or more outputs of the first data type by the MMA operation based, at least in part, on the one or more operands of the second datatype.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 21.
Claim 26 is not eligible.
Regarding claim 27, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 27 that recite an abstract idea under mathematical concepts:
wherein the MMA operation comprises one or more multiplication operations and one or more accumulation operations to generate one or more data sets of the first datatype based, at least in part, on the one or more operands of the second datatype.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 21.
Claim 27 is not eligible.
Regarding claim 28, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Claim language recites conversion from a first datatype to a second datatype for a matrix multiply-accumulate operation.
Below are the limitations of claim 28 that recite an abstract idea under mathematical concepts:
to convert one or more thirty-two bit floating point (FP32) operands to one or more tensorflow32 (TF32) operands and cause a matrix-multiply-accumulate (MMA) operation to be performed on the one or more TF32 operands.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include:
A processor
One or more circuits
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer, as to the arithmetic logic unit and the processor. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 28 does not amount to significantly more than the abstract idea.
Claim 28 is not eligible.
Regarding claim 29, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 29 that recite an abstract idea under mathematical concepts:
wherein each of the one or more FP32 operands comprises a one-bit sign, an eight-bit exponent, and a twenty three-bit mantissa, and the one or more circuits are to convert the one or more FP32 operands by copying, for each of the one or more FP32 operands, the one-bit sign, the eight-bit exponent, and a first ten bits of the twenty-three bit mantissa to at least one of the one or more TF32 operands.
All limitations as indicated describe “mathematical concepts” and “mental steps”. Copying portions of the number into the TF32 operands can be done mentally or with the aid of pen and paper.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 28.
Claim 29 is not eligible.
Regarding claim 30, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 30 that recite an abstract idea under mathematical concepts:
to convert the one or more FP32 operands to the one or more TF32 operands by computing one or more differences between the one or more FP32 operands and one or more other data values (mathematical concepts)
and copying the one or more differences to the one or more TF32 operands (mental steps)
All limitations as indicated describe “mathematical concepts” and “mental steps”. Copying the one or more differences to each of the TF32 operands can be done mentally or with the aid of pen and paper.
There are no further additional elements beyond those recited in claim 28.
Claim 30 is not eligible.
Regarding claim 31, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 31 that recite an abstract idea under mathematical concepts:
wherein the MMA operation is an ml 6n8k4 MMA instruction which, if executed, causes the one or more circuits to compute one or more sets of FP32 data.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 28.
Claim 31 is not eligible.
Regarding claim 32, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 32 that recite an abstract idea under mathematical concepts:
wherein the one or more FP32 operands comprise a first set of data with a first width and a first height and a second set of data with a second width and a second height and the one or more TF32 operands comprise a third set of data with at least the first height and a fourth set of data with at least the second width and the MMA operation, if performed, causes the one or more circuits to generate a fifth set of data with at least the first height and the second width.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 28.
Claim 32 is not eligible.
Regarding claim 33, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 33 that recite an abstract idea under mathematical concepts:
wherein the one or more TF32 operands comprise a first set of data computed based, at least in part, on at least one mantissa of the one or more FP32 operands and a second set of data computed based, at least in part, on one or more differences between the one or more FP32 operands and one or more data values.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 28.
Claim 33 is not eligible.
Regarding claim 34, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 34 that recite an abstract idea under mathematical concepts:
wherein the MMA operation comprises a shape and the one or more TF32 operands comprise one or more dimensions to satisfy the shape.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 28.
Claim 34 is not eligible.
Claims 35, 38, 39, 40, 42 are directed towards the system of processors of claims 28, 33, 29, 32, and 31 respectively. Claims 35, 38, 39, 40 are directed to the statutory category of machine, thus also satisfying Step 1. As explained above, the additional elements at best are the equivalent of merely adding the words “apply it” to the judicial exception.
As disclosed in the claim in light of the specification, described are mere instructions to apply an exception, invoking the computing elements merely as a tool to perform an existing process. See MPEP 2105.06(f). Mere instructions to apply an exception cannot provide an inventive concept. The claims are not eligible.
Regarding claim 36, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 36 that recite an abstract idea under mathematical concepts:
wherein the MMA operation comprises a shape and the shape indicates one or more dimensions of the one or more TF32 operands.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 35.
Claim 36 is not eligible.
Regarding claim 37, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 37 that recite an abstract idea under mathematical concepts:
wherein the MMA operation is a ml6n8k4 TF32 MMA instruction that, if executed, causes the one or more processors to compute one or more FP32 data values based, at least in part, on the one or more TF32 operands.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 35.
Claim 37 is not eligible.
Regarding claim 41, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 41 that recite an abstract idea under mathematical concepts:
wherein the one or more processors are the convert the one or more FP32 operands by decomposing each of the one or more FP32 operands into a high part and a low part and copying the high part and the low part into sets of data to be combined into the one or more TF32 operands.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no additional elements beyond those recited in claim 35.
Claim 41 is not eligible.
Claims 43-49 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to non-statutory subject matter. During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, 367 F.3d 1359, 1369, 70 U.S.P.Q.2d 1827, 1834 (Fed. Cir. 2004). Claims 43-49 recites a machine-readable medium, while the instant specification at paragraph [0343] defines a “computer-readable storage medium” as one that is non-transitory. It is unclear if the medium as recited in the claim is the same as the medium as recited in the instant specification. Since there is no explicit disavowal of transitory signals per se, the “computer readable medium” as claimed in claims 43-49 falls under signals per se. Signals per se is not a “process,” a “machine,” a “manufacture,” or a “composition of matter” as defined in 35 U.S.C. § 101. At Step 2A, claims 43-49 is not directed to a statutory category of invention. Therefore, claims 43-49 are not eligible.
Claims 50-51 and 53-55 are directed towards the method practiced by the apparatus of claims 35, 41, 40, 36, and 42 respectively. Claims 50-51 and 53-55 are directed to the statutory category of method, thus also satisfying Step 1. Moreover, at Step 2A none of the additional elements regarding the generic computer components are more than high level generic computer components that amount to mere instructions to apply the abstract idea on a generic computer. As explained above, the additional elements at best are the equivalent of merely adding the words “apply it” to the judicial exception.
As disclosed in the claim in light of the specification, described are mere instructions to apply an exception, invoking the computing elements merely as a tool to perform an existing process. See MPEP 2105.06(f). Mere instructions to apply an exception cannot provide an inventive concept. The claims are not eligible.
Regarding claim 52, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 52 that recite an abstract idea under mathematical concepts:
converting the one or more FP32 operands by copying a one-bit sign, an eight-bit exponent, and a first ten bits of a twenty three-bit mantissa of at least one of the one or more FP32 operands to at least one of the one or more TF32 operands
and calculating one or more differences between the at least one of the one or more FP32 operands and one or more data values
copying the one or more differences to the at least one of the one or more TF32 operands (mental steps)
All limitations as indicated describe “mathematical concepts” or “mental steps”. Copying to TF32 operands can be done mentally or with the aid of pen and paper.
At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include:
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer, as to the arithmetic logic unit and the processor. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 28 does not amount to significantly more than the abstract idea.
Claim 52 is not eligible.
Regarding claim 56, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 56 that recite an abstract idea under mathematical concepts:
wherein causing the MMA operation to be performed causes one or more sets of FP32 data to be generated based, at least in part, on the one or more TF32 operands and calculating one or more differences between the at least one of the one or more FP32 operands and one or more data values.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no further additional elements beyond those recited in claim 50.
Claim 56 is not eligible.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 9-11, 14-16, 18, 21-22, 24, 26-29, 35, 39, 43, 45, 50, 52, 56 are rejected under 35 U.S.C. 102(a)(1) as being anticipated NVIDIA, ("NVIDIA A100 Tensor Core GPU Architecture", 2020) (hereinafter “NVIDIA’1”).
Regarding claim 1, NVIDIA’1 teaches:
A processor comprising:
one or more circuits (NVIDIA’1: Pg. 26 Lines 32-37 conversion and MMA operations occur on NVIDIA Ampere architecture using the plurality of tensor cores, the tensor cores having circuitries within for carrying out operations) to transform one or more operands of a first datatype to one or more operands of a second datatype (Pg. 27 Fig. 9 transforming of datatypes from FP32 first datatype to TF32 second datatype) and causing a matrix multiply-accumulate (MMA) operation to be performed on the one or more operands of the second datatype (NVIDIA’1: Pg. 27 Fig. 9 matrix multiply operation occurring using TF32 operands and accumulation in FP32).
Regarding claim 2, NVIDIA’1 teaches:
The processor of claim 1, wherein the one or more operands of the first datatype are to be transformed by causing a first portion of the one or more operands of the first datatype to be stored as the one or more operands of the second datatype (NVIDIA’1: Pg. 27 Fig. 9 first portion, first FP32 matrix blue box are being converted and stored as second datatype operands for MMA operation) and a second portion of the one or more operands of the first datatype to be stored as one or more other operands of the second datatype (NVIDIA’1: Pg. 27 Fig. 9 second portion (red box) of FP32 operands are converted to be second datatype operands (for MMA operation to occur these must be stored as other operands different from the first portion operands)).
Regarding claim 3, NVIDIA’1 teaches:
The processor of claim 1, wherein the MMA operation, if performed by the one or more circuits, causes the one or more circuits to perform one or more mathematical operations specific to the second datatype (NVIDIA’1: Pg. 27 MMA operation right figure shows matrix multiply operation occurring with FP32 operands i.e., second datatype).
Regarding claim 5, NVIDIA’1 teaches:
The processor of claim 1, wherein the MMA operation, if performed by the one or more circuits, is to generate one or more outputs of the first datatype (NVIDIA’1: Pg. 27 Fig. 9 FP32 output matrix, first datatype).
Regarding claim 6, NVIDIA’1 teaches:
The processor of claim 1, wherein the one or more circuits are to transform the one or more operands of the first datatype by causing one or more first bits to be stored as a first set of bits in the one or more operands of the second datatype (NVIDIA’1: Pg. 27 Fig. 9 first set of bits are sign bits, which are taken from FP32 datatype and kept for TF32 operands), one or more second bits to be stored as a second set of bits in the one or more operands of the second datatype (NVIDIA’1: Pg. 27 Fig. 9 second set of bits are exponent bits which are taken from FP32 datatype and kept for TF32 operands), and one or more third bits to be stored as a third set of bits in the one or more operands of the second datatype (NVIDIA’1: Pg. 27 Fig. 9 third set of bits of bits are mantissa bits, which are taken from FP32 datatype the first 10 bits from the 23 mantissa bits and kept for TF32 operands).
Claims 7, and 10-11 recite the system for the processors as recited in claims 1, and 5-6 respectively and are therefore rejected for the same reasons therein. NVIDIA’1 additionally teaches MMA operations occurring on NVIDIA Ampere architecture i.e., the system using the plurality of tensor cores i.e., the processors, the tensor cores having circuitries within for carrying out operations (NVIDIA’1: Pg. 26 Lines 32-37).
Claims 14, 15, 16, and 18 recite the machine-readable medium storing instructions for the processors as recited in claims 1, 2, 6, and 5 respectively. NVIDIA’1 additionally teaches a memory from which instructions are fetched in order to perform operations on GPUs, including MMA and conversion operations (NVIDIA’1: Pg. 40 Data Fetch Improvements Paragraph).
Claims 21, 22, 24, and 26 recite the method of claims 1, 6, 2, and 5 respectively and are therefore rejected for same reasons therein.
Regarding claim 27, NVIDIA’1 teaches:
The method of claim 21, wherein the MMA operation comprises one or more multiplication operations and one or more accumulation operations to generate one or more data sets of the first datatype based, at least in part, on the one or more operands of the second datatype (NVIDIA’1: Pg. 27 Fig. 9 matrix multiplication operation with TF32 operands followed by accumulation in FP32 format, in order to obtain final result in FP32 format i.e., first datatype).
Regarding claim 28, NVIDIA’1 teaches:
A processor comprising:
one or more circuits (NVIDIA’1: Pg. 26 Lines 32-37 conversion and MMA operations occur on NVIDIA Ampere architecture using the plurality of tensor cores, the tensor cores having circuitries within for carrying out operations) to convert one or more thirty-two bit floating point (FP32) operands to one or more tensorflow32 (TF32) operands (Pg. 27 Fig. 9 transforming of datatypes from FP32 first datatype to TF32 second datatype) and cause a matrix-multiply-accumulate (MMA) operation to be performed on the one or more TF32 operands (NVIDIA’1: Pg. 27 Fig. 9 matrix multiply operation occurring using TF32 operands and accumulation in FP32).
Regarding claim 29, NVIDIA’1 teaches:
The processor of claim 28, wherein each of the one or more FP32 operands comprises a one-bit sign, an eight-bit exponent, and a twenty three-bit mantissa (NVIDIA’1: Pg. 27 Fig. 9 FP32 has sign bit, eight bit exponent, and 23 bit mantissa), and the one or more circuits are to convert the one or more FP32 operands by copying, for each of the one or more FP32 operands, the one-bit sign, the eight-bit exponent, and a first ten bits of the twenty-three bit mantissa to at least one of the one or more TF32 operands (NVIDIA’1: Pg. 27 conversion to TF32 has a sign bit, eight bit exponent, and 10 bits taken from 23 bit mantissa).
Claims 35 and 39 recite the system for the processors as recited in claims 28 and 29 respectively and are therefore rejected for the same reasons therein. NVIDIA’1 additionally teaches MMA operations occurring on NVIDIA Ampere architecture i.e., the system using the plurality of tensor cores i.e., the processors, the tensor cores having circuitries within for carrying out operations (NVIDIA’1: Pg. 26 Lines 32-37).
Claims 43 and 45 recite the machine-readable medium storing instructions for the processors as recited in claims 28 and 29 respectively. NVIDIA’1 additionally teaches a memory from which instructions are fetched in order to perform operations on GPUs, including MMA and conversion operations (NVIDIA’1: Pg. 40 Data Fetch Improvements Paragraph).
Claims 50 and 52 recite the method as practiced by the processor of claims 28 and 29 and are therefore rejected for the same reasons therein.
Regarding claim 56, NVIDIA’1 teaches:
The method of claim 50, wherein causing the MMA operation to be performed causes one or more sets of FP32 data to be generated based, at least in part, on the one or more TF32 operands (NVIDIA’1: Pg. 27 computation of FP32 output values using TF32 operands).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13, 20, 25, 31, 34, 36-37, 42, 47-48, and 54-55 are rejected under 35 U.S.C. 103 as being unpatentable over NVIDIA’1 in view of NVIDIA ("Parallel Thread Execution ISA v7.2", 2020) (hereinafter “NVIDIA’2”).
Regarding claim 13, while NVIDIA’1 teaches the system of claim 7, NVIDIA’7 does not explicitly teach the MMA operation having a shape and the one or more operands of the second datatype comprising one or more sets of data to satisfy the shape.
However, NVIDIA’2 teaches the MMA operation being an m16n8k4 MMA instruction with 16m8k4 shape, and sets of TF32 operands (of the second datatype) being determined in order to satisfy the specific shape (Pg. 276-279 Section 9.7.13.4.6).
It would be obvious to combine the specific MMA shape as taught by NVIDIA’1 with the system as taught by NVIDIA’2 as both teachings are directed towards MMA computations on NVIDIA GPU Cores. One with ordinary skill in the art would be motivated to combine the teachings because the parallel thread execution (PTX) can be used across all NVIDIA GPUs in order to enable NVIDIA GPUs to be used as programmable parallel computers (NVIDIA’2: Pg. 1 Section 1.1 third paragraph).
Regarding claim 20, while NVIDIA’1 teaches the machine-readable medium of claim 14, NVIDIA’1 does not explicitly teach the MMA operation having a shape based on a set of dimensions of the one more operands of the second datatype and the MMA operation being specific to the second datatype.
However, NVIDIA’2 teaches:
wherein the MMA operation has a shape determined based, at least in part, on a set of dimensions of the one or more operands of the second datatype and the MMA operation is specific to the second datatype (NVIDIA’2: Pg. 276-279 Section 9.7.13.4.6. MMA operation is an m16n8k4 MMA instruction mma.m16n8k4 with 16m8k4 shape, having sets of TF32 operands dimensions specific to the shape and MMA operation carried out in TF32 format, followed by accumulation in FP32 format).
The motivation to combine with respect to claim 13 applies equally to claim 20.
Claim 25 teaches the method practiced by the instructions stored in the machine-readable medium of claim 20 and is therefore rejected for the same reasons therein.
Regarding claim 31, while NVIDIA’1 teaches the processor of claim 28, NVIDIA’1 does not explicitly teach the MMA operation being an m16n8k4 MMA instruction, and causing the one or more circuits to compute one or more sets of FP32 data.
However, NVIDIA’2 teaches:
wherein the MMA operation is an m16n8k4 MMA instruction, which, if executed, causes the one or more circuits to compute one or more sets of FP32 data (NVIDIA’2: Pg. 276-279 Section 9.7.13.4.6. MMA operation is an m16n8k4 MMA instruction mma.m16n8k4 with 16m8k4 shape, having sets of TF32 operands dimensions specific to the shape and MMA operation carried out in TF32 format, followed by accumulation of various sets of FP32 format).
The motivation to combine with regards to claim 13 applies equally to claim 31.
Regarding claim 34, while NVIDIA’1 teaches the processor of claim 28, NVIDIA’1 does not explicitly teach the MMA operation comprising a shape and the one or more TF32 operands comprising dimensions to satisfy the shape.
However, NVIDIA’2 teaches:
The processor of claim 28, wherein the MMA operation comprises a shape and the one or more TF32 operands comprise one or more dimensions to satisfy the shape (NVIDIA’2: Pg. 276-279 Section 9.7.13.4.6. MMA operation is an m16n8k4 MMA instruction mma.m16n8k4 with 16m8k4 shape, having sets of TF32 operands dimensions specific to the shape and MMA operation carried out in TF32 format).
The motivation to combine with respect to claim 13 applies equally to claim 34.
Regarding claim 36, while NVIDIA’1 teaches the system of claim 35, NVIDIA’1 does not explicitly teach the MMA operation comprising a shape and the shape indicating one or more dimensions of the one or more TF32 operands.
However, NVIDIA’2 teaches:
The system of claim 25, wherein the MMA operation comprises a shape and the shape indicates one or more dimensions of the one or more TF32 operands (NVIDIA’2: Pg. 276-279 Section 9.7.13.4.6. MMA operation is an m16n8k4 MMA instruction mma.m16n8k4 with 16m8k4 shape, having sets of TF32 operands dimensions specific to the shape and MMA operation carried out in TF32 format).
The motivation to combine with respect to claim 13 applies equally to claim 36.
Regarding claim 37, while NVIDIA’1 teaches the system of claim 35 as well as carrying out an MMA operation of FP32 values based on TF32 operands (Pg. 27 FP32 inputs are converted to TF32 operands and MMA operation is carried out to output FP32 values carried out GPUs, i.e., processors), NVIDIA’1 does not explicitly teach the MMA instruction being a m16n8k4 TF32 MMA instruction.
However, NVIDIA’2 teaches:
wherein the MMA operation is a m16n8k4 TF32 MMA instruction (NVIDIA’2: Pg. 276-279 Section 9.7.13.4.6. MMA operation is an m16n8k4 MMA instruction mma.m16n8k4 with 16m8k4 shape).
The motivation to combine with respect to claim 13 applies equally to claim 37.
Regarding claim 42, while NVIDIA’1 teaches the system of claim 35, NVIDIA’1 does not explicitly teach an m16n8k4 TF32 MMA instruction.
However, NVIDIA’2 teaches:
wherein the MMA operation is to be performed in response to an m16n8k4 TF32 MMA instruction (NVIDIA’2: Pg. 276-279 Section 9.7.13.4.6. MMA operation is an m16n8k4 MMA instruction mma.m16n8k4 with 16m8k4 shape).
The motivation to combine with respect to claim 13 applies equally to claim 42.
Regarding claim 47, while NVIDIA’1 teaches the machine-readable medium of claim 43, NVIDIA’1 does not explicitly teach the MMA operation comprising a shape and the shape indicating dimensions of the one or more TF32 operands.
However, NVIDIA’2 teaches:
wherein the MMA operation comprises a shape and the shape indicates one or more dimensions of the one or more TF32 operands (NVIDIA’2: Pg. 276-279 Section 9.7.13.4.6. MMA operation is an m16n8k4 MMA instruction mma.m16n8k4 with 16m8k4 shape).
The motivation to combine with respect to claim 13 applies equally to claim 47.
Regarding claim 48, while NVIDIA’1 teaches the machine-readable medium of claim 43 and generating one or more sets of FP32 data (NVIDIA’1: Pg. 27 Fig. 9 output as FP32 format), NVIDIA’1 does not explicitly teach the MMA operation being an m16n8k4 MMA instruction.
However, NVIDIA’2 teaches:
wherein the MMA operation is an m16n8k4 MMA instruction (NVIDIA’2: Pg. 276-279 Section 9.7.13.4.6. MMA operation is an m16n8k4 MMA instruction mma.m16n8k4).
The motivation to combine with respect to claim 13 applies equally to claim 48.
Claims 54-55 recite the method practiced by the machine-readable medium as recited in claims 47-48, and are rejected for the same reasons therein.
Allowable Subject Matter
Claims 4, 8, 12, 17, 19, 23, 30, 32, 33, 38, 40, 41, 44, 46, 49, 51, and 53 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and rewritten to overcome the 101 rejections.
Applicant claims a processor wherein the processor as in claim 1 comprises:
one or more circuits to transform one or more operands of a first datatype to one or more operands of a second datatype and causing a matrix multiply-accumulate (MMA) operation to be performed on the one or more operands of the second datatype.
Wherein claim 4 is dependent on claim 1 further comprising:
The processor of claim 1, wherein the one or more operands of a first datatype comprise one or more first sets of data and the one or more operands of the second datatype comprise one or more second sets of data transformed from the one or more first sets of data by combining one or more subsets of the one or more first sets of data.
The specific reason for indication of allowable subject matter is the combination of subsets for conversion purposes. NVIDIA’1 in view of NVIDIA’2 discloses the claimed invention according to the claim mappings above. NVIDIA’1 in view of NVIDIA’2 does not explicitly disclose the combination of subsets of operands for conversion as claimed.
Claim 19, that recites the machine-readable medium with instructions for performing the instructions for the method performed by the apparatus of claim 4 is therefore also allowable.
Applicant claims a system wherein the system as in claim 7 comprises:
one or more processors to convert one or more operands of a first datatype to one or more operands of a second datatype and causing a matrix multiply-accumulate (MMA) operation to be performed on the one or more operands of the second datatype.
Wherein claim 8 is dependent on claim 7 further comprising:
The system of claim 7, wherein the one or more operands of the first datatype comprise one or more sets of data with a set of dimensions and the MMA operation, if performed by the one or more processors, is to generate one or more other sets of data of the first datatype with a subset of the set of dimensions.
The specific reason for indication of allowable subject matter is generating sets of data with a subset of the set of dimensions. NVIDIA’1 in view of NVIDIA’2 discloses the claimed invention according to the claim mappings above. NVIDIA’1 in view of NVIDIA’2 does not explicitly disclose generating sets of data with a subset of the set of dimensions as claimed.
Wherein claim 12 is dependent on claim 7 further comprising:
wherein the one or more processors are to convert the one or more operands of the first datatype by calculating one or more differences between each of the one or more operands of the first data type and each of the one or more operands of the second datatype and storing the one or more differences in another one or more operands of the second datatype.
The specific reason for indication of allowable subject matter is conversion by calculation of differences between the one or more operands and the storing of differences. NVIDIA’1 in view of NVIDIA’2 discloses the claimed invention according to the claim mappings above. NVIDIA’1 in view of NVIDIA’2 does not explicitly disclose conversion by calculation of differences between the one or more operands and the storing of differences.
Claim 17, that recites the machine-readable medium with instructions for performing the instructions for the method performed by the apparatus of claim 12 is therefore also allowable.
Claim 23, that recites the method performed by the apparatus of claim 12 is therefore also allowable.
Applicant claims a processor wherein the processor as in claim 28 comprises:
one or more circuits to convert one or more thirty-two bit floating point (FP32) operands to one or more tensorflow32 (TF32) operands and cause a matrix-multiply-accumulate (MMA) operation to be performed on the one or more TF32 operands.
Wherein claim 30 is dependent on claim 28 further comprising:
The processor of claim 28, wherein the one or more circuits are to convert the one or more FP32 operands to the one or more TF32 operands by computing one or more differences between the one or more FP32 operands and one or more other data values and copying the one or more differences to the one or more TF32 operands.
The specific reason for indication of allowable subject matter is conversion by calculation of differences between the one or more operands and the storing of differences. NVIDIA’1 in view of NVIDIA’2 discloses the claimed invention according to the claim mappings above. NVIDIA’1 in view of NVIDIA’2 does not explicitly disclose conversion by calculation of differences between the one or more operands and the storing of differences.
Claim 46, that recites the machine-readable medium with instructions for performing the instructions for the method performed by the apparatus of claim 30 is therefore also allowable.
Wherein claim 32 is dependent on claim 28 further comprising:
wherein the one or more FP32 operands comprise a first set of data with a first width and a first height and a second set of data with a second width and a second height and the one or more TF32 operands comprise a third set of data with at least the first height and a fourth set of data with at least the second width and the MMA operation, if performed, causes the one or more circuits to generate a fifth set of data with at least the first height and the second width.
The specific reason for indication of allowable subject matter is the specific output of the operation with the corresponding first height and second width. NVIDIA’1 in view of NVIDIA’2 discloses the claimed invention according to the claim mappings above. NVIDIA’1 in view of NVIDIA’2 does not explicitly disclose the specific output of the operation with the corresponding first height and second width.
Claim 40, that recites the system with the processors of claim 32 is therefore also allowable.
Claim 49, that recites the machine-readable medium with the instructions for the method performed by the processor of claim 32 is therefore also allowable.
Claim 53, that recites the method performed by the processor of claim 32 is therefore also allowable.
Wherein claim 33 is dependent on claim 28 further comprising:
wherein the one or more TF32 operands comprise a first set of data computed based, at least in part, on at least one mantissa of the one or more FP32 operands and a second set of data computed based, at least in part, on one or more differences between the one or more FP32 operands and one or more data values.
The specific reason for indication of allowable subject matter is the computation on the differences of the FP32 operands. NVIDIA’1 in view of NVIDIA’2 discloses the claimed invention according to the claim mappings above. NVIDIA’1 in view of NVIDIA’2 does not explicitly disclose the computation on the differences of the FP32 operands.
Claim 38, that recites the system of processors of claim 33, is therefore also allowable.
Applicant claims a system wherein the system as in claim 35 comprises:
one or more processors to convert one or more thirty-two bit floating point (FP32) operands to one or more tensorflow32 (TF32) operands and cause a matrix-multiply-accumulate (MMA) operation to be performed on the one or more TF32 operands.
Wherein claim 41 is dependent on claim 35 further comprising:
wherein the one or more processors are the convert the one or more FP32 operands by decomposing each of the one or more FP32 operands into a high part and a low part and copying the high part and the low part into sets of data to be combined into the one or more TF32 operands.
The specific reason for indication of allowable subject matter is the decomposing of the FP32 operands into a high and low part for combination into TF32 operands. NVIDIA’1 in view of NVIDIA’2 discloses the claimed invention according to the claim mappings above. NVIDIA’1 in view of NVIDIA’2 does not explicitly disclose the decomposing of the FP32 operands into a high and low part for combination into TF32 operands.
Claim 44, that recites the machine-readable medium having instructions to perform method performed by the system of claim 41, is therefore also allowable.
Claim 50, that recites the method performed by the system of claim 41, is therefore also allowable.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
J. Moreira et al., “A matrix math facility for Power ISATM processors”, 2021 teaches a family of matrix math instructions using the Power10 processor for accelerating computation-intensive kernels i.e., matrix multiplication.
A. Rodriguez et al., “Lower Numerical Precision Deep Learning Inference and Training”, 2018 teaches low bit precision training and inference, and inference using matrix multiplication on Intel Xeon Scalable platforms.
P. Kharya, “TensorFloat-32 in the A100 GPU Accelerates AI Training, HPC up to 20x”, 2020, teaches the new math mode TensorFloat-32 in NVIDIA A100 GPUs and how the TF32 format accelerates math-intensive computations.
G. Tagliavini et al., “A Transprecision Floating-Point Platform for Ultra-Low Power Computing”, 2017 teaches a software library for computations of various floating-point types and computations that take in various precisions.
Conclusion
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151