DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0081033 A1 to Toyoda et al. (hereinafter “Toyoda ‘033” – previously cited reference) in further view of US 2017/0077081 A1 to Toyoda (hereinafter “Toyoda ‘081” – previously cited reference).
Regarding claim 1, Toyoda ‘033 discloses a semiconductor device (semiconductor device; Fig. 1; paragraph [0077]) comprising:
a semiconductor base body of a first conductivity type (n-type substrate 1 and epitaxial layer 2; Fig. 1; paragraph [0078]);
a high-potential-side terminal connected to the semiconductor base body (VCC terminal electrically connected to substrate 1 and epitaxial layer 2; Fig. 1; paragraph [0086]);
a horizontal first control circuit element deposited at an upper part of the semiconductor base body (horizontal n-channel MOSFET 20 deposited at upper part of substrate 1 and epitaxial layer 2; Fig. 1; paragraphs [0077], [0080]-[0081]);
a first signal input terminal connected to a control electrode of the first control circuit element (gate electrode 27 of MOSFET 20 electrically connected to wiring layer which in part may provide input signals to gate electrode 27; Fig. 1; paragraphs [0079], [0081]);
a low-potential-side terminal connected to a first main electrode region of the first control circuit element (GND terminal connected to source electrode 22 of MOSFET 20; Fig. 1; paragraphs [0084]-[0085]);
an input-side diode connected in a forward direction between the first signal input terminal and the semiconductor base body (diode D2 disposed in circuit portion which receives input signals and arranged between wiring layer and substrate 1/epitaxial layer 2 as shown in Fig. 3; paragraphs [0079], [0081], [0090]); and
a vertical protective element connected between the semiconductor base body and the low-potential-side terminal (vertical diode D1 of protective element portion 30 and connected between GND terminal and substrate 1/epitaxial layer 2 as shown in Fig. 3; paragraphs [0076], [0086], [0090]-[0093]);
a horizontal second control circuit element deposited at an upper part of the semiconductor base body (second unit cell of horizontal n-channel MOSFET 20 deposited at upper part of substrate 1 and epitaxial layer 2; Figs. 1 & 15; paragraphs [0077], [0080]-[0081], [0122]);
a second signal input terminal connected to a control electrode of the second control circuit element (gate electrode 27 of second unit cell of MOSFET 20 electrically connected to wiring layer which in part may provide input signals to gate electrode 27; Fig. 1; paragraphs [0079], [0081]); and
a second input-side diode connected in a forward direction between the second signal input terminal and the high-potential-side terminal (second diode formed by second p-n junction between epitaxial layer 2 and diffusion region 24 and disposed in circuit portion which receives input signals and arranged between wiring layer and VCC terminal as shown in Fig. 3; paragraphs [0079], [0081], [0088], [0090]-[0091]), wherein cathodes of the input-side diode and the second input-side diode are commonly connected to the vertical protective element (cathodes of diodes formed by p-n junctions between layer 2 and region 24 are electrically connected to protective element portion 30; Fig. 3), an external signal which is different from an external signal input to the first signal input terminal is input to the second signal input terminal (wiring layer provides signals to terminals of first and second MOSFET unit cells 20; Figs. 1 & 15; paragraphs [0077], [0079]-[0082], [0122]), and the first control circuit element and the second control circuit element are MOS transistors (first and second MOSFET unit cells 20; paragraphs [0082], [0122]).
Toyoda ‘033 fails to disclose wherein an anode of the input-side diode is connected to the control electrode of the first control circuit element.
However, Toyoda ‘081 discloses wherein an anode of the input-side diode is connected to the control electrode of the first control circuit element (anode of diode 130 connected in forward direction between input to gate terminal VG of MOSFET 120 and substrate 101/semiconductor layer 102; Fig. 11; paragraphs [0006]-[0009]).
Toyoda ‘033 and Toyoda ‘081 are both considered to be analogous to the claimed invention because they are in the same field of IGBTs using diodes as protective elements. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Toyoda ‘033 to incorporate the teaching of Toyoda ‘081 in order to potentially provide protection against overvoltage, noise immunity and signal isolation, and controlled signal conditioning.
Claims 1-6, 13-15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Toyoda ‘033 in further view of US 2017/0237422 A1 to Akahane (hereinafter “Akahane” – previously cited reference).
Regarding claim 1, Toyoda ‘033 discloses a semiconductor device (semiconductor device; Fig. 1; paragraph [0077]) comprising:
a semiconductor base body of a first conductivity type (n-type substrate 1 and epitaxial layer 2; Fig. 1; paragraph [0078]);
a high-potential-side terminal connected to the semiconductor base body (VCC terminal electrically connected to substrate 1 and epitaxial layer 2; Fig. 1; paragraph [0086]);
a horizontal first control circuit element deposited at an upper part of the semiconductor base body (horizontal n-channel MOSFET 20 deposited at upper part of substrate 1 and epitaxial layer 2; Fig. 1; paragraphs [0077], [0080]-[0081]);
a first signal input terminal connected to a control electrode of the first control circuit element (gate electrode 27 of MOSFET 20 electrically connected to wiring layer which in part may provide input signals to gate electrode 27; Fig. 1; paragraphs [0079], [0081]);
a low-potential-side terminal connected to a first main electrode region of the first control circuit element (GND terminal connected to source electrode 22 of MOSFET 20; Fig. 1; paragraphs [0084]-[0085]);
an input-side diode connected in a forward direction between the first signal input terminal and the semiconductor base body (diode D2 disposed in circuit portion which receives input signals and arranged between wiring layer and substrate 1/epitaxial layer 2 as shown in Fig. 3; paragraphs [0079], [0081], [0090]); and
a vertical protective element connected between the semiconductor base body and the low-potential-side terminal (vertical diode D1 of protective element portion 30 and connected between GND terminal and substrate 1/epitaxial layer 2 as shown in Fig. 3; paragraphs [0076], [0086], [0090]-[0093]);
a horizontal second control circuit element deposited at an upper part of the semiconductor base body (second unit cell of horizontal n-channel MOSFET 20 deposited at upper part of substrate 1 and epitaxial layer 2; Figs. 1 & 15; paragraphs [0077], [0080]-[0081], [0122]);
a second signal input terminal connected to a control electrode of the second control circuit element (gate electrode 27 of second unit cell of MOSFET 20 electrically connected to wiring layer which in part may provide input signals to gate electrode 27; Fig. 1; paragraphs [0079], [0081]); and
a second input-side diode connected in a forward direction between the second signal input terminal and the high-potential-side terminal (second diode formed by second p-n junction between epitaxial layer 2 and diffusion region 24 and disposed in circuit portion which receives input signals and arranged between wiring layer and VCC terminal as shown in Fig. 3; paragraphs [0079], [0081], [0088], [0090]-[0091]), wherein cathodes of the input-side diode and the second input-side diode are commonly connected to the vertical protective element (cathodes of diodes formed by p-n junctions between layer 2 and region 24 are electrically connected to protective element portion 30; Fig. 3), an external signal which is different from an external signal input to the first signal input terminal is input to the second signal input terminal (wiring layer provides signals to terminals of first and second MOSFET unit cells 20; Figs. 1 & 15; paragraphs [0077], [0079]-[0082], [0122]), and the first control circuit element and the second control circuit element are MOS transistors (first and second MOSFET unit cells 20; paragraphs [0082], [0122]).
Toyoda ‘033 fails to disclose wherein an anode of the input-side diode is connected to the control electrode of the first control circuit element.
However, Akahane discloses wherein an anode of the input-side diode is connected to the control electrode of the first control circuit element (anode of diode 44 connected in forward direction between gate 16 of transistor 46 of input circuit 40 and an input terminal of driving circuit 100; Fig. 1; paragraphs [0049], [0061]).
Toyoda ‘033 and Akahane are both considered to be analogous to the claimed invention because they are in the same field of IGBTs using diodes as protective elements. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Toyoda ‘033 to incorporate the teaching of Akahane in order to potentially provide protection against overvoltage, noise immunity and signal isolation, and controlled signal conditioning.
Regarding claim 2, Toyoda ‘033 in view of Akahane teaches the semiconductor device of claim 1. Toyoda ‘033 further discloses further comprising an internal power supply circuit connected between a second main electrode region of the first control circuit element and the high-potential-side terminal (power source circuit 12 connected between drain electrode 23 and high potential-side n+-type diffusion region 13 connected to VCC terminal as shown in Fig. 3; paragraphs [0080], [0086]).
Regarding claim 3, Toyoda ‘033 in view of Akahane teaches the semiconductor device of claim 1. Toyoda ‘033 further discloses wherein the vertical protective element is a vertical protective diode connected in a reverse direction between the high-potential- side terminal and the low-potential-side terminal (vertical diode D1 of protective element portion 30 connected in reverse direction between VCC and GND terminals as shown in Fig. 3; paragraphs [0091]-[0094]).
Regarding claim 4, Toyoda ‘033 in view of Akahane teaches the semiconductor device of claim 1. Toyoda ‘033 further discloses wherein the input-side diode includes: a cathode region that is a part of the semiconductor base body (diode D2 includes cathode region that is part of n-type epitaxial layer 2 as shown in Fig. 3; paragraphs [0091], [0093]); and an anode region of a second conductivity type deposited at an upper part of the semiconductor base body (diode D2 includes anode region of p-type deposited at upper part of epitaxial layer 2 as shown in Fig. 3; paragraphs [0091], [0093]).
Regarding claim 5, Toyoda ‘033 in view of Akahane teaches the semiconductor device of claim 3. Toyoda ‘033 further discloses wherein the vertical protective diode includes: a cathode region that is a part of the semiconductor base body (diode D1 includes cathode region that is part of n-type epitaxial layer 2 as shown in Fig. 3; paragraphs [0091]-[0094]); and an anode region of a second conductivity type deposited at an upper part of the semiconductor base body (diode D2 includes anode region of p-type deposited at upper part of epitaxial layer 2 as shown in Fig. 3; paragraphs [0091]-[0094]).
Regarding claim 6, Toyoda ‘033 in view of Akahane teaches the semiconductor device of claim 1. Toyoda ‘033 further discloses wherein the first control circuit element includes: a well region of a second conductivity type deposited at an upper part of the semiconductor base body (horizontal n-channel MOSFET 20 includes a p-type base region 21 as shown in Fig. 3; paragraphs [0080], [0082]); first and second main electrode regions of the first conductivity type deposited at upper parts of the well region (n-type source and drain electrodes 22, 23 deposited at upper part of p-type base region 21 as shown in Fig. 3; paragraphs [0080]-[0081]); and a gate electrode provided on the well region interposed between the first and second main electrode regions via a gate insulating film (gate electrode 27 disposed upon gate insulating film and between source and drain electrodes 22, 23 as shown in Fig. 3; paragraph [0081]).
Regarding claim 13, Toyoda ‘033 in view of Akahane teaches the semiconductor device of claim 1. Toyoda ‘033 further discloses further comprising a vertical output-stage element provided in the semiconductor base body (vertical MOSFET 10 of output stage portion provided in epitaxial layer 2 as shown in Fig. 3; paragraph [0078]).
Regarding claim 14, Toyoda ‘033 in view of Akahane teaches the semiconductor device of claim 1. Toyoda ‘033 further discloses wherein the first signal input terminal is a terminal for inputting a first external signal (wiring layer for receiving external signals, e.g. from input terminals or pads, to be delivered to gate electrode 27; paragraph [0081]).
Regarding claim 15, Toyoda ‘033 in view of Akahane teaches the semiconductor device of claim 14.
Toyoda ‘033 fails to disclose wherein a surge current flows to the low- potential-side terminal via the input-side diode and the vertical protective element, when an external surge is applied to the first signal input terminal.
However, Akahane discloses wherein a surge current flows to the low- potential-side terminal via the input-side diode and the vertical protective element, when an external surge is applied to the first signal input terminal (surge applied to input terminal of driving circuit 100 causing surge current to flow to low-potential side terminal via diodes 44, 54, 64 and diodes 45, 55, 65; Fig. 1; paragraphs [0046]-[0047], [0058], [0061]-[0062]).
Toyoda ‘033 and Akahane are both considered to be analogous to the claimed invention because they are in the same field of IGBTs using diodes as protective elements. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Toyoda ‘033 to incorporate the teaching of Akahane in order to potentially provide effective surge current diversion, enhanced overvoltage protection, and robust vertical current handling.
Regarding claim 19, Toyoda ‘033 in view of Akahane teaches the semiconductor device of claim 1. Toyoda ‘033 further discloses wherein the first signal input terminal receives a first external signal to control an output-stage element, and the second signal input terminal receives a second external signal to control a protective circuit (wiring layer provides signals to terminals of first and second MOSFET unit cells 20 possibly for the purpose of controlling an output stage element or protective circuit such as vertical output stage MOSFET 10 or protective element 30; Figs. 1 & 15; paragraphs [0077], [0079]-[0082], [0087], [0122]).
Claims 7-10, 12 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Toyoda ‘033 in further view of Akahane and US 2018/0277437 A1 to Yamada et al. (hereinafter “Yamada” – previously cited reference).
Regarding claim 7, Toyoda ‘033 disclose a semiconductor device comprising:
a semiconductor base body of a first conductivity type (n-type substrate 1 and epitaxial layer 2; Fig. 1; paragraph [0078]);
a high-potential-side terminal connected to the semiconductor base body (VCC terminal electrically connected to substrate 1 and epitaxial layer 2; Fig. 1; paragraph [0086]);
a horizontal first control circuit element deposited at an upper part of the semiconductor base body (first unit cell of horizontal n-channel MOSFET 20 deposited at upper part of substrate 1 and epitaxial layer 2; Figs. 1 & 15; paragraphs [0077], [0080]-[0081], [0122]);
a first signal input terminal connected to a control electrode of the first control circuit element (gate electrode 27 of first unit cell of MOSFET 20 electrically connected to wiring layer which in part may provide input signals to gate electrode 27; Fig. 1; paragraphs [0079], [0081]);
a low-potential-side terminal connected to a first main electrode region of the first control circuit element (GND terminal connected to source electrode 22 of MOSFET 20; Fig. 1; paragraphs [0084]-[0085]);
an input-side diode connected in a forward direction between the first signal input terminal and the semiconductor base body (diode D2 formed by first p-n junction between epitaxial layer 2 and diffusion region 24 and disposed in circuit portion which receives input signals and arranged between wiring layer and substrate 1/epitaxial layer 2 over VCC terminal as shown in Fig. 3; paragraphs [0079], [0081], [0088], [0090]);
a vertical protective element connected between the semiconductor base body and the low-potential-side terminal (vertical diode D1 of protective element portion 30 and connected between GND terminal and substrate 1/epitaxial layer 2 as shown in Fig. 3; paragraphs [0076], [0086], [0090]-[0093]),
a diode with a cathode connected to the high-potential-side terminal (diode D1 of protective element portion 30 connected to VCC terminal as shown in Fig. 3; paragraphs [0090]-[0093]); and
a resistor connected between an anode of the diode and the low- potential-side terminal (resistor R1 connected between diode D1 and GND terminal as shown in Fig. 3; paragraphs [0091], [0093]), and
the anode of the diode is connected to a second main electrode of the MOS transistor via the resistor (anode of diode D1 connected to electrodes of vertical MOSFET 10 via various resistive elements; paragraphs [0085]-[0086], [0091]-[0094], [0099], [0102]-[0103]).
Toyoda ‘033 fails to disclose wherein the vertical protective element includes: a vertical MOS transistor connected between the high-potential-side terminal and the low-potential-side terminal; a horizontal diode, and the anode of the horizontal diode is connected to a second main electrode of the MOS transistor; wherein an anode of the input-side diode is connected to the control electrode of the first control circuit element; and further comprising horizontal diodes connected in series, and an anode of a second horizontal diode of the horizontal diodes is connected to a second main electrode of the MOS transistor.
However, Yamada teaches the vertical protective element includes: a vertical MOS transistor connected between the high-potential-side terminal and the low-potential-side terminal (overvoltage protection device having vertical MOSFET 10 coupled between high and low potential sides of semiconductor device in circuit; Figs. 1-3; paragraphs [0031]-[0033]); a horizontal diode (overvoltage protection device having temperature sensing part 20 which may be a horizontal diode; abstract; Figs. 1-3; paragraphs [0031]-[0033]), and the anode of the horizontal diode is connected to a second main electrode of the MOS transistor (anode electrode 23 of part 20 connected to electrode 9 of vertical MOSFET 10 via contact hole 8b; Figs. 1-3; paragraphs [0035]-[0036]).
Toyoda ‘033 and Yamada are both considered to be analogous to the claimed invention because they are in the same field of high-voltage semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Toyoda ‘033 to incorporate the teaching of Yamada in order to adequately prevent an overvoltage event within the circuit (see Yamada, paragraphs [0031]-[0033]).
Toyoda ‘033 as modified further fails to disclose wherein an anode of the input-side diode is connected to the control electrode of the first control circuit element.
However, Akahane discloses wherein an anode of the input-side diode is connected to the control electrode of the first control circuit element (anode of diode 44 connected in forward direction between gate 16 of transistor 46 of input circuit 40 and an input terminal of driving circuit 100; Fig. 1; paragraphs [0049], [0061]).
Toyoda ‘033 and Akahane are both considered to be analogous to the claimed invention because they are in the same field of IGBTs using diodes as protective elements. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Toyoda ‘033 to incorporate the teaching of Akahane in order to potentially provide protection against overvoltage, noise immunity and signal isolation, and controlled signal conditioning.
Toyoda ‘033 as modified further fails to disclose horizontal diodes connected in series.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Toyoda ‘033 in this manner as it is well-known to connect diodes in series in order to increase reverse breakdown voltage or adjust forward threshold given that single lateral diodes have limited breakdown due to lateral spacing and doping constraints. Stacking lateral diodes in series is a routine, low-complexity technique with predictable trade-offs to reliably increase reverse voltage handling with minimal layout changes.
Regarding claim 8, Toyoda ‘033 in view of Akahane and Yamada teaches the semiconductor device of claim 7. Toyoda ‘033 further discloses wherein the input-side diode includes: a cathode region that is a part of the semiconductor base body (diode D2 includes cathode region that is part of n-type epitaxial layer 2 as shown in Fig. 3 of Toyoda et al.; paragraphs [0091], [0093]); and an anode region of a second conductivity type deposited at an upper part of the semiconductor base body (diode D2 includes anode region of p-type deposited at upper part of epitaxial layer 2 as shown in Fig. 3 of Toyoda et al.; paragraphs [0091], [0093]).
Regarding claim 9, Toyoda ‘033 in view of Akahane and Yamada teaches the semiconductor device of claim 7. Toyoda ‘033 further discloses wherein the vertical MOS transistor includes: a well region of a second conductivity type deposited at an upper part of the semiconductor base body (p-type base region 6 deposited at upper part of epitaxial layer 2 as shown in Fig. 3 of Toyoda et al.; paragraph [0079]); a main electrode region of the first conductivity type deposited at an upper part of the well region (n-type source region 7 deposited at upper part of p-type base region 6 as shown in Fig. 3 of Toyoda et al.; paragraph [0079]); and a gate electrode buried in a trench via a gate insulating film provided at an upper part of the semiconductor base body (gate electrode 5 buried in trench 3 with gate insulating film 4 at upper part of epitaxial layer 2 as shown in Fig. 3 of Toyoda et al.; paragraph [0079]).
Regarding claim 10, Toyoda ‘033 in view of Akahane and Yamada teaches the semiconductor device of claim 7.
Toyoda ‘033 fails to disclose wherein the horizontal diodes are polysilicon diodes provided on the semiconductor base body via an insulating film.
However, Yamada teaches wherein the horizontal diodes are polysilicon diodes provided on the semiconductor base body via an insulating film (overvoltage protection device having temperature sensing part 20 which may be a horizontal poly-silicon diode with an insulating film 8 disposed over silicon carbide base 100; abstract; Figs. 1-3; paragraphs [0031]-[0033]).
Toyoda ‘033 and Yamada are both considered to be analogous to the claimed invention because they are in the same field of high-voltage semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Toyoda ‘033 to incorporate the teaching of Yamada in order to utilize a known material for a diode in order to prevent an overvoltage event within the circuit (see Yamada, paragraphs [0031]-[0033]).
Regarding claim 12, Toyoda ‘033 in view of Akahane and Yamada teaches the semiconductor device of claim 7. Another interpretation of Toyoda ‘033 further discloses further comprising: a horizontal second control circuit element deposited at an upper part of the semiconductor base body (second unit cell of horizontal n-channel MOSFET 20 deposited at upper part of substrate 1 and epitaxial layer 2; Figs. 1 & 15; paragraphs [0077], [0080]-[0081], [0122]); a second signal input terminal connected to a control electrode of the second control circuit element (gate electrode 27 of second unit cell of MOSFET 20 electrically connected to wiring layer which in part may provide input signals to gate electrode 27; Fig. 1; paragraphs [0079], [0081]); and a second input-side diode connected in a forward direction between the second signal input terminal and the high-potential-side terminal (second diode formed by second p-n junction between epitaxial layer 2 and diffusion region 24 and disposed in circuit portion which receives input signals and arranged between wiring layer and VCC terminal as shown in Fig. 3; paragraphs [0079], [0081], [0088], [0090]-[0091]).
Regarding claim 16, Toyoda ‘033 in view of Akahane and Yamada teaches the semiconductor device of claim 12. Another interpretation of Toyoda ‘033 further discloses wherein the first signal input terminal is a terminal for inputting a first external signal, and the second signal input terminal is a terminal for inputting a second external signal (wiring layer for receiving external signals, e.g. from input terminals or pads, to be delivered to gate electrode 27; paragraph [0081]).
Regarding claim 17, Toyoda ‘033 in view of Akahane and Yamada teaches the semiconductor device of claim 16.
Toyoda ‘033 fails to disclose wherein a surge current flows to the low-potential-side terminal via the input-side diode and the vertical protective element, when an external surge is applied to the first signal input terminal, and a surge current flows to the low-potential-side terminal via the second input-side diode and the vertical protective element, when an external surge is applied to the second signal input terminal.
However, Akahane discloses wherein a surge current flows to the low-potential-side terminal via the input-side diode and the vertical protective element, when an external surge is applied to the first signal input terminal (surge applied to input terminal of driving circuit 100 causing surge current to flow to low-potential side terminal via diodes 44, 54, 64 and diodes 45, 55, 65; Fig. 1; paragraphs [0046]-[0047], [0058], [0061]-[0062]), and a surge current flows to the low-potential-side terminal via the second input-side diode and the vertical protective element, when an external surge is applied to the second signal input terminal (surge applied to input terminals of driving circuit 100 causing surge current to flow to low-potential side terminal via diodes 44, 54, 64 and diodes 45, 55, 65; Fig. 1; paragraphs [0046]-[0047], [0058], [0061]-[0062]).
Toyoda ‘033 and Akahane are both considered to be analogous to the claimed invention because they are in the same field of IGBTs using diodes as protective elements. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Toyoda ‘033 to incorporate the teaching of Akahane in order to potentially provide effective surge current diversion, enhanced overvoltage protection, and robust vertical current handling.
Regarding claim 18, Toyoda ‘033 in view of Akahane and Yamada teaches the semiconductor device of claim 7. Toyoda ‘033 further discloses a vertical output-stage element provided in the semiconductor base body (vertical output stage MOSFET 10 disposed in epitaxial layer 2; Fig. 1; paragraph [0078]).
6. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Toyoda ‘033 in view of Akahane, Yamada, and further in view of US 7,317,239 B2 to Chen et al. (hereinafter “Chen” – previously cited reference).
Regarding claim 11, Toyoda ‘033 in view of Akahane and Yamada teaches the semiconductor device of claim 7.
Toyoda ‘033 fails to disclose wherein the resistor is a polysilicon resistor provided on the semiconductor base body via an insulating film.
However, Chen teaches wherein the resistor is a polysilicon resistor provided on the semiconductor base body via an insulating film (polysilicon resistor structure includes semiconductor layer 12 provided upon substrate 10 via dielectric layer 13 as shown in Fig. 1; Col. 2, Lines 47-62; Col. 3, Lines 25-36).
Toyoda ‘033 and Chen are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices requiring high-resistance elements. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have further modified Toyoda ‘033 to incorporate the teachings of Chen in order to provide a high resistance element of a known material for a high-voltage semiconductor device to prevent an overvoltage event.
Response to Arguments
Applicant's arguments filed November 21, 2025 have been fully considered. Applicant presents substantive arguments with respect to amended claims 1 and 7 relative to Toyoda ‘033, Akahane, and Yamada. Examiner disagrees that amended claim 1 overcomes the 35 USC 103 rejection using combinations of Toyoda ‘033, Akahane, and Yamada. Specifically, Toyoda ‘033 discloses the limitations amended into amended claim 1 as outlined above. Examiner agrees that amended claim 7 overcomes the previous rejection. However, simply adding another diode in series is a very well-known technique (see e.g. US 6,781,805 B1 to Urakawa) having predictable tunable results as outlined above. Therefore, amended claims 1 and 7 remain rejected under 35 USC 103.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818