DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submissions filed on June 18 and July 13, 2026 have been entered. Claims 1, 11, 12, and 21 are amended. Claims 24 and 25 have been added.
Claims 1, 3-17, 21, 22, 24, and 25 are currently pending.
Response to Amendment
The amendments to the claims filed June 18, 2026 have been entered. Applicant’s amendments to the claims have failed to overcome each and every rejection set forth in the previous Office Action filed March 13, 2026.
Response to Arguments
Applicant's arguments filed June 18, 2026 have been fully considered but they are not persuasive.
Applicant argues on pages 8-9 that Lin does not teach or suggest "a dielectric structure interposed between the first epitaxial structure and second epitaxial structure, the dielectric structure extending between the first epitaxial structure and the second epitaxial structure and electrically isolating the first epitaxial structure from the second epitaxial structure," as recited in amended independent claim 1. Applicant argues on page 8 that the mapping of the “dielectric structure” to Lin’s gate dielectric layer 152 in the rejection of claim 1 set forth in the previous Office Action filed March 13, 2026 is erroneous because Lin does not explicitly describe the function of the gate dielectric layer 152 as electrically isolating one epitaxial structure from another but instead describes it as having a different intended use.
This argument is not persuasive because a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. As explained in the rejection of claims below, the gate dielectric layer 152 of Lin is a dielectric material, and using a dielectric material to electrically isolate various structures from each other is common practice and was known in the art before the filing date of the claimed invention. Applicant acknowledges the inherent property of “a dielectric material to electrically isolate,” (see Applicant’s specification, para. [0015]). Moreover, Applicant has previous acknowledged that the gate dielectric layer 152 of Lin functions as an electrical isolator, “the gate dielectric layer 152 of Lin electrically isolates the semiconductor layers from the S/D structure 138,” (see Applicant’s Remarks filed December 3, 2025, page 14). Therefore, Applicant’s argument that the gate dielectric layer 152 of Lin does not function to electrically isolate one epitaxial structure from another is not persuasive.
Applicant argues on page 9, regarding the rejection of claim 1, that if the Examiner were to remap the "dielectric structure" of amended claim 1 to Lin's isolation sealing layer 174, this remapping would not cure the deficiency. This argument is moot, as it relies on a hypothetical rejection of claim 1, however in order to advance prosecution, Examiner notes that the material of Lin’s isolation sealing layer 174 is described as a dielectric material, like gate dielectric layer 152, and is therefore capable of performing the intended use, i.e., electrically isolating.
Applicant asserts on pages 9-10 that “the Office Action further acknowledges that Lin fails to teach or suggest ‘wherein a ratio of a first distance between laterally aligned ones of the plurality of first semiconductor sections and the plurality of second semiconductor sections, respectively, to a second distance between laterally aligned ones of the plurality of first spacers and the plurality of second spacers, respectively, is less than a threshold of about 1.5.’”
This argument is not persuasive because it relies on a mischaracterization of the previous Office Action. The previous Office Action did not acknowledge that “Lin fails to teach or suggest ‘wherein a ratio of a first distance between laterally aligned ones of the plurality of first semiconductor sections and the plurality of second semiconductor sections, respectively, to a second distance between laterally aligned ones of the plurality of first spacers and the plurality of second spacers, respectively, is less than a threshold of about 1.5.’” as Applicant contends. Rather, the previous Office Action explained that this feature is implicitly taught by Lin:
Lin teaches the use of a multi-step etching process to form an opening through multiple stacked semiconductor layers and dielectric layers that results in “substantially vertical” sidewalls (Lin, FIGs. 6A and 6B, opening 171 for isolation sealing layer 174, [0115-0118]), i.e., a person having ordinary skill in the art would recognize that the ratio of a first distance between laterally aligned ones of the plurality of first semiconductor sections and the plurality of second semiconductor sections, respectively, to a second distance between laterally aligned ones of the plurality of first spacers and the plurality of second spacers, respectively, is approximately 1, which is below Applicant’s claimed threshold of about 1.5.
The previous Office Action then applied Chang as an additional reference, in the same field of endeavor, to show that it was known in the art before the filing date of the claimed invention that:
the width and taper of an etch can be predictably controlled to arrive at an approximately 90 degree taper angle which would result in approximately equal distances between the opposing sides, i.e., the ratio of a first distance between laterally aligned ones of the plurality of first semiconductor sections and the plurality of second semiconductor sections, respectively, to a second distance between laterally aligned ones of the plurality of first spacers and the plurality of second spacers, respectively, is approximately 1 (see Chang, FIGs. 12A-12E and accompanying text).
In response to Applicant's arguments on pages 9-10 against the Lin and Chang references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Applicant argues on pages 9-10 that:
The cited portions of Chang appear to describe controlling the width and taper of a separation plug … but do not describe any dimensional relationship between alternating layers of semiconductor sections and spacers, and therefore do not teach or suggest "a ratio of a first distance between laterally aligned ones of the plurality of first semiconductor sections and the plurality of second semiconductor sections, respectively, to a second distance between laterally aligned ones of the plurality of first spacers and the plurality of second spacers, respectively, is less than a threshold of about 1.5," as recited in amended independent claim 1.
This argument is not persuasive because, as explained in the previous Office Action, and again the rejections of the claims below, the rejections are based on the combination of Lin and Chang. Chang is cited to show that a person having ordinary skill in the art before the effective filing date of the claimed invention would have known that the width and taper of an etch can be predictably controlled to arrive at an approximately 90 degree taper angle which would result in approximately equal distances between the opposing sides. Applying the etch technique taught by Chang to the teachings of Lin, would therefore teach the ratio of a first distance between laterally aligned ones of the plurality of first semiconductor sections and the plurality of second semiconductor sections, respectively, to a second distance between laterally aligned ones of the plurality of first spacers and the plurality of second spacers, respectively, is approximately 1, which is less than Applicant’s claimed threshold of 1.5. For the same reasons, Chang in view of Lin teaches a maximum variance percentage of a width of the dielectric structure is less than about 50%. Therefore, this argument is not persuasive.
In response to Applicant’s argument that the dependent claims are patentably distinct over the prior art, and are also allowable based at least on their dependency from the independent claims 1, 11, and 21 as amended, see the rejections of the claims below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al., US 2021/0135009 A1 (hereinafter Lin) in view of Chang et al., U.S. Pat. No. 9,331,074 B1 (hereinafter Chang).
Regarding claim 1, as amended, Lin teaches: A semiconductor device, comprising: a first epitaxial structure (Lin, FIGs. 1G-1K, portion of S/D structure 138 shown below the intersection of lines AA1 and BB1, [0044]) and a second epitaxial structure (Lin, FIGs. 1G-1K, portion of S/D structure 138 shown to the right of the intersection of lines AA1 and BB1, [0044]);
a dielectric structure interposed between the first epitaxial structure and second epitaxial structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152 [the dielectric structure] shown interposed between the portion of S/D structure 138 shown below the intersection of lines AA1 and BB1 [the first epitaxial structure] and the portion of S/D structure 138 shown to the right of the intersection of lines AA1 and BB1 [the second epitaxial structure], [0058-0059]), the dielectric structure extending between the first epitaxial structure and the second epitaxial structure (Lin, FIG. 1K shows gate dielectric layer 152 [the dielectric structure] extending parallel to line AA1 between the portion of S/D structure 138 shown below the intersection of lines AA1 and BB1 [the first epitaxial structure] and the portion of S/D structure 138 shown to the right of the intersection of lines AA1 and BB1 [the second epitaxial structure]) and electrically isolating the first epitaxial structure from the second epitaxial structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152 [the dielectric structure] shown interposed between the portion of S/D structure 138 shown below the intersection of lines AA1 and BB1 [the first epitaxial structure] and the portion of S/D structure 138 shown to the right of the intersection of lines AA1 and BB1 [the second epitaxial structure], [0058-0059]); Applicant acknowledges the inherent property of “a dielectric material to electrically isolate,” see Applicant’s specification, para. [0015]);
a plurality of first semiconductor sections coupled between the dielectric structure and the first epitaxial structure (Lin, FIG. 1K-2, the first semiconductor sections are shown as the left half of second semiconductor layers 106, [0026-0028; 0044]);
a plurality of first spacers interposed between the dielectric structure and the first epitaxial structure (Lin, FIG. 1K-2, the first spacers are shown as the left half of inner spacer layers 136, [0040]), wherein the plurality of first spacers are alternately arranged with the plurality of first semiconductor sections (Lin, see FIGs. 1K – 1K-2);
a plurality of second semiconductor sections coupled between the dielectric structure and the second epitaxial structure (Lin, FIG. 1K-2, the second semiconductor sections are shown as the right half of second semiconductor layers 106, shown coupled between gate dielectric layer 152 [the dielectric structure] and portion of S/D structure 138 [the second epitaxial structure], [0026-0028; 0044]); and
a plurality of second spacers interposed between the dielectric structure and the second epitaxial structure (Lin, FIG. 1K-2, the second spacers are shown as the right half of inner spacer layers 136, [0040]), wherein the plurality of second spacers are alternately arranged with the plurality of second semiconductor sections (Lin, see FIGs. 1K – 1K-2);
Lin does not explicitly teach: wherein a ratio of a first distance between laterally aligned ones of the plurality of first semiconductor sections and the plurality of second semiconductor sections, respectively, to a second distance between laterally aligned ones of the plurality of first spacers and the plurality of second spacers, respectively, is less than a threshold of about 1.5.
However, this feature is implicitly taught by Lin. Lin teaches the use of a multi-step etching process to form an opening through multiple stacked semiconductor layers and dielectric layers that results in “substantially vertical” sidewalls (Lin, FIGs. 6A and 6B, opening 171 for isolation sealing layer 174, [0115-0118]), i.e., a person having ordinary skill in the art would recognize that the ratio of a first distance between laterally aligned ones of the plurality of first semiconductor sections and the plurality of second semiconductor sections, respectively, to a second distance between laterally aligned ones of the plurality of first spacers and the plurality of second spacers, respectively, is approximately 1, which is below Applicant’s claimed threshold of about 1.5. Additionally, Chang, in the same field of endeavor, teaches that the width and taper of an etch can be predictably controlled to arrive at an approximately 90 degree taper angle which would result in approximately equal distances between the opposing sides, i.e., the ratio of a first distance between laterally aligned ones of the plurality of first semiconductor sections and the plurality of second semiconductor sections, respectively, to a second distance between laterally aligned ones of the plurality of first spacers and the plurality of second spacers, respectively, is approximately 1 (see Chang, FIGs. 12A-12E and accompanying text).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin with the etch control process as taught by Chang, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as implicitly recognized by Chang, to predicably control the etch process, yielding the taper angle and width of the etch within an optimal predetermined threshold, thereby improving manufacturing processes and device reliability.
Regarding claim 3, Lin in view of Chang teaches: The semiconductor device of claim 1, wherein the dielectric structure extends perpendicular to the first epitaxial structure and the second epitaxial structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152 [the dielectric structure] shown extending perpendicular to each of S/D structures 138 [the first epitaxial structure and the second epitaxial structure], [0058-0059]).
Regarding claim 4, Lin in view of Chang teaches: The semiconductor device of claim 1, further comprising a third epitaxial structure (Lin, FIG. 1G, portion of S/D structure 138 shown to the left of the intersection of lines AA1 and BB1, [0044]) and a fourth epitaxial structure (Lin, FIG. 1G, portion of S/D structure 138 shown above the intersection of lines AA1 and BB1, [0044]).
Regarding claim 5, Lin in view of Chang teaches: The semiconductor device of claim 4, wherein the dielectric structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152) is also interposed between the third epitaxial structure and fourth epitaxial structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152 [the dielectric structure] shown interposed between the portion of S/D structure 138 shown to the left of the intersection of lines AA1 and BB1 [the third epitaxial structure] and the portion of S/D structure 138 shown above the intersection of lines AA1 and BB1 [the fourth epitaxial structure], [0058-0059]).
Regarding claim 6, Lin in view of Chang teaches every element of claim 6 but is silent regarding: a fifth epitaxial structure and a sixth epitaxial structure aligned with the first epitaxial structure and the second epitaxial structure.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed structural arrangement comprising a fifth epitaxial structure and a sixth epitaxial structure aligned with the first epitaxial structure and the second epitaxial structure, because, as discussed above regarding claim 1, the arrangement of epitaxial structures was known in the art, and mere duplication of parts has no patentable significance unless a new and unexpected result is produced. See MPEP 2144.04, VI.
Regarding claim 7, Lin in view of Chang teaches: The semiconductor device of claim 6, further comprising a first active gate structure extending parallel to the dielectric structure and in contact with the dielectric structure (Lin, FIGs. 1K – 1K-2, work function layer 154 [the active gate structure] shown extending parallel to and in contact with gate dielectric layer 152 [the dielectric structure], [0058]), wherein the first active gate structure wraps around each of a plurality of layers of channel material (Lin, see FIGs. 1K – 1K-2, “each of the second semiconductor layers 106 [layers of channel material] is surrounded by the multiple layers of the first gate structure 170 a and the multiple layers of the second gate structure 170 b,” including work function layer 154 [the active gate structure], [0058]).
Regarding claim 8, Lin in view of Chang teaches every element of claim 8 but is silent regarding: wherein the fifth epitaxial structure and sixth epitaxial structure, disposed on opposite sides of the first active gate structure, are in electrical contact with the plurality of layers of channel material.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed structural arrangement wherein the fifth epitaxial structure and sixth epitaxial structure, disposed on opposite sides of the first active gate structure, are in electrical contact with the plurality of layers of channel material, because, as discussed above regarding claim 7, the arrangement of epitaxial structures, gate structures, and channel material layers was known in the art, and mere duplication of parts has no patentable significance unless a new and unexpected result is produced. See MPEP 2144.04, subsection VI. Additionally, Lin teaches that the epitaxial structure is formed directly on the semiconductor layers, i.e., is in electrical contact with the channel material (Lin, [0042]).
Regarding claim 9, Lin in view of Chang teaches every element of claim 9 but is silent regarding: a second active gate structure disposed in parallel with the dielectric structure, wherein the second active gate structure wraps around each of a plurality of second layers of channel material.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed structural arrangement comprising a second active gate structure disposed in parallel with the dielectric structure, wherein the second active gate structure wraps around each of a plurality of second layers of channel material, because, as discussed above regarding claim 7, the arrangement of gate structures was known in the art, and mere duplication of parts has no patentable significance unless a new and unexpected result is produced. See MPEP 2144.04, subsection VI.
Regarding claim 10, Lin in view of Chang teaches: The semiconductor device of claim 9, wherein the first epitaxial structure or the second epitaxial structure is in electrical contact with the plurality of second layers of channel material (Lin, “S/D structure 138 [the epitaxial structure] is formed on the exposed second semiconductor layers 106 [the plurality of second layers of channel material],”, i.e., in electrical contact, [0042; 0044]).
Regarding claim 11, as amended, Lin teaches: A semiconductor device, comprising: a first epitaxial structure (Lin, FIG. 1J, S/D structure 138 formed on first fin structure 110a, “S/D structure 138 [the first epitaxial structure] is formed on the exposed second semiconductor layers 106” [0042; 0044]);
a dielectric structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152 shown extending along the direction parallel to the line AA1, [0058-0059]) disposed next to the first epitaxial structure (Lin, see FIGs. 1K – 1K-2, [0058]), the dielectric structure extending between the first epitaxial structure and a second epitaxial structure (Lin, FIGs. 1K – 1K-2 shows gate dielectric layer 152 [the dielectric structure] extending along the direction parallel to the line AA1 between two instances of S/D structure 138 [the first epitaxial structure and a second epitaxial structure], [0058-0059]) and electrically isolating the first epitaxial structure from the second epitaxial structure (Lin, FIGs. 1K – 1K-2 shows gate dielectric layer 152 [the dielectric structure] extending along the direction parallel to the line AA1 between two instances of S/D structure 138 [the first epitaxial structure and a second epitaxial structure], [0058-0059]; Applicant acknowledges the inherent property of “a dielectric material to electrically isolate,” see Applicant’s specification, para. [0015]);
a plurality of first semiconductor sections interposed between the dielectric structure and the first epitaxial structure (Lin, FIGs. 1K – 1K-2, second semiconductor layers 106, [0026-0028; 0044]); and
a plurality of first spacers interposed between the dielectric structure and the first epitaxial structure (Lin, FIG. 1K-2, the first spacers are shown as the left half of inner spacer layers 136, [0040]), wherein the plurality of first spacers are alternately arranged with the plurality of first semiconductor sections and coupled to the first epitaxial structure (Lin, FIGs. 1K – 1K-2, inner spacer layers 136 [the plurality of first spacers] shown alternately arranged with the second semiconductor layers 106 [the plurality of first semiconductor sections] and coupled to S/D structure 138 [the first epitaxial structure], [0040]);
wherein
Although Lin is silent regarding a maximum variance percentage of a width of the dielectric structure is less than about 50%, this feature is implicitly taught by Lin. Lin teaches that the width of the dielectric structure is defined by an opening having “substantially vertical” sidewalls, i.e., the maximum variance percentage of the width of the resulting dielectric structure is less than about 50% (Lin, FIGs. 6A – 6B, [0115-0118]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed maximum variance percentage of a width of the dielectric structure is less than about 50% with predictable results and without undue experimentation because Lin teaches that vertical sidewalls, and the resulting minimal variation in the resulting width of the dielectric structure, are known in the art and it has been held that routine optimization is not inventive. See MPEP 2144.05(II)(A). Furthermore, Chang, in the same field of endeavor, teaches that the width and taper of an etch can be predictably controlled to arrive at an approximately 90-degree taper angle which would result in approximately equal distances between the opposing sides, i.e., a maximum variance percentage of a width of the dielectric structure is less than about 50% (see Chang, FIGs. 12A-12E and accompanying text).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin with the etch control process as taught by Chang, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as implicitly recognized by Chang, to predicably control the etch process, yielding the taper angle and width of the etch within an optimal predetermined threshold, thereby improving manufacturing processes and device reliability.
Regarding claim 12, as amended, Lin in view of Chang teaches: The semiconductor device of claim 11, wherein the dielectric structure is coupled to the first epitaxial structure and the second epitaxial structure (Lin, FIG. 1K-2, shows gate dielectric layer 152 [the dielectric structure] formed on, i.e., coupled to, each of S/D structure 138 formed on first fin structure 110a [the first epitaxial structure] and S/D structure 138 formed on second fin structure 110b [the second epitaxial structure], “the S/D structure 138 [the first and second epitaxial structure] is formed on the exposed second semiconductor layers 106 [the first semiconductor sections],” [0042]; “each of the nanostructures 106 [the first semiconductor sections] is surrounded by the gate dielectric layer 152 [the dielectric structure],” [0058], i.e., the dielectric structure is coupled to the first epitaxial structure and the second epitaxial structure).
Regarding claim 13, Lin in view of Chang teaches: The semiconductor device of claim 12, further comprising: a plurality of second semiconductor sections interposed between the dielectric structure and the second epitaxial structure (Lin, FIGs. 1K – 1K-2, second semiconductor layers 106, [0026-0028; 0044]); and a plurality of second spacers interposed between the dielectric structure and the second epitaxial structure, wherein the plurality of second spacers are alternately arranged with the plurality of second semiconductor sections (Lin, FIGs. 1K – 1K-2, inner spacer layers 136, [0040]).
Regarding claim 14, Lin in view of Chang teaches: The semiconductor device of claim 11, further comprising an active gate structure in contact with the dielectric structure (Lin, FIGs. 1K – 1K-2, work function layer 154 [the active gate structure] shown in contact with gate dielectric layer 152 [the dielectric structure], [0058]), wherein the active gate structure wraps around a second semiconductor section aligned with one of the plurality of first semiconductor sections (Lin, see FIGs. 1K – 1K-2, “each of the second semiconductor layers 106 [the plurality of semiconductor sections] is surrounded by the multiple layers of the first gate structure 170 a and the multiple layers of the second gate structure 170 b,” including work function layer 154 [the active gate structure], [0058]).
Regarding claim 15, Lin in view of Chang teaches: The semiconductor device of claim 14, further comprising a third epitaxial structure and a fourth epitaxial structure in electrical contact with the second semiconductor section (Lin, FIGs. 1J – 1K-2 show four S/D structures 138, i.e., four epitaxial structures, in electrical contact with the second semiconductor layers 106 [the second semiconductor section], [0058]).
Regarding claim 16, Lin in view of Chang teaches: The semiconductor device of claim 11, wherein the dielectric structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152, [0059]) includes at least one of an oxide material or silicon nitride (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152, “made of ... zirconium oxide, aluminum oxide, titanium oxide ...,” i.e., an oxide material, [0059]).
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Lin include one or more of Applicant’s claimed alternative elements, for example: an oxide material.
Regarding claim 17, Lin in view of Chang teaches: The semiconductor device of claim 11, wherein the dielectric structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152, [0059]) downwardly extends beyond a bottom surface of the first epitaxial structure (Lin, FIGs. 1K1 shows gate dielectric layer 152 [the dielectric structure] downwardly extends beyond a bottom surface of S/D structure 138 formed on first fin structure 110a [the first epitaxial structure]; gate dielectric layer 152 [the dielectric structure] is shown below lower surface of S/D structure 138 formed on first fin structure 110a [the first epitaxial structure]).
Regarding claim 21, as amended, Lin teaches: A semiconductor device, comprising: a plurality of layers of channel material vertically spaced from one another (Lin, FIG. 1J, second semiconductor layers 106, shown spaced apart from one another both vertically and horizontally, “second semiconductor layers 106 [the plurality of layers of channel material] are used to as channel region,” i.e., channel material, [0053]) and in contact with a pair of epitaxial structures (Lin, FIG. 1J, S/D structure 138, “S/D structure 138 [the pair of epitaxial structures] is formed on the exposed second semiconductor layers 106 [the plurality of layers of channel material],” [0042; 0044]);
a gate structure formed over the plurality of layers of channel material (Lin, FIG. 1K shows first gate structure 170a and second gate structure 170b formed over second semiconductor layers 106 [the plurality of layers of channel material], [0058]); and
a dielectric structure electrically isolating the pair of epitaxial structures (Lin, FIG. 2E, isolation sealing layer 174, “a high-k dielectric layer,” shown in between each of S/D structure 138 [the pair of epitaxial structures], [0075]; Applicant acknowledges the inherent property of “a dielectric material to electrically isolate,” see Applicant’s specification, para. [0015]) and extending through the plurality of layers of channel material (Lin, FIGs. 2E-2G show isolation sealing layer 174 [the dielectric structure] extending between, i.e., through, vertical columns of second semiconductor layers 106 [the plurality of layers of channel material], [0078]),
Although Lin is silent regarding a maximum variance in width of the dielectric structure between the pair of epitaxial structures falls within a predetermined tolerance range, such that a maximum variance percentage of the width of the dielectric structure is less than about 50%, Lin teaches that the dielectric structure is formed in an opening having “substantially vertical” sidewalls, i.e., the maximum variance percentage of the width of the resulting dielectric structure is less than about 50% (Lin, FIGs. 6A – 6B, [0115-0118]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed maximum variance percentage of the width of the dielectric structure is less than about 50% with predictable results and without undue experimentation because Lin teaches that vertical sidewalls, and the resulting minimal variation in the width of the dielectric structure, are known in the art and it has been held that routine optimization is not inventive. See MPEP 2144.05(II)(A). Furthermore, Chang, in the same field of endeavor, teaches that the width and taper of an etch can be predictably controlled to arrive at an approximately 90-degree taper angle which would result in approximately equal distances between the opposing sides, i.e., the maximum variance percentage of the width of the dielectric structure is less than about 50% (see Chang, FIGs. 12A-12E and accompanying text).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin with the etch control process as taught by Chang, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as implicitly recognized by Chang, to predicably control the etch process, yielding the taper angle and width of the etch within an optimal predetermined threshold, thereby improving manufacturing processes and device reliability.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Chang, and further in view of Frougier et al., US 2023/0086633 A1 (hereinafter Frougier).
Regarding claim 22, Lin in view of Chang teaches: The semiconductor device of claim 21, wherein the dielectric structure extends downward beyond a bottom surface of the pair of epitaxial structures (Lin, FIG. 2E shows isolation sealing layer 174 [the dielectric structure] extending downward through gate dielectric layer 152 shown below bottom surface of S/D structure 138 [the pair of epitaxial structures], i.e., extending downward beyond a bottom surface of the pair of epitaxial structures, [0075])
Lin in view of Chang is silent regarding: the dielectric structure extends downward … into a substrate material upon which the pair of epitaxial structures are defined.
However, Frougier, in the same field of endeavor, teaches: the dielectric structure (Frougier, FIG. 13B, dielectric layer 1000, [0068]) extends downward … into a substrate material upon which the pair of epitaxial structures are defined (Frougier, FIG. 13B shows dielectric layer 1000 [the dielectric structure] extending downward into substrate 102 [the substrate material] upon which the pair of epitaxial structures are defined, [0068]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Frougier with the teachings of Lin in view of Chang, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Frougier, to further enhance the electrical isolation of the source/drain regions, thereby improving device performance and reliability.
Regarding claim 24, Lin in view of Chang teaches: The semiconductor device of claim 21, wherein the dielectric structure (Lin, FIG. 2E, isolation sealing layer 174) includes at least one of an oxide material or silicon nitride (Lin, FIG. 2E, isolation sealing layer 174 [the dielectric structure] includes a high-k dielectric layer; high-k dielectric materials include “zirconium oxide, aluminum oxide, titanium oxide,” i.e., an oxide material, [0075]).
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Lin include one or more of Applicant’s claimed alternative elements, for example: an oxide material.
Regarding claim 25, Lin in view of Chang teaches: The semiconductor device of claim 21, further comprising a plurality of spacers (Lin, FIG. 1K-2, inner spacer layers 136, [0040-0041]) interposed between the dielectric structure and one of the pair of epitaxial structures (Lin, FIGs. 1J - 1K-2, one of S/D structure 138 [one of the pair of epitaxial structures], shown in FIG. 1K-2 as the first gate structure 170a, and including inner spacer layers 136 [the plurality of spacers], is separated from the other one of S/D structure 138 [one of the pair of epitaxial structures] by isolation sealing layer 174 [the dielectric structure], [0042-0044]; “The first gate structure 170 a and the second gate structure 170 b [the pair of epitaxial structures, including the plurality of spacers] are separated by the first isolation sealing layer 174 [the dielectric structure],” [0078], i.e., the plurality of spacers are between the dielectric structure and one of the pair of epitaxial structures), wherein the plurality of spacers are alternately arranged with the plurality of layers of channel material (Lin, FIG. 1K-2 shows inner spacer layers 136 [the plurality of spacers] alternately arranged with the second semiconductor layers 106 [the plurality of layers of channel material], [0040-0041]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure. The cited prior art discloses similar materials, devices, and methods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRENT A FAIRBANKS can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights