Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Applicant’s Amendment and Request for Reconsideration filed December 3, 2025. Applicant’s amendments to the claims, specification, and drawings have been entered. Claims 2 and 23 have been canceled.
Claims 1, 3-17, 21 and 22 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 29, 2024 has been placed in the application file and is being considered by the examiner with the exception of Cite No. A4 which fails to comply with 37 CFR 1.98(a)(3)(i) because a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language has not been provided. In response to Applicant’s comments on page 11, Cite No. A3 was submitted with an English translation of the Abstract, and the translated portion of the reference has been considered.
Drawings
The drawings filed with the application on June 22, 2022 and the amendments to the drawings filed March 7, 2023 were objected to in the previous Office Action. Applicant has amended the drawings, therefore the previously stated objections to the drawings are withdrawn. The corrected drawings were received on December 3, 2025. These drawings are acceptable.
Response to Amendment
The amendments to the claims filed December 3, 2025 have been entered. Applicant’s amendments to the claims have failed to overcome each and every rejection set forth in the Non-Final Office Action filed March 27, 2025.
Response to Arguments
Applicant's arguments filed December 3, 2025 have been fully considered but they are not persuasive.
Applicant argues on page 14 that the semiconductor layers 106 of Lin are not coupled to the purported "dielectric structure" (cited as the gate dielectric layer 152) and to the purported epitaxial structure (cited as the SID structure 138), because the gate dielectric layer 152 of Lin electrically isolates the semiconductor layers from the SID structure 138 [emphasis added]. This argument is not persuasive because the features upon which applicant relies (i.e., an electrical connection) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Additionally, Applicant’s specification does not define the term “coupled to” as indicative of an electrical connection. As explained in the previous Office Action, and again in the rejection of claims below, FIG. 1K-2 of Lin shows the semiconductor layers 106 [semiconductor sections] in contact with, i.e., coupled to, each of the gate dielectric layer 152 [the dielectric structure] and the S/D structure 138 [the epitaxial structure]. Therefore, this argument is not persuasive.
Applicant argues on pages 15-16 that Chang does not appear to describe any type of etching process in which alternating layers of semiconductor sections and spacers, as claimed, are etched to achieve the claimed distances. This argument is not persuasive because the features upon which applicant relies (i.e., an etching process) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims.
In response to applicant's arguments on pages 15-16 against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Applicant argues on pages 15-16 that Chang does not appear to describe any type of etching process in which alternating layers of semiconductor sections and spacers, as claimed, are etched to achieve the claimed distances. This argument is not persuasive because, as explained in the previous Office Action, and again the rejections of the claims below, the rejections are based on the combination of Lin and Chang. Chang is cited to show that a person having ordinary skill in the art before the effective filing date of the claimed invention would have known that the width and taper of an etch can be predictably controlled to arrive at an approximately 90 degree taper angle which would result in approximately equal distances between the opposing sides. Applying the etch technique taught by Chang to the teachings of Lin, would therefore teach the ratio of a first distance between laterally aligned ones of the plurality of first semiconductor sections and the plurality of second semiconductor sections, respectively, to a second distance between laterally aligned ones of the plurality of first spacers and the plurality of second spacers, respectively, is approximately 1, which is less than Applicant’s claimed threshold of 1.5. For the same reasons, Chang in view of Lin teaches a maximum variance percentage of a width of the dielectric structure is less than about 50%. Therefore, this argument is not persuasive.
In response to Applicant’s argument on pages 15-16 that the dependent claims are patentably distinct over the prior art, and are also allowable based at least on their dependency from the independent claims 1, 11, and 21 as amended, see the rejections of the claims below.
Claim Rejections - 35 USC § 112
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 21-23 were rejected under 35 U.S.C. 112(b) in the previous Office Action filed March 27, 2025. Applicant’s amendments to the claims, filed December 3, 2025 have overcome the rejection, therefore the 35 U.S.C. 112(b) rejection of claims 21-23 has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al., US 2021/0135009 A1 (hereinafter Lin) in view of Chang et al., U.S. Pat. No. 9,331,074 B1 (hereinafter Chang).
Regarding claim 1, as amended, Lin teaches: A semiconductor device, comprising: a first epitaxial structure (Lin, FIG. 1G, portion of S/D structure 138 shown below the intersection of lines AA1 and BB1, [0044]) and a second epitaxial structure (Lin, FIG. 1G, portion of S/D structure 138 shown to the right of the intersection of lines AA1 and BB1, [0044]); a dielectric structure interposed between the first epitaxial structure and second epitaxial structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152 [the dielectric structure] shown interposed between the portion of S/D structure 138 shown below the intersection of lines AA1 and BB1 [the first epitaxial structure] and the portion of S/D structure 138 shown to the right of the intersection of lines AA1 and BB1 [the second epitaxial structure], [0058-0059]); a plurality of first semiconductor sections coupled between the dielectric structure and the first epitaxial structure (Lin, FIG. 1K-2, the first semiconductor sections are shown as the left half of second semiconductor layers 106, [0026-0028; 0044]); a plurality of first spacers interposed between the dielectric structure and the first epitaxial structure (Lin, FIG. 1K-2, the first spacers are shown as the left half of inner spacer layers 136, [0040]), wherein the plurality of first spacers are alternately arranged with the plurality of first semiconductor sections (Lin, see FIGs. 1K – 1K-2); a plurality of second semiconductor sections coupled between the dielectric structure and the second epitaxial structure (Lin, FIG. 1K-2, the second semiconductor sections are shown as the right half of second semiconductor layers 106, shown coupled between gate dielectric layer 152 [the dielectric structure] and portion of S/D structure 138 [the second epitaxial structure], [0026-0028; 0044]); and a plurality of second spacers interposed between the dielectric structure and the second epitaxial structure (Lin, FIG. 1K-2, the second spacers are shown as the right half of inner spacer layers 136, [0040]), wherein the plurality of second spacers are alternately arranged with the plurality of second semiconductor sections (Lin, see FIGs. 1K – 1K-2);
Lin does not explicitly teach: wherein a ratio of a first distance between laterally aligned ones of the plurality of first semiconductor sections and the plurality of second semiconductor sections, respectively, to a second distance between laterally aligned ones of the plurality of first spacers and the plurality of second spacers, respectively, is less than a threshold of about 1.5.
However, Lin teaches the use of a multi-step etching process to form an opening through multiple stacked semiconductor layers and dielectric layers that results in “substantially vertical” sidewalls (Lin, FIGs. 6A and 6B, opening 171 for isolation sealing layer 174, [0115-0118]), i.e., a person having ordinary skill in the art would recognize that the ratio of a first distance between laterally aligned ones of the plurality of first semiconductor sections and the plurality of second semiconductor sections, respectively, to a second distance between laterally aligned ones of the plurality of first spacers and the plurality of second spacers, respectively, is approximately 1, which is below Applicant’s claimed threshold of about 1.5. Additionally, Chang, in the same field of endeavor, teaches that the width and taper of an etch can be predictably controlled to arrive at an approximately 90 degree taper angle which would result in approximately equal distances between the opposing sides, i.e., the ratio of a first distance between laterally aligned ones of the plurality of first semiconductor sections and the plurality of second semiconductor sections, respectively, to a second distance between laterally aligned ones of the plurality of first spacers and the plurality of second spacers, respectively, is approximately 1 (see Chang, FIGs. 12A-12E and accompanying text).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin with the etch control process as taught by Chang, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as implicitly recognized by Chang, to predicably control the etch process, yielding the taper angle and width of the etch within an optimal predetermined threshold, thereby improving manufacturing processes and device reliability.
Regarding claim 3, as amended, Lin in view of Chang teaches: The semiconductor device of claim 1, wherein the dielectric structure extends perpendicular to the first epitaxial structure and the second epitaxial structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152 [the dielectric structure] shown extending perpendicular to each of S/D structures 138 [the first epitaxial structure and the second epitaxial structure], [0058-0059]).
Regarding claim 4, as amended, Lin in view of Chang teaches: The semiconductor device of claim 1, further comprising a third epitaxial structure (Lin, FIG. 1G, portion of S/D structure 138 shown to the left of the intersection of lines AA1 and BB1, [0044]) and a fourth epitaxial structure (Lin, FIG. 1G, portion of S/D structure 138 shown above the intersection of lines AA1 and BB1, [0044]).
Regarding claim 5, Lin in view of Chang teaches: The semiconductor device of claim 4, wherein the dielectric structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152) is also interposed between the third epitaxial structure and fourth epitaxial structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152 [the dielectric structure] shown interposed between the portion of S/D structure 138 shown to the left of the intersection of lines AA1 and BB1 [the third epitaxial structure] and the portion of S/D structure 138 shown above the intersection of lines AA1 and BB1 [the fourth epitaxial structure], [0058-0059]).
Regarding claim 6, as amended, Lin in view of Chang teaches every element of claim 6 but is silent regarding: a fifth epitaxial structure and a sixth epitaxial structure aligned with the first epitaxial structure and the second epitaxial structure.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed structural arrangement comprising a fifth epitaxial structure and a sixth epitaxial structure aligned with the first epitaxial structure and the second epitaxial structure, because, as discussed above regarding claim 1, the arrangement of epitaxial structures was known in the art, and mere duplication of parts has no patentable significance unless a new and unexpected result is produced. See MPEP 2144.04, VI.
Regarding claim 7, as amended, Lin in view of Chang teaches: The semiconductor device of claim 6, further comprising a first active gate structure extending parallel to the dielectric structure and in contact with the dielectric structure (Lin, FIGs. 1K – 1K-2, work function layer 154 [the active gate structure] shown extending parallel to and in contact with gate dielectric layer 152 [the dielectric structure], [0058]), wherein the first active gate structure wraps around each of a plurality of layers of channel material (Lin, see FIGs. 1K – 1K-2, “each of the second semiconductor layers 106 [layers of channel material] is surrounded by the multiple layers of the first gate structure 170 a and the multiple layers of the second gate structure 170 b,” including work function layer 154 [the active gate structure], [0058]).
Regarding claim 8, as amended, Lin in view of Chang teaches every element of claim 8 but is silent regarding: wherein the fifth epitaxial structure and sixth epitaxial structure, disposed on opposite sides of the first active gate structure, are in electrical contact with the plurality of layers of channel material.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed structural arrangement wherein the fifth epitaxial structure and sixth epitaxial structure, disposed on opposite sides of the first active gate structure, are in electrical contact with the plurality of layers of channel material, because, as discussed above regarding claim 7, the arrangement of epitaxial structures, gate structures, and channel material layers was known in the art, and mere duplication of parts has no patentable significance unless a new and unexpected result is produced. See MPEP 2144.04, subsection VI. Additionally, Lin teaches that the epitaxial structure is formed directly on the semiconductor layers, i.e., is in electrical contact with the channel material (Lin, [0042]).
Regarding claim 9, as amended, Lin in view of Chang teaches every element of claim 9 but is silent regarding: a second active gate structure disposed in parallel with the dielectric structure, wherein the second active gate structure wraps around each of a plurality of second layers of channel material.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed structural arrangement comprising a second active gate structure disposed in parallel with the dielectric structure, wherein the second active gate structure wraps around each of a plurality of second layers of channel material, because, as discussed above regarding claim 7, the arrangement of gate structures was known in the art, and mere duplication of parts has no patentable significance unless a new and unexpected result is produced. See MPEP 2144.04, subsection VI.
Regarding claim 10, as amended, Lin in view of Chang teaches: The semiconductor device of claim 9, wherein the first epitaxial structure or the second epitaxial structure is in electrical contact with the plurality of second layers of channel material (Lin, “S/D structure 138 [the epitaxial structure] is formed on the exposed second semiconductor layers 106 [the plurality of second layers of channel material],”, i.e., in electrical contact, [0042; 0044]).
Regarding claim 11, as amended, Lin teaches: A semiconductor device, comprising: a first epitaxial structure (Lin, FIG. 1J, S/D structure 138 formed on first fin structure 110a, “S/D structure 138 [the first epitaxial structure] is formed on the exposed second semiconductor layers 106” [0042; 0044]); a dielectric structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152 shown extending along the direction parallel to the line AA1, [0058-0059]) disposed next to the first epitaxial structure (Lin, see FIGs. 1K – 1K-2); a plurality of first semiconductor sections interposed between the dielectric structure and the first epitaxial structure (Lin, FIGs. 1K – 1K-2, second semiconductor layers 106, [0026-0028; 0044]); and a plurality of first spacers interposed between the dielectric structure and the first epitaxial structure (Lin, FIG. 1K-2, the first spacers are shown as the left half of inner spacer layers 136, [0040]), wherein the plurality of first spacers are alternately arranged with the plurality of first semiconductor sections and coupled to the first epitaxial structure (Lin, FIGs. 1K – 1K-2, inner spacer layers 136 [the plurality of first spacers] shown alternately arranged with the second semiconductor layers 106 [the plurality of first semiconductor sections] and coupled to S/D structure 138 [the first epitaxial structure], [0040]); wherein
Although Lin is silent regarding a maximum variance percentage of a width of the dielectric structure is less than about 50%, Lin teaches that the dielectric structure is formed in an opening having “substantially vertical” sidewalls, i.e., the maximum variance percentage of the width of the resulting dielectric structure is less than about 50% (Lin, FIGs. 6A – 6B, [0115-0118]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed maximum variance percentage of a width of the dielectric structure is less than about 50% with predictable results and without undue experimentation because Lin teaches that vertical sidewalls, and the resulting minimal variation in the width of the dielectric structure, are known in the art and it has been held that routine optimization is not inventive. See MPEP 2144.05(II)(A). Furthermore, Chang, in the same field of endeavor, teaches that the width and taper of an etch can be predictably controlled to arrive at an approximately 90-degree taper angle which would result in approximately equal distances between the opposing sides, i.e., a maximum variance percentage of a width of the dielectric structure is less than about 50% (see Chang, FIGs. 12A-12E and accompanying text).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin with the etch control process as taught by Chang, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as implicitly recognized by Chang, to predicably control the etch process, yielding the taper angle and width of the etch within an optimal predetermined threshold, thereby improving manufacturing processes and device reliability.
Regarding claim 12, as amended, Lin in view of Chang teaches: The semiconductor device of claim 11, further comprising a second epitaxial structure (Lin, FIG. 1J, S/D structure 138 formed on second fin structure 110b, [0042; 0044]) spaced apart from the first epitaxial structure (Lin, FIG. 1J, S/D structure 138 formed on first fin structure 110a), wherein the dielectric structure is positioned between the first epitaxial structure and the second epitaxial structure (Lin, FIG. 1K-2, shows gate dielectric layer 152 [the dielectric structure] positioned between S/D structure 138 formed on first fin structure 110a [the first epitaxial structure] and S/D structure 138 formed on second fin structure 110b [the second epitaxial structure]).
Regarding claim 13, as amended, Lin in view of Chang teaches: The semiconductor device of claim 12, further comprising: a plurality of second semiconductor sections interposed between the dielectric structure and the second epitaxial structure (Lin, FIGs. 1K – 1K-2, second semiconductor layers 106, [0026-0028; 0044]); and a plurality of second spacers interposed between the dielectric structure and the second epitaxial structure, wherein the plurality of second spacers are alternately arranged with the plurality of second semiconductor sections (Lin, FIGs. 1K – 1K-2, inner spacer layers 136, [0040]).
Regarding claim 14, as amended, Lin in view of Chang teaches: The semiconductor device of claim 11, further comprising an active gate structure in contact with the dielectric structure (Lin, FIGs. 1K – 1K-2, work function layer 154 [the active gate structure] shown in contact with gate dielectric layer 152 [the dielectric structure], [0058]), wherein the active gate structure wraps around a second semiconductor section aligned with one of the plurality of first semiconductor sections (Lin, see FIGs. 1K – 1K-2, “each of the second semiconductor layers 106 [the plurality of semiconductor sections] is surrounded by the multiple layers of the first gate structure 170 a and the multiple layers of the second gate structure 170 b,” including work function layer 154 [the active gate structure], [0058]).
Regarding claim 15, as amended, Lin in view of Chang teaches: The semiconductor device of claim 14, further comprising a third epitaxial structure and a fourth epitaxial structure in electrical contact with the second semiconductor section (Lin, FIGs. 1J – 1K-2 show four S/D structures 138, i.e., four epitaxial structures, in electrical contact with the second semiconductor layers 106 [the second semiconductor section], [0058]).
Regarding claim 16, Lin in view of Chang teaches: The semiconductor device of claim 11, wherein the dielectric structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152, [0059]) includes at least one of an oxide material or silicon nitride (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152, “made of ... zirconium oxide, aluminum oxide, titanium oxide ...,” i.e., an oxide material, [0059]).
Regarding claim 17, Lin in view of Chang teaches: The semiconductor device of claim 11, wherein the dielectric structure (Lin, FIGs. 1K – 1K-2, gate dielectric layer 152, [0059]) downwardly extends beyond a bottom surface of the first epitaxial structure (Lin, FIGs. 1K1 shows gate dielectric layer 152 [the dielectric structure] downwardly extends beyond a bottom surface of S/D structure 138 formed on first fin structure 110a [the first epitaxial structure]; gate dielectric layer 152 [the dielectric structure] is shown below lower surface of S/D structure 138 formed on first fin structure 110a [the first epitaxial structure]).
Regarding claim 21, as amended, Lin teaches: A semiconductor device, comprising: a plurality of layers of channel material (Lin, FIG. 1J, second semiconductor layers 106, [0053]) vertically spaced from one another (Lin, FIG. 1J, [0053]) and in contact with a pair of epitaxial structures (Lin, FIG. 1J, S/D structure 138, “S/D structure 138 [the pair of epitaxial structures] is formed on the exposed second semiconductor layers 106 [the plurality of layers of channel material],” [0042; 0044]); a gate structure formed over the plurality of layers of channel material (Lin, FIG. 1K shows first gate structure 170a and second gate structure 170b formed over second semiconductor layers 106 [the plurality of layers of channel material], [0058]); and a dielectric structure electrically isolating the pair of epitaxial structures (Lin, FIG. 2E, isolation sealing layer 174, “a high-k dielectric layer,” shown in between each of S/D structure 138 [the pair of epitaxial structures] [0075]),
Although Lin is silent regarding a maximum variance in width of the dielectric structure between the pair of epitaxial structures falls within a predetermined tolerance range, such that a maximum variance percentage of the width of the dielectric structure is less than about 50%, Lin teaches that the dielectric structure is formed in an opening having “substantially vertical” sidewalls, i.e., the maximum variance percentage of the width of the resulting dielectric structure is less than about 50% (Lin, FIGs. 6A – 6B, [0115-0118]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed maximum variance percentage of the width of the dielectric structure is less than about 50% with predictable results and without undue experimentation because Lin teaches that vertical sidewalls, and the resulting minimal variation in the width of the dielectric structure, are known in the art and it has been held that routine optimization is not inventive. See MPEP 2144.05(II)(A). Furthermore, Chang, in the same field of endeavor, teaches that the width and taper of an etch can be predictably controlled to arrive at an approximately 90-degree taper angle which would result in approximately equal distances between the opposing sides, i.e., the maximum variance percentage of the width of the dielectric structure is less than about 50% (see Chang, FIGs. 12A-12E and accompanying text).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin with the etch control process as taught by Chang, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as implicitly recognized by Chang, to predicably control the etch process, yielding the taper angle and width of the etch within an optimal predetermined threshold, thereby improving manufacturing processes and device reliability.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Chang, and further in view of Frougier et al., US 2023/0086633 A1 (hereinafter Frougier).
Regarding claim 22, as amended, Lin in view of Chang teaches: The semiconductor device of claim 21, wherein the dielectric structure extends downward beyond a bottom surface of the pair of epitaxial structures (Lin, FIG. 2E shows isolation sealing layer 174 [the dielectric structure] extending downward through gate dielectric layer 152 shown below bottom surface of S/D structure 138 [the pair of epitaxial structures], i.e., extending downward beyond a bottom surface of the pair of epitaxial structures, [0075])
Lin in view of Chang is silent regarding: the dielectric structure extends downward … into a substrate material upon which the pair of epitaxial structures are defined.
However, Frougier, in the same field of endeavor, teaches: the dielectric structure (Frougier, FIG. 13B, dielectric layer 1000, [0068]) extends downward … into a substrate material upon which the pair of epitaxial structures are defined (Frougier, FIG. 13B shows dielectric layer 1000 [the dielectric structure] extending downward into substrate 102 [the substrate material] upon which the pair of epitaxial structures are defined, [0068]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Frougier with the teachings of Lin in view of Chang, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Frougier, to further enhance the electrical isolation of the source/drain regions, thereby improving device performance and reliability.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure. The cited prior art discloses similar materials, devices, and methods.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899