Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “wherein the second extending portion of the gate trench portion is a dummy gate trench” as recited in claim 27 must be shown or the feature(s) canceled from the claim(s). Specifically, claim 27 is dependent from claim 1 and claim 1 requires a connection portion connecting one end of the first extending portion to a nearest end of the second extending portion, and none of the drawings show this connection portion to a dummy gate trench. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 27 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 27 recites “wherein the second extending portion of the gate trench portion is a dummy gate trench portion and no emitter regions are provided in contact with the second extending portion of the gate trench portion” while claim 1 recites “a connection portion connecting one end of the first extending portion to a nearest end of the second extending portion” and “wherein the first extending portion and the second extending portion of the gate trench portion are both conductively connected to a single, common gate metal layer.” These features were not described in the original disclosure. Appropriate correction is required. No new matter should be entered.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 28 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. claim 28 recites the same limitation that is recited in claim 1. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Naito in US 2019/0051739 A1 (hereinafter Naito).
Regarding claim 9, Naito teaches in the embodiment of FIGS. 15A, 15B and related text, a semiconductor device comprising:
a drift region (18, [0191]) of a first conductivity type (N-type [0190]), provided in a semiconductor substrate (10, [0190]), the semiconductor substrate (10) having an upper surface (21, [0190]);
one or more mesa portions (60, [0184]), each of the one or more mesa portions (60) being defined at least in part by a gate trench portion (40, [0183]) extending into the semiconductor substrate (10) from the upper surface of the semiconductor substrate (21), the gate trench portion (40) of each of the one or more mesa portions (60) comprising a straight, elongated first extending portion (39 left, [0179], see annotated FIG. 15a below), a straight, elongated second extending portion (39 right), annotated FIG. 15a), and a connection portion (41, [0179]) connecting one end of the first extending portion (39 left) to a nearest end of the second extending portion (39 right), wherein the first extending portion (39 left) and the second extending portion (39 right) extend in parallel in an extending direction (x) and the first extending portion (39 left) and the second extending portion (39 right) are spaced apart in a trench array direction (y) that is perpendicular to the extending direction (x), wherein both the trench array direction (y) and the extending direction (x) are parallel to the upper surface of the semiconductor substrate (10, [0067]) wherein each of the first extending portion (39 left) and the second extending portion (39 right) has a length (annotated FIG. 15a), and wherein the first extending portion (39 left) and the second extending portion (39 right) of the gate trench portion (40) are both conductively connected to a single, common gate metal layer (48, [0181]);
a dummy trench portion (30, [0178]) in the form of an elongated, straight dummy trench portion (FIG. 15a) extending in the extending direction (x) provided in each of the one or more mesa portions (60), wherein only a single dummy trench portion (30) is provided in each of the one or more mesa portions (60) intermediate the first extending portion (39 left) and the second extending portion (39 right) of the gate trench portion (40);
a base region (14, [0182]) of a second conductivity type (P-type), provided above the drift region (18) within each of the one or more mesa portions (60);
a first plurality of emitter regions (12, [0182], annotated FIG. 15a) of the first conductivity type (N-type), with a doping concentration higher than the drift region (18, [0101]), provided above the base region (14) in contact with the first extending portion (39 left) of the gate trench portion (40) and distributed along the length (annotated FIG. 15a) of the first extending portion (39 left), each of the first plurality of emitter regions (12) extends from the first extending portion (39 left) of the gate trench portion (40) toward the dummy trench portion (30) and terminates without reaching the second extending portion (39 right) of the gate trench portion (40);
a contact region (15, [0182]) of the second conductivity type (P-type), with a doping concentration higher than the base region (14, [0083]), provided above the base region (14) within each of the one or more mesa portions (60),
wherein within each of the one or more mesa portions (60) between the first extending portion (39 left) of the gate trench portion (40) and the dummy trench portion (30), in cross sections through each of the first plurality of emitter regions (12, see FIG. 15b) parallel to the trench array direction (y), the contact region (15) is provided below a lower end of each of the first plurality of emitter regions (12), extends toward the first extending portion (39 left) of the gate trench portion (40) from a bottom of the lower end of each of the first plurality of emitter regions (12) in the trench array direction (y), is in contact with the dummy trench portion (30), and terminates without reaching the first extending portion (39 left) of the gate trench portion (40).
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Annotated FIGS. 15a and 15b (Naito)
Naito does not explicitly teach in the embodiment of FIGS. 15a/15b, each of the first plurality of emitter regions terminates without reaching the dummy trench portion and wherein the contact region is continuous along the sidewall of the dummy trench portion on the upper surface of the semiconductor substrate.
However, Naito teaches in the embodiment of FIGS. 7a/7b and related text, each of a first plurality of emitter regions (12) terminates without reaching a dummy trench portion (30, see FIG. 6b) in order to improve the saturation current characteristics of the transistor portion ([0149]) and wherein the contact region (15) is continuous along the sidewall of the dummy trench portion (30) on the upper surface of the semiconductor substrate (10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Naito’s device in the embodiment of FIGS. 15a/15b such that each of the first plurality of emitter regions terminates without reaching the dummy trench portion, as taught by Naito in the embodiment of FIGS. 7a/7b, with the purpose of improving the saturation current characteristics of the transistor portion ([0149]).
Regarding claim 10, Naito teaches in the embodiments of FIGS. 15a/15b and 7a/7b the semiconductor device according to claim 9. Naito teaches in the embodiment of FIGS. 15a/15b further comprising:
a second plurality of emitter regions (12, see annotated FIG. 15a in the rejection of claim 9) of the first conductivity type (N-type), with a doping concentration higher than the drift region (18, [0101]), provided above the base region (14) in contact with the second extending portion (39 on right, annotated FIG. 15a) of the gate trench portion (40) and distributed along the length of the second extending portion (39 right), each of the second plurality of emitter regions (12) extends from the second extending portion (39 right) of the gate trench portion (40) toward the dummy trench portion (30);
wherein within each of the one or more mesa portions (60) between the second extending portion (39 right) of the gate trench portion (40) and the dummy trench portion (30), in cross sections through each of the second plurality of emitter regions (12, see FIG. 15b) parallel to the trench array direction (y), the contact region (15) is provided below a lower end of each of the second plurality of emitter regions (12), extends toward the second extending portion (39 right) of the gate trench portion (40) from a bottom of the lower end of each of the second plurality of emitter regions (12) in the trench array direction (y), is in contact with the dummy trench portion (30), and terminates without reaching the second extending portion (39 right) of the gate trench portion (40).
Naito further teaches in the embodiment of FIGS. 7a/7b and related text, each of a second plurality of emitter regions (12) terminates without reaching a dummy trench portion (30, see FIG. 7b) in order to improve the saturation current characteristics of the transistor portion ([0149]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Naito’s device in the embodiment of FIGS. 15a/15b such that each of the second plurality of emitter regions terminates without reaching the dummy trench portion, as taught by Naito in the embodiment of FIGS. 7a/7b, with the purpose of improving the saturation current characteristics of the transistor portion ([0149]).
Regarding claim 11, Naito teaches in the embodiments of FIGS. 15a/15b and 7a/7b the semiconductor device according to claim 10. Naito does not explicitly teach in the embodiment of FIGS. 15a/15b wherein no part of any of the first plurality of emitter regions and no part of any of the second plurality of emitter regions reaches the dummy trench portion.
Naito teaches in the embodiment of FIGS. 7a/7b wherein no part of any of the first plurality of emitter regions (12) and no part of any of the second plurality of emitter regions (12) reaches the dummy trench portion (30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Naito’s device in the embodiment of FIGS. 15a/15b such that no part of any of the first plurality of emitter regions and no part of any of the second plurality of emitter regions reaches the dummy trench portion, as taught by Naito in the embodiment of FIGS. 7a/7b, with the purpose of improving the saturation current characteristics of the transistor portion ([0149]).
Claim 14, 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Naito in US 2019/0051739 A1 (hereinafter Naito) and in view of Naito in US 2018/0337233 (hereafter Naito2).
Regarding claim 14, Naito teaches in the embodiments of FIGS. 15a/15b and 7a/7b the semiconductor device according to claim 9. Naito further teaches in the embodiment of FIGS. 15a/15b wherein the dummy trench portion (30) has a dummy trench dielectric film (32, [0201]) and a dummy trench conductive portion (34, [0201]).
Naito does not explicitly teach that the dummy trench conductive portion is set to be at an emitter potential or a floating potential.
However, Naito2 teaches (Fig. 11 and related text) a semiconductor device (100, [0038]) including a dummy first trench portion (30, [0040]), wherein a dummy trench conductive portion (34, [0082]) is set to be at an emitter potential ([0104]) in an operating mode that reduces power loss at the time of turn-on [0113]).
Naito and Naito2 are analogous art to the claimed invention because they both are directed to trench gate semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Naito in view of Naito2 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to set the dummy trench conductive portion in the device of Naito to be at an emitter potential, as taught by Naito2, in order to operate the device in a manner that reduces power loss at the time of turn-on (Naito2, [0113]). Additionally, in reference to the claim limitation “the dummy trench conductive portion is set to be at an emitter potential or a floating potential”, intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. (MPEP 2114).
Regarding claim 22, Naito teaches in the embodiment of FIGS. 15a/15b/15c and related text, a semiconductor device comprising:
a drift region (18, [0191]) of a first conductivity type (N-type [0190]), provided in a semiconductor substrate (10, [0190]), the semiconductor substrate (10) having an upper surface (21, [0190]);
one or more mesa portions (60, [0184]), each of the one or more mesa portions (60) being defined at least in part by a gate trench portion (40, [0183]) extending into the semiconductor substrate (10);
one or more dummy trench portions (30, [0178]), each of the one or more dummy trench portions (30) being provided in the mesa portion (60), wherein
the gate trench portion (40) and the dummy trench portion (30) extend in an extending direction (x), and are spaced apart in a trench array (y) direction that is perpendicular to the extending direction (x, [0067]),
both the extending direction (x) and the trench array direction (y) are parallel with the upper surface (21) of the semiconductor substrate (10, [0067]),
the gate trench portion (40) is a first gate trench portion (40),
a base region (14, [0182]) of a second conductivity type (P-type), provided above the drift region (18) within each of the one or more mesa portions (60);
a first plurality of emitter regions (12, [0182], annotated FIG. 15a) of the first conductivity type (N-type), with a doping concentration higher than the drift region (18, [0101]), being in contact with the first gate trench portion above the base region (14) and being arranged along the extending direction (x) of the first gate trench portion (40), each of the first plurality of emitter regions (12) extending from the first gate trench portion (40) toward the dummy trench portion (30) in the trench array direction (y) and reaches the dummy trench portion (30) such that each of the first plurality of emitter regions (12) is in contact with both the first gate trench (40) portion and the dummy trench portion (30; see FIG. 15c);
a contact region (15, [0182]) of the second conductivity type (P-type), with a doping concentration higher than the base region (14, [0083]), provided above at least a portion of the base region (14) within each of the one or more mesa portions (60), wherein
in cross sections through each of the first plurality of emitter regions (12, see FIG. 15b) parallel to the trench array direction (y), the contact region (15) is provided below a lower end of each of the first plurality of emitter regions (12), is in contact with the dummy trench portion (30), extends in a direction parallel to the trench array direction toward the first gate trench portion (40), and terminates without reaching the first gate trench portion (40);
an interlayer dielectric film (38, [0190]) provided above a first mesa region (60, see annotated FIG. 15b below), of each of the one or more mesa portions (60), between the first gate trench portion (40) and the dummy trench portion (30), wherein the first gate trench portion (40) is a neighboring first gate trench portion (40) of the dummy trench portion (30) such that no other gate trench portion (40) is located in the first mesa region (60) and no other dummy trench portion (30) is located in the first mesa region (40); and
an emitter electrode (52, [0190]) provided above the interlayer dielectric film (38).
Naito does not explicitly teach a contact trench portion extending into the first plurality of emitter regions from an upper surface of the interlayer dielectric film, wherein the semiconductor substrate is electrically connected to the emitter electrode via the contact trench portion, and the contact trench portion is electrically connected to the contact region below the first plurality of emitter regions.
Naito2 teaches in FIG. 12 and related text, a contact trench portion (55, [0115]) extending into a first emitter region (12, [0116]) from an upper surface of an interlayer dielectric film (38, [0066]), wherein a semiconductor substrate (10, [0066]) is electrically connected to an emitter electrode (52, [0117]) via the contact trench portion (55; first emitter 12 is part of substrate 10 and is electrically connected to emitter electrode 52 via contact trench portion 55), and the contact trench portion (55) is electrically connected to a contact region (15, [0117]) below the first emitter region (12; [0117]).
Naito and Naito2 are analogous art to the claimed invention because they are directed to trench gate semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Naito in view of Naito2 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Naito to include a contact trench portion extending into the first plurality of emitter regions from an upper surface of the interlayer dielectric film, wherein the semiconductor substrate is electrically connected to the emitter electrode via the contact trench portion, and the contact trench portion is electrically connected to the contact region below the first plurality of emitter regions, as taught by Naito2, with the purpose of reducing contact resistance between the emitter regions, contact regions, and emitter electrode (Naito2, [0117]).
Regarding claim 23, as best understood, Naito as modified by Naito2 teach the semiconductor device according to claim 22. Naito further teaches wherein
the contact region (15) includes a first contact region (see annotated FIG. 15a) and a second contact region (annotated FIG. 15a), wherein
in the upper surface (21) of the semiconductor substrate (10), the first contact region (annotated FIG. 15a) and the second contact region (annotated FIG. 15a) are provided separately from each other in the extending direction (x) by the first plurality of emitter regions (12, annotated FIG. 15a), and
in cross sections through each of the first plurality of emitter regions parallel to the trench array direction (FIG. 15b), the first contact region and the second contact region are in contact below a bottom of each of the first plurality of emitter regions (the first contact region and second contact region are both in contact with base region 14 in FIG. 15b and are therefore at least in electrical contact).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Naito in US 2019/0051739 A1 (hereinafter Naito) and in view Matsushita in US 2019/0088769 A1 (hereafter Matsushita).
Regarding claim 26, Naito teaches in the embodiments of FIGS. 15a/15b and 7a/7b the semiconductor device according to claim 9. Naito further teaches in the embodiment of FIGS. 15a/15b wherein the dummy trench portion (30) has a dummy trench dielectric film (32, [0201]) and a dummy trench conductive portion (34, [0201]).
Naito does not explicitly teach wherein the dummy trench portion is a dummy gate trench portion, and the dummy trench conductive portion is set to be at a gate potential.
Matsushita teaches in FIGS. 2A, 2B, and related text, a trench IGBT device [0033] in which a dummy trench portion (52, [0033]) is a dummy gate trench portion (dummy trench portion 52 comprises dummy gate electrode 18, [0033]), and the dummy trench conductive portion (18) is set to be at a gate potential ([0058], Fig. 2B), in order to achieve an IGBT device with high switching speed and low on-resistance ([0006]).
Naito and Matsushita are analogous art to the claimed invention because they both are directed trench gate semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Naito in view of Matsushita because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Naito such that the dummy trench portion is a dummy gate trench portion, and the dummy trench conductive portion is set to be at a gate potential, as taught by Matsushita, in order to achieve an IGBT device with high switching speed and low on-resistance ([0006]). Additionally, in reference to the claim limitation “the dummy trench conductive portion is set to be at a gate potential”, intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. (MPEP 2114).
Allowable Subject Matter
Claims 1-4, 6-8, 12, 15, 24 and 25 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest all of the limitations recited in independent claim 1 or 24. Specifically, Applicant’s arguments on pages 16 and 24 of the remarks received 10/20/2025 are persuasive. Dependent claims 2-4, 6-8, 12, 15 and 25 are allowable because of their dependence from an allowable independent claim.
Response to Arguments
Applicant’s arguments with respect to claim(s) 22, 23 and 25 with respect to the 112 rejections are persuasive and the rejection has been withdrawn.
Applicant’s arguments with respect to claims 1-4, 6-8, 12 and 15 are persuasive and the rejection has been withdrawn.
Applicant’s arguments, see pages 16-17, filed 10/20/2025, and pages 12-13, filed 11/20/2025 with respect to the rejection(s) of claim(s) 9 under obviousness rejection in view of fig 6 of Naito have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of fig 7 of Naito.
Applicant argued with respect to claim 22 that Naito2 says nothing about the contact trench portion connecting to the contact region below the emitter region 12 and study of fig 12 of Naito2 shows that the contact trench portion 55 terminates within the level of the emitter region 12 in elevation and does not extend below the emitter region 12. Therefore, the contact trench portion 55 of Naito2 does not connect to the contact region 15 below the emitter region 12.
Examiner disagrees because fig 12 of Naito2 shows that the trench portion of the emitter electrode 12 is electrically connected to the contact region below the first plurality of emitter regions. Specifically, there is electrical connection to the part of 15 that is below the emitter regions 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 1/26/2026