Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/10/2026 has been entered.
Response to Amendment
The amendment filed 3/10/2026 has been entered. Claims 1-7, 9-11, and 13-22 remain
pending in the application.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Please see Claim Rejections below for details.
Claim Objections
Claim 11 is objected to because of the following informalities: the claim states in part “…from the first side of the dielectric interposer…”. In the view of the Examiner, this should read “…from the first side of the Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US9368440B1 (Hool).
Regarding Claim 1, Hool discloses a microelectronic assembly (Fig. 4, Col. 8, ll. 17-21), comprising: a package substrate (see annotated Fig. 4 below, bottom layer of el. 420, Col. 8, ll. 21-26); an interposer (see annotated Fig. 4 below, top layer of el. 420, Col. 8, ll. 21-26, Examiner is treating the top package layer as the interposer) coupled to the package substrate (Fig. 4, Col. 8, ll. 21-26), the interposer have a first side coupled to the package substrate (see annotated Fig. 4 below) and a second side opposite the first side (see annotated Fig. 4 below), the interposer comprising a dielectric material (Fig. 2C, el. 222, Col. 4, ll. 66-67), a conductive pillar (Fig. 2C, el. 221, Col. 4, ll. 66-67) through the dielectric material (Fig. 2C, Col. 5, ll. 1-3) and a conductive structure (Fig. 2C, el. 223, Col. 5, ll. 1-3) at least partially surrounding the conductive pillar (Fig. 2C, Col. 5, ll. 1-3), the conductive structure separated from the conductive pillar by the dielectric material (Fig. 2C, Col. 5, ll. 1-3), wherein the conductive pillar extends from the first side of the interposer to the second side of the interposer (see annotated Fig. 4 below and Fig. 2C), and the conductive structure extends form the first side of the interposer to the second side of the interposer (see annotated Fig. 4 below and Fig. 2C); and an integrated circuit die (Fig. 4, el. 410, Col. 8, ll. 21-22) coupled to the interposer (Fig. 4, Col. 8, ll. 21-22) on the second side of the interposer (Fig. 4), wherein the conductive pillar couples the IC die conductively to the package substrate (Fig. 4), and the conductive structure is coupled to a ground connection (Col. 5, ll. 34-35).
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Regarding Claim 2, Hool discloses the microelectronic assembly of claim 1, further comprising a plurality of conductive pillars (Fig. 4, els. 430, Col. 8, ll. 26-28).
Regarding Claim 3, Hool discloses the microelectronic assembly of claim 2, wherein the dielectric material around each conductive pillar is completely surrounded by the conductive structure (Fig. 2C, Col. 5, ll. 1-3).
Regarding Claim 10, Hool discloses the microelectronic assembly of claim 1, wherein the conductive structure comprises an electromagnetic shield (Col. 5, ll. 1-10).
Claims 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hool.
Regarding Claim 18, Hool discloses A method for fabricating a microelectronic assembly (Col. 4, ll. 9-11) , the method comprising: providing a package substrate; providing an interposer comprising conductive pillars (Fig. 2D, Col. 5, ll. 42-64), a dielectric material and an electromagnetic shield, the interposer having a first side coupled to the package substrate and a second side opposite the first side (Fig. 2D, Col. 5, ll. 42-64); providing an IC die (Fig. 2J); coupling the IC die to the interposer (Fig. 2J, Col. 7, ll. 27-33) ; and coupling the interposer to the package substrate (see Fig. 4, where the interposer is coupled to the package substrate), wherein: the conductive pillars extend through a thickness from the first side of the interposer to the second side of the interposer (Fig. 2C), the conductive pillars providing a conductive pathway between the IC die and the package substrate, the electromagnetic shield extends from the first side of the interposer to the second side through the thickness of the interposer, the conductive pillars are surrounded by the dielectric material, and the dielectric material is surrounded by the electromagnetic shield.
Regarding Claim 19, further comprising coupling the electromagnetic shield to a ground connection (Col. 5, ll. 34-35)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hool and
US20190385977A1 (Elsherbini).
Regarding Claim 9, Hool discloses the microelectronic assembly of claim 1, wherein the IC die comprises a first IC die (Fig. 4, where there is only one IC die), and the conductive pillar is a
first conductive pillar (Fig. 4, the conductive pillar 430 can be taken as a first conductive pillar).
Hool does not disclose that the interposer further comprises a second IC die
surrounded by the dielectric material, the interposer further comprises a second conductive pillar
between the second IC die and the package substrate, the second conductive pillar couples the second
IC die conductively to the package substrate, the dielectric material surrounds the second conductive
pillar, the conductive structure at least partially surrounds the second conductive pillar, and the
conductive structure is separated from the second conductive pillar by the dielectric material.
Elsherbini discloses a microelectronic assembly (Fig. 10, el. 1700, Para. [0100]) comprising an IC
die (Fig. 10, el. 1714, Para. [0104]) surrounded by dielectric material (Para. [0104]), with a conductive
pillar (Fig. 10, el. 1706, Fig. 10) between the IC die 1714 and a package substrate (Fig. 10, el. 1702, Para.
[0100]), the conductive pillar 1706 couples the IC die 1714 conductively to the package substrate 1702
(see Fig. 10), and the dielectric material surrounds the conductive pillar 1706 (Para. [0104])).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to take the interposer disclosed by Conn in view of Uzoh and add a second IC die with
a second conductive pillar as disclosed by Elsherbini such that the conductive structure is separated
from the second conductive pillar by the dielectric. Doing so would have the benefit of saving space by
including an IC in the interposer instead of on the interposer.
Claim 11, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hool and
Elsherbini.
Regarding Claim 11, Hool discloses an IC package (Fig. 4, Col. 8, ll. 17-21), comprising: a package substrate (see annotated Fig. 4 above, bottom layer of el. 420, Col. 8, ll. 21-26); an interposer (see annotated Fig. 4 above, top layer of el. 420, Col. 8, ll. 21-26, Examiner is treating the top package layer as the interposer) coupled to the package substrate (Fig. 4, Col. 8, ll. 21-26), the interposer having a first side coupled to the package substrate (see annotated Fig. 4 above) and a second side opposite the first side (see annotated Fig. 4 above), the interposer comprising: a dielectric material (Fig. 2C, el. 222, Col. 4, ll. 66-67), a second plurality of conductive pillars (Fig. 4, el. 430, Col. 8, ll. 26-29) through the dielectric material (Fig. 2C), wherein one of the second plurality of conductive pillars extends from the first side of the interposer to the second side of the interposer (see annotated Fig. 4 above); and an electromagnetic shield (Fig. 2C, el. 223, Col. 4, ll. 66-67) at least partially surrounding the conductive pillars of the second plurality of conductive pillars (Fig. 2C, Col. 5, ll. 1-3), the electromagnetic shield separated from the conductive pillars by the dielectric material (Fig. 2C), wherein at least a portion of the electromagnetic shield extends from the first side of the interposer to the second side of the interposer (Fig. 2C); and a second IC die (Fig. 4, el. 410, Col. 8, ll. 21-22) coupled to the second side of the interposer (see annotated Fig. 4 above), wherein: the electromagnetic shield is a conductive structure (Col. 4, ll. 66-67), and the second plurality of conductive pillars conductively couples the second IC die and the package substrate (Fig. 4).
Hool does not disclose that the interposer comprises a first IC die, a first plurality of conductive pillars through the dielectric material, the first plurality of conductive pillars between the first IC die and the package substrate, that the electromagnetic shield at least partially surrounds the conductive pillars of the first plurality of conductive pillars, and that the first plurality of conductive pillars conductively couples the first IC die and the package substrate.
Elsherbini discloses a microelectronic assembly (Fig. 10, el. 1700, Para. [0100]) comprising an IC
die (Fig. 10, el. 1714, Para. [0104]) surrounded by dielectric material (Para. [0104]), with a conductive
pillar (Fig. 10, el. 1706, Fig. 10) between the IC die 1714 and a package substrate (Fig. 10, el. 1702, Para.
[0100]), the conductive pillar 1706 couples the IC die 1714 conductively to the package substrate 1702
(see Fig. 10), and the dielectric material surrounds the conductive pillar 1706 (Para. [0104])).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to take the interposer disclosed by Conn in view of Uzoh and add a second IC die with
a second conductive pillar as disclosed by Elsherbini such that the conductive structure is separated
from the second conductive pillar by the dielectric. Doing so would have the benefit of saving space by
including an IC in the interposer instead of on the interposer.
Regarding Claim 16, Hool in view of Elsherbini discloses the IC package of Claim 11, wherein the electromagnetic shield is conductively coupled to a ground connection (Hool, Col. 5, ll. 34-35)
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hool and
Elsherbini.
Regarding Claim 17, Hool in view of Elsherbini disclose sthe IC package of Claim 11.
Hool in view of Elsherbini does not disclose wherein the dielectric material comprises at least one of: epoxy with porous silica fillers, epoxy with fluorinated silica fillers, cyclotene, benzocyclobutene, paraffin, and perfluoroalkyl.
However, Elsherbini further discloses an interposer (Fig. 10, el. 1704) that can be made out of an epoxy resin with inorganic fillers, among other materials (Para. [0104]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to take the IC package disclosed by Conn in view of Uzoh, Kuo and Elsherbini and use
epoxy with porous silica fillers, for example, to make the dielectric. Elsherbini already discloses using
epoxy resin with inorganic fillers, and porous silica filler is a well-known type of inorganic filler that has
the benefit of being stable, durable, and resistant to heat.
Allowable Subject Matter
Claims 4-7, 13-15, and 20-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 4, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination the limitation “the dielectric material around a subset of the conductive pillars is completely surrounded by the conductive structure, and the subset comprises a plurality of mutually adjacent conductive pillars.”
Claims 5-6 are allowable at least because they depend on claim 4.
Regarding Claim 1, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination “wherein the dielectric material comprises: a first dielectric material and a second dielectric material, and the first dielectric material separates the conductive pillar from the second dielectric material.”
Regarding Claim 13, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination the limitation “subsets of the conductive pillars in at least one of the first plurality of conductive pillars and the second plurality of conductive pillars are in respective blocks of the dielectric material, each subset comprises a plurality of mutually adjacent conductive pillars, and the electromagnetic shield separates the respective blocks of the dielectric material.”
Claims 14-15 are allowable at least because they depend on claim 13.
Regarding Claim 20, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination the limitation “further comprising sending high-speed signals having a frequency greater than 10 GHz through the conductive pillars.”
Regarding Claim 21, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination the limitation “wherein the conductive pillar comprises a first portion and a second portion, the first portion having a different diameter than the second portion.”
Regarding Claim 22, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination the limitation “wherein the conductive pillar has a diameter between 60 and 70 micrometers.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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