DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 6/23/2022. Claims 1-17 are currently pending, of which claims 1-17 are currently rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (U.S. Patent Application Publication No.: US 20200065650 A1) (cited in IDS on 01/11/2023), hereinafter “Tran”, in view of Myung et al. (U.S. Patent Application Publication No.: US 20210303266 A1), hereinafter “Myung”.
Regarding Claim 1, Tran teaches:
A system comprising:
a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns (Fig. 7, e.g., Non-Volatile Memory array 33; ¶0071; Fig. 9, e.g., shows memory cells arranged in rows and columns);
a capacitor comprising a first terminal and a second terminal, the second terminal coupled to a common potential (Fig. 34, e.g., shows capacitor 3453 with a first terminal connected to the output of the switch 3452, and a second terminal connected to ground (common potential));
… enable an application of an input signal to the first terminal of the capacitor (Fig. 34, e.g., switch 3452 controls current going to the first terminal of the capacitor 3453) … ; and
a buffer coupled to the first terminal of the capacitor, the buffer to generate an output voltage for a respective row of the vector by matrix multiplication array (Fig. 34, e.g., shows Op amp 3454 (buffer) coupled to the first terminal of the capacitor; ¶0167).
Tran does not teach:
a row decoder to enable an application of an input signal to the first terminal of the capacitor in response to an address;
However, Myung teaches:
a row decoder to enable an application of an input signal to the first terminal of the capacitor in response to an address (¶0175, e.g., row decoder 530 controls switch based on a row address; Fig. 14);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the row decoder 530 receiving a row address and controlling the switch as taught by Myung with the S/H circuit as taught by Tran. One would have been motivated to combine these references because both references disclose Compute in-memory arrays, and Myung enhances the model of Tran by allowing for the control of switches in the S/H circuit.
Regarding Claim 2, Tran in view of Myung teach:
The system of claim 1, wherein the row decoder enables the input signal by closing a switch with an output of the row decoder, wherein the switch, in a closed position, couples an input neuron current as the input signal to the first terminal of the capacitor (Tran: Fig. 34, e.g., switch 3452 controls current going to the first terminal of the capacitor 3453; Myung: ¶0175, e.g., row decoder 530 controls switch based on a row address; Fig. 14); and
wherein the row decoder disables the input signal by opening the switch with the output of the row decoder, wherein the switch, in an open position, disconnects the input neuron current from the first terminal of the capacitor (Tran: Fig. 34, e.g., switch 3452 controls current going to the first terminal of the capacitor 3453; Myung: ¶0175, e.g., row decoder 530 controls switch based on a row address; Fig. 14).
The motivation to combine provided with respect to claim 1 applies equally to claim 2.
Regarding Claim 3, Tran in view of Myung teach:
The system of claim 2, wherein the input neuron current is received from a neural network array (Tran: ¶0152, e.g., Activation function circuit can receive maximum neuron current that can be received from the attached VMM (not shown); ¶0167, e.g., S/H circuit can be used with activation circuit).
Regarding Claim 4, Tran in view of Myung teach:
The system of claim 2, wherein the input neuron current is a scaled current based on a current received from a neural network array (Tran: ¶0152, e.g., output of the attached VMM array can be the input of the VMM array, hence the current is scaled).
Regarding Claim 6, Tran in view of Myung teach:
The system of claim 1, wherein the plurality of non-volatile memory cells comprises stacked-gate flash memory cells (Tran: ¶0061, e.g., stacked gate flash memory cell is shown in Fig. 5).
Regarding Claim 7, Tran in view of Myung teach:
The system of claim 1, wherein the plurality of non-volatile memory cells comprises split-gate flash memory cells (Tran: ¶0057, e.g., split gate memory cells are other types of flash memory cells).
Regarding Claim 8, Tran teaches:
A system comprising:
a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns (Fig. 7, e.g., Non-Volatile Memory array 33; ¶0071; Fig. 9, e.g., shows memory cells);
a switch to switchably couple a respective input to a respective row of the vector by matrix multiplication array (Fig. 34, e.g., switch 3452 controls current going to the first terminal of the capacitor 3453); and
… enabling the switch … so as to couple the respective input to the respective row of the vector by matrix multiplication array (Fig. 34, e.g., switch 3452 controls current going to the first terminal of the capacitor 3453).
Tran does not teach:
a row decoder for enabling the switch in response to an address so as to couple the respective input to the respective row of the vector by matrix multiplication array.
However, Myung teaches:
a row decoder for enabling the switch in response to an address so as to couple the respective input to the respective row of the vector by matrix multiplication array (¶0175, e.g., row decoder 530 controls switch based on a row address; Fig. 14).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the row decoder 530 receiving a row address and controlling the switch as taught by Myung with the S/H circuit as taught by Tran. One would have been motivated to combine these references because both references disclose Compute in-memory arrays, and Myung enhances the model of Tran by allowing for the control of switches in the S/H circuit.
Regarding Claim 9, Tran in view of Myung teach:
The system of claim 8, wherein the respective input is received from a neural network array (Tran: ¶0152, e.g., Activation function circuit can receive maximum neuron current that can be received from the attached VMM (not shown); ¶0167, e.g., S/H circuit can be used with activation circuit).
Regarding Claim 10, Tran in view of Myung teach:
The system of claim 8, wherein the respective input is applied to control gate terminals of non-volatile memory cells in the respective row (Tran: ¶0088, e.g., control gate can be used as input of the memory cell).
Regarding Claim 11, Tran in view of Myung teach:
The system of claim 8, wherein the plurality of non-volatile memory cells comprises stacked-gate flash memory cells (Tran: ¶0061, e.g., stacked gate flash memory cell is shown in Fig. 5).
Regarding Claim 12, Tran in view of Myung teach:
The system of claim 8, wherein the plurality of non-volatile memory cells comprises split-gate flash memory cells (Tran: ¶0057, e.g., split gate memory cells are other types of flash memory cells).
Regarding Claims 13-14 and 16-17, they are method claims practiced by the apparatus of claims 1, 3, and 6-7. They are rejected for the same reasons as claims 1, 3, and 6-7.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tran in view of Myung, further in view of Willy McAllister in NPL: “Linearity of electronic components” (https://spinningnumbers.org/a/linearity-RLC.html), hereinafter “McAllister”.
Regarding Claim 5, Tran in view of Myung teach:
The system of claim 2, wherein the output voltage is generated … by the switch and the capacitor (Tran: Fig. 34, e.g., Switch 3452 and capacitor 3453 output current to op amp 3454, which outputs Vout).
Tran in view of Myung do not teach:
wherein the output voltage is generated according to a linear function performed on the input neuron current by the switch and the capacitor.
However, McAllister teaches how a capacitor is a linear electrical component. McAllister explains “The capacitor law can be graphed as a straight line with dv/dt as the horizontal axis and i as the vertical axis. The slope of the capacitor line is C.” (McAllister: “Capacitors and inductors” section)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the capacitor performing a linear function as taught by McAllister with capacitor 3453 as taught by Tran in view of Myung. One would have been motivated to combine these references because both references disclose the use of capacitors, and McAllister enhances the model of Tran in view of Myung because “Circuit made from linear elements can be solved exactly.” (McAllister: “Capacitors and inductors” section, Second to last paragraph.)
Regarding Claim 15, it is a method claim practiced by the apparatus of claim 5. It is rejected for the same reasons as claim 5.
Prior Art Made of Record
US 10943652 B2 – teaches an array of RM devices to compute dot-product, which includes a row pulse decoder, an address counter, and column counter. See Fig. 2 and corresponding description.
US 20210224185 A1 – teaches PIM block 100 that includes a memory cell array 110, a block controller 120, a block row driver 131, and a block column driver 132. See Fig. 1 and corresponding description.
Conclusion
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182