DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is final and is in response to the claims filed 5/29/2022. Claims 1-17 are currently pending, of which claims 1-17 are currently rejected.
Response to Arguments
Applicant's arguments filed 05/29/2026 have been fully considered, but they are not persuasive.
35 U.S.C. 103: Applicant’s arguments regarding the 35 U.S.C. 103 rejection have been fully considered, but they are not persuasive.
Applicant argues in pages 5-6 that Tran in view of Myung do not teach amended claims 1 and 13, and independent claim 8. Applicant explains “The combination of Tran and Myung do not disclose this limitation. In Tran, buffer 3454 in Figure 34 is not coupled to a row of a vector by multiplication array and buffer 3454 therefore does not apply a voltage to the row. Tran explains, "FIG. 34 depicts current sample and hold S/H circuit 3400 and voltage sample and hold S/H circuit 3450....Op amp 3454 is used to buffer the S/H voltage on the capacitor 3453. S/ H circuits 3400 and 3450 can be used with the output summer circuits and/or activation circuits described herein." Tran at paragraph [0167]. This circuit in Tran is used to receive an output from the array and not to apply a voltage as an input to a row of the array as required by claims 1 and 13.” Applicant relies on this same argument for the limitation “a switch to switchably couple a respective input to a respective row of the vector by matrix multiplication array; and a row decoder for enabling the switch in response to an address so as to couple the respective input to the respective row of the vector by matrix multiplication array” of claim 8.
Examiner respectfully disagrees. Applicant points out how Tran does not teach said limitations of claims 1, 8, and 13. However, Applicant does not address the combination of Tran in view of Myung, where the combination would cause for the S/H circuit taught by Tran to be used in the row decoder taught by Myung. Tran envisions using the sample and hold circuit in multiple locations of the system, as Tran explains “S/H circuits 3400 and 3450 can be used with the output summer circuits and/or activation circuits described herein.” See 35 USC 103 rejection below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (U.S. Patent Application Publication No.: US 20200065650 A1) (cited in IDS on 01/11/2023), hereinafter “Tran”, in view of Myung et al. (U.S. Patent Application Publication No.: US 20210303266 A1), hereinafter “Myung”.
Regarding Claim 1, Tran teaches:
A system comprising:
a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns (Fig. 7, e.g., Non-Volatile Memory array 33; ¶0071; Fig. 9, e.g., shows memory cells arranged in rows and columns);
a capacitor comprising a first terminal and a second terminal, the second terminal coupled to a common potential (Fig. 34, e.g., shows capacitor 3453 with a first terminal connected to the output of the switch 3452, and a second terminal connected to ground (common potential));
… enable an application of an input signal to the first terminal of the capacitor (Fig. 34, e.g., switch 3452 controls current going to the first terminal of the capacitor 3453) … ; and
a buffer comprising an input node coupled to the first terminal of the capacitor and an output node … , the buffer to generate an output voltage and to apply the voltage by the output node … (Fig. 34, e.g., shows Op amp 3454 (buffer) coupled to the first terminal of the capacitor; ¶0167).
Tran does not teach:
a row decoder to enable an application of an input signal to the first terminal of the capacitor in response to an address; and
a buffer comprising an input node coupled to the first terminal of the capacitor and an output node coupled to a row of the vector by matrix multiplication array , the buffer to generate an output voltage and to apply the voltage by the output node and to apply the voltage by the output node to the row of the vector by matrix multiplication array.
However, Myung teaches:
a row decoder to enable an application of an input signal to the first terminal of the capacitor in response to an address (¶0175, e.g., row decoder 530 controls switch based on a row address; Fig. 14);
Tran further explains in ¶0167 “S/H circuits 3400 and 3450 can be used with the output summer circuits and/or activation circuits described herein.” Hence, Tran envisions using the sample and hold circuit in multiple locations of the system.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the row decoder 530 receiving a row address and controlling the switch as taught by Myung with the S/H circuit as taught by Tran. One would have been motivated to combine these references because both references disclose Compute in-memory arrays, and Myung enhances the model of Tran by allowing for the control of switches in the S/H circuit. Combination would cause for the S/H circuit taught by Tran to be used in the row decoder as taught by Myung, and would allow for the controlling of the switch within the sample and hold circuit to provide inputs to respective rows of the array.
Regarding Claim 2, Tran in view of Myung teach:
The system of claim 1, wherein the row decoder enables the input signal by closing a switch with an output of the row decoder, wherein the switch, in a closed position, couples an input neuron current as the input signal to the first terminal of the capacitor (Tran: Fig. 34, e.g., switch 3452 controls current going to the first terminal of the capacitor 3453; Myung: ¶0175, e.g., row decoder 530 controls switch based on a row address; Fig. 14); and
wherein the row decoder disables the input signal by opening the switch with the output of the row decoder, wherein the switch, in an open position, disconnects the input neuron current from the first terminal of the capacitor (Tran: Fig. 34, e.g., switch 3452 controls current going to the first terminal of the capacitor 3453; Myung: ¶0175, e.g., row decoder 530 controls switch based on a row address; Fig. 14).
The motivation to combine provided with respect to claim 1 applies equally to claim 2.
Regarding Claim 3, Tran in view of Myung teach:
The system of claim 2, wherein the input neuron current is received from a neural network array (Tran: ¶0152, e.g., Activation function circuit can receive maximum neuron current that can be received from the attached VMM (not shown); ¶0167, e.g., S/H circuit can be used with activation circuit).
Regarding Claim 4, Tran in view of Myung teach:
The system of claim 2, wherein the input neuron current is a scaled current based on a current received from a neural network array (Tran: ¶0152, e.g., output of the attached VMM array can be the input of the VMM array, hence the current is scaled).
Regarding Claim 6, Tran in view of Myung teach:
The system of claim 1, wherein the plurality of non-volatile memory cells comprises stacked-gate flash memory cells (Tran: ¶0061, e.g., stacked gate flash memory cell is shown in Fig. 5).
Regarding Claim 7, Tran in view of Myung teach:
The system of claim 1, wherein the plurality of non-volatile memory cells comprises split-gate flash memory cells (Tran: ¶0057, e.g., split gate memory cells are other types of flash memory cells).
Regarding Claim 8, Tran teaches:
A system comprising:
a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns (Fig. 7, e.g., Non-Volatile Memory array 33; ¶0071; Fig. 9, e.g., shows memory cells);
a switch to switchably couple a respective input to a respective row of the vector by matrix multiplication array (Fig. 34, e.g., switch 3452 controls current going to the first terminal of the capacitor 3453); and
… enabling the switch … so as to couple the respective input to the respective row of the vector by matrix multiplication array (Fig. 34, e.g., switch 3452 controls current going to the first terminal of the capacitor 3453).
Tran does not teach:
a row decoder for enabling the switch in response to an address so as to couple the respective input to the respective row of the vector by matrix multiplication array.
However, Myung teaches:
a row decoder for enabling the switch in response to an address so as to couple the respective input to the respective row of the vector by matrix multiplication array (¶0175, e.g., row decoder 530 controls switch based on a row address; Fig. 14).
Tran further explains in ¶0167 “S/H circuits 3400 and 3450 can be used with the output summer circuits and/or activation circuits described herein.” Hence, Tran envisions using the sample and hold circuit in multiple locations of the system.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the row decoder 530 receiving a row address and controlling the switch as taught by Myung with the S/H circuit as taught by Tran. One would have been motivated to combine these references because both references disclose Compute in-memory arrays, and Myung enhances the model of Tran by allowing for the control of switches in the S/H circuit. Combination would cause for the S/H circuit taught by Tran to be used in the row decoder as taught by Myung, and would allow for the controlling of the switch within the sample and hold circuit to provide inputs to respective rows of the array.
Regarding Claim 9, Tran in view of Myung teach:
The system of claim 8, wherein the respective input is received from a neural network array (Tran: ¶0152, e.g., Activation function circuit can receive maximum neuron current that can be received from the attached VMM (not shown); ¶0167, e.g., S/H circuit can be used with activation circuit).
Regarding Claim 10, Tran in view of Myung teach:
The system of claim 8, wherein the respective input is applied to control gate terminals of non-volatile memory cells in the respective row (Tran: ¶0088, e.g., control gate can be used as input of the memory cell).
Regarding Claim 11, Tran in view of Myung teach:
The system of claim 8, wherein the plurality of non-volatile memory cells comprises stacked-gate flash memory cells (Tran: ¶0061, e.g., stacked gate flash memory cell is shown in Fig. 5).
Regarding Claim 12, Tran in view of Myung teach:
The system of claim 8, wherein the plurality of non-volatile memory cells comprises split-gate flash memory cells (Tran: ¶0057, e.g., split gate memory cells are other types of flash memory cells).
Regarding Claims 13-14 and 16-17, they are method claims practiced by the apparatus of claims 1, 3, and 6-7. They are rejected for the same reasons as claims 1, 3, and 6-7.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tran in view of Myung, further in view of Willy McAllister in NPL: “Linearity of electronic components” (https://spinningnumbers.org/a/linearity-RLC.html), hereinafter “McAllister”.
Regarding Claim 5, Tran in view of Myung teach:
The system of claim 2, wherein the voltage is generated … by the switch and the capacitor (Tran: Fig. 34, e.g., Switch 3452 and capacitor 3453 output current to op amp 3454, which outputs Vout).
Tran in view of Myung do not teach:
wherein the output voltage is generated according to a linear function performed on the input neuron current by the switch and the capacitor.
However, McAllister teaches how a capacitor is a linear electrical component. McAllister explains “The capacitor law can be graphed as a straight line with dv/dt as the horizontal axis and i as the vertical axis. The slope of the capacitor line is C.” (McAllister: “Capacitors and inductors” section)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the capacitor performing a linear function as taught by McAllister with capacitor 3453 as taught by Tran in view of Myung. One would have been motivated to combine these references because both references disclose the use of capacitors, and McAllister enhances the model of Tran in view of Myung because “Circuit made from linear elements can be solved exactly.” (McAllister: “Capacitors and inductors” section, Second to last paragraph.)
Regarding Claim 15, it is a method claim practiced by the apparatus of claim 5. It is rejected for the same reasons as claim 5.
Prior Art Made of Record
US 20220027130 A1 – teaches using row drivers used to drive time-based signals to each row. See Fig. 7 and ¶0074. This row drivers are pertinent to the row decoders of the instant application shown in Figures 35A-37.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS H DE LA GARZA whose telephone number is (571)272-0474. The examiner can normally be reached Monday-Friday 9:30AM-6PM.
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182 /EMILY E LAROCQUE/Primary Examiner, Art Unit 2182 /EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
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