Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Response to Arguments
Applicant’s arguments with respect to claim(s) #1, 8 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) #1, 7, 8, 13, 15, 16, 20, 21, 24, 25, is/are rejected under 35 U.S.C. 102(a)(2) as being unpatentable by Loubet (U.S. Pub. No, 2023/0411531), hereinafter referred to as "Loubet".
Loubet shows, with respect to claim #1 and 7, an integrated circuit comprising: a substrate (fig. #2a, item 206) having a (110) crystallographic surface orientation (paragraph 0050-0051); a first semiconductor device (Below, fig. #Ex1, item BD1) on the substrate, the first semiconductor device (bodies consisting of SiGe; paragraph 0072) having one or more first bodies (Below, fig. #Ex1, item 244) of semiconductor material extending in a first direction from a first source (Below, fig. #Ex1, item SO) region to a first drain region (Below, fig. #Ex1, item DR) (paragraph 0083); a second semiconductor device (Below, fig. #Ex1, item BD2) on the substrate, the second semiconductor device having one or more second bodies (Below, fig. #Ex1, item 246) of semiconductor material extending in the first direction from a second source region to a second drain region (paragraph 0083); a first gate structure (Below, fig. #Ex1, item GT1) at least partially around the one or more first bodies (Below, fig. #Ex1, item 244) of semiconductor material and extending length wise along a second direction orthogonal to the first direction; and a second gate structure (Below, fig. #Ex1, item GT2) at least partially around the one or more second bodies (Below, fig. #Ex1, item 246) of semiconductor material and extending lengthwise along the second direction; wherein the one or more first bodies of semiconductor material and the one or more second bodies of semiconductor material have a (110) crystallographic surface orientation along surfaces that are parallel with a plane extending along the first direction and the second direction (paragraph 0045-0046), and wherein the first semiconductor device is an n-channel device and the second semiconductor device is a p-channel device (paragraph 0045-0046).
[AltContent: textbox (Gate; GT2)][AltContent: textbox (Gate; GT1)]
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[AltContent: textbox (Spacer; SP)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Drain; DR)][AltContent: arrow][AltContent: arrow][AltContent: connector][AltContent: arrow][AltContent: arrow][AltContent: textbox (Body #2; BD2)][AltContent: textbox (Body #1; BD1)][AltContent: textbox (Source; SO)][AltContent: arrow][AltContent: arrow][AltContent: connector][AltContent: ][AltContent: textbox (Channel; CH)][AltContent: textbox (Ex1)]
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Loubet shows, with respect to claim #8, an electronic device, comprising: a chip package comprising one or more dies, at least one of the one or more dies comprising a substrate (fig. #2a, item 206) having a (110) crystallographic surface orientation (paragraph 0050-0051); a first semiconductor device (Above, fig. #Ex1, item BD1) on the substrate, the first semiconductor device (bodies consisting of SiGe; paragraph 0072) having one or more first semiconductor nanoribbons (Above, fig. #Ex1, item 244) extending in a first direction from a first source region to a first drain region (paragraph 0043); a second semiconductor device (Above, fig. #Ex1, item BD2) on the substrate, the second semiconductor device having one or more second semiconductor nanoribbons (Above, fig. #Ex1, item 246) extending in the first direction from a second source region to a second drain region (paragraph 0043, 0083) and a first gate structure (Above, fig. #Ex1, item GT1) at least partially around the one or more first semiconductor nanoribbons (Above, fig. #Ex1, item 244) and extending lengthwise along a second direction orthogonal to the first direction; and a second gate structure (Above, fig. #Ex1, item GT2) at least partially around the one or more second semiconductor nanoribbons (Above, fig. #Ex1, item 246) and extending lengthwise along the second direction, wherein the first semiconductor device is an n-channel device and the second semiconductor device is a p-channel device, and wherein the first source region and the first drain region do not have visible crystal facets along a first cross-section through the first source region and the first drain region, and the second source region and the second drain region do not have visible crystal facets along a second cross- section through the second source region and the second drain region, each of the first cross-section and the second cross-section extending along the first direction and a third direction, the third direction being orthogonal to both the first direction and the second direction (paragraph 0045-0046).
Loubet shows, with respect to claim #13, a device, wherein the n-channel device is an n- type metal oxide semiconductor (NMOS) device, and the p-channel device is a p-type metal oxide semiconductor (PMOS) device, and wherein the first gate structure includes a first gate dielectric (BDI, fig. #2j ,item 238) (paragraph 0071, 0081) on each of the one or more first semiconductor nanoribbons and a first gate electrodes on the first gate dielectric, and the second gate structure includes a second gate dielectric on each of the one or more second semiconductor nanoribbons and a second gate electrode on the second gate dielectric (paragraph 0042, 0066, 0071)
Loubet shows, with respect to claim #15 and 20, integrated circuit comprising: an n-channel semiconductor device having one or more first semiconductor nanoribbons extending in a first direction between a first source region and a first drain region; p-channel semiconductor device having one or more second semiconductor nanoribbons extending in the first direction between a second source region and a second drain region (paragraph 0042-0043); first spacer (fig. #2J, item 238) structure that extends lengthwise in a second direction orthogonal to the first direction and around first ends of the one or more first and second semiconductor nanoribbons (paragraph 0081); and a second spacer structure that extends lengthwise in the second direction parallel with the first spacer structure and around second ends of the one or more first and second semiconductor nanoribbons (paragraph 0081); and, gate structure (Above, fig. #Ex1, item GT1) at least partially around the one or more semiconductor nanoribbons (Below, fig. #Ex1, item 244) and between the first and second spacer structures; wherein each of the one or more first semiconductor nanoribbons and one or more second semiconductor nanoribbons has a (110) crystallographic surface orientation along surfaces that are parallel with a plane extending in the first direction and the second direction, (paragraph 0045-0046).
Loubet shows, with respect to claim #16, an electronic device, comprising: further comprising a substrate having a (110) crystallographic surface orientation (paragraph 0045-0046).
Loubet shows, with respect to claim #21, a device wherein the second source region and the second drain region do not have visible crystal facets (Above, fig. #Ex1, item 244, 246) along a cross-section through the second source region (Above, fig. #Ex1, item SO) and the second drain region (as block by the S/D structures) (Above, fig. #Ex1, item DR), the cross-section extending along the first direction and a third direction, the third direction orthogonal to both the first direction and the second direction (paragraph 0042-0043, 0083).
Loubet shows, with respect to claim #24, a device further comprising: a first gate structure (Below, fig. #Ex1, item GT1) over the one or more first semiconductor nanoribbons (Above, fig. #Ex1, item 244) and between the first spacer structure (Above, fig. #Ex1, item SP) and the second spacer structure; and a second gate structure (Above, fig. #Ex1, item GT2 ) over the one or more second semiconductor nanoribbons and between the first spacer structure and the second spacer structure (paragraph 0043, 0045-0046, 0083).
Loubet shows, with respect to claim #25, a device wherein the first source region and the first drain region do not have visible crystal facets along a first cross-section through the first source (Above, fig. #Ex1, item SO) region and the first drain region (Above, fig. #Ex1, item DR), and the second source region and the second drain region do not have visible crystal facets (as block by the S/D structures) (Above, fig. #Ex1, item 244, 246) along a second cross-section through the second source region and the second drain region, each of the first cross-section and the second cross-section extending along the first direction and a third direction, the third direction being orthogonal to both the first direction and the second direction (paragraph 0042-0043, 0083).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim #2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Loubet (U.S. Pub. No, 2023/0411531), hereinafter referred to as "Loubet", as shown in the rejection of claim #1 above and in view of Kakkad et al., (U.S. Pat. No. 2020/0357638), hereinafter referred to as "Kakkad".
Loubet substantially shows the claimed invention as shown in the rejection of claim #1 above.
Loubet fails to show, with respect to claim #2, a device wherein the first source region and the first drain region do not have visible crystal facets along a cross-section through the first source region and the first drain region, the cross-section extending along the first direction and a third direction, the third direction orthogonal to both the first direction and the second direction.
Kakkad teaches, with respect to claim #2, a device wherein the first source region and the first drain region do not have visible crystal facets along a cross-section through the first source region and the first drain region, the cross-section extending along the first direction and a third direction, the third direction orthogonal to both the first direction and the second direction (paragraph 0046-0047).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #2, to modified the invention of Loubet as modified by the invention of Kakkad, which teaches, a device wherein the first source region and the first drain region do not have visible crystal facets along a cross-section through the first source region and the first drain region, the cross-section extending along the first direction and a third direction, the third direction orthogonal to both the first direction and the second direction, to incorporate a structural condition that would reduce the crystallization thermal budget and therefore improve reduction of the crystallization temperature by combining prior art elements according to known methods to improving device performance, as taught by Kakkad.
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Claim #5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Loubet (U.S. Pub. No, 2023/0411531), hereinafter referred to as "Loubet" as shown in the rejection of claim #1 above, and in further view of Balakrishnan et al., (U.S. Pat. No. 2017/0179128), hereinafter referred to as " Balakrishnan ".
Loubet substantially shows the claimed invention as shown in the rejection of claim #1 above.
Loubet, fail to show, with respect to claim #5, a device wherein the first source region and the first drain region do not have visible crystal facets along a cross-section through the first source region and the first drain region, the cross-section extending along the first direction and a third direction, the third direction orthogonal to both the first direction and the second direction.
Balakrishnan teaches, with respect to claim #5, a device further comprising a dielectric spine between the one or more first bodies of semiconductor material and the one or more second bodies of semiconductor material, such that the one or more first bodies of semiconductor material abut a first side of the dielectric spine and the one or more second bodies of semiconductor material abut a second side of the dielectric spine (paragraph 0029).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #5, to modified the invention of Loubet with the invention of Balakrishnan, which teaches, a device further comprising a dielectric spine between the one or more first bodies of semiconductor material and the one or more second bodies of semiconductor material, such that the one or more first bodies of semiconductor material abut a first side of the dielectric spine and the one or more second bodies of semiconductor material abut a second side of the dielectric spine, to incorporate a structural condition that would reduce the crystallization thermal budget and therefore improve reduction of the crystallization temperature by combining prior art elements according to known methods to improving device performance, as taught by Balakrishnan.
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Claim #6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Loubet (U.S. Pub. No, 2023/0411531), hereinafter referred to as "Loubet" as shown in the rejection of claim #1 above, and in view of Dewey et al., (U.S. Pat. No. 2020/0105751), hereinafter referred to as "Dewey".
Loubet substantially shows the claimed invention as shown in the rejection of claim #1 above.
Loubet, fails to show, with respect to claim #6, a device further comprising a dielectric spine between the one or more first bodies of semiconductor material and the one or more second bodies of semiconductor material include nanoribbons or nanosheets.
Dewey teaches, with respect to claim #6, a device further comprising a dielectric spine between the one or more first bodies of semiconductor material (fig. #4a, item 402) and the one or more second bodies of semiconductor material include nanoribbons or nanosheets (paragraph 0009, 0015, 0020, 0042).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #6, to modified the invention of Loubet with the invention of Dewey, which teaches, a device further comprising a dielectric spine between the one or more first bodies of semiconductor material and the one or more second bodies of semiconductor material include nanoribbons or nanosheets, to incorporate a structural condition that would improve the logic transistor density and performance, as taught by Dewey.
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Claim #9, 11, 12, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Loubet (U.S. Pub. No, 2023/0411531), hereinafter referred to as "Loubet" as shown in the rejection of claim #8 above, and in view of Dewey et al., (U.S. Pat. No. 2020/0105751), hereinafter referred to as "Dewey".
Loubet substantially shows the claimed invention as shown in the rejection of claim #8 above.
Loubet, fails to show, with respect to claim #9, a device wherein the one or more first semiconductor nanoribbons have a (110) crystallographic surface orientation along surfaces that are parallel with a plane extending along the first direction and the second direction.
Dewey teaches, with respect to claim #9, a device wherein the one or more first semiconductor nanoribbons have a (110) crystallographic surface orientation along surfaces that are parallel with a plane extending along the first direction and the second direction (paragraph 0020, 0022-0023).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #9, to modified the invention of Loubet with the invention of Dewey, which teaches, a device wherein the one or more first semiconductor nanoribbons have a (110) crystallographic surface orientation along surfaces that are parallel with a plane extending along the first direction and the second direction, to incorporate a structural condition that would improve the logic transistor density and performance, as taught by Dewey.
Loubet substantially shows the claimed invention as shown in the rejection of claim #9 above.
Loubet, fails to show, with respect to claim #11, a device wherein the one or more second semiconductor nanoribbons have a (110) crystallographic surface orientation along surfaces that are parallel with a plane extending along the first direction and the second direction.
Dewey teaches, with respect to claim #11, a device wherein the one or more second semiconductor nanoribbons have a (110) crystallographic surface orientation along surfaces that are parallel with a plane extending along the first direction and the second direction (paragraph 0020, 0022-0023).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #11, to modified the invention of Loubet with the invention of Dewey, which teaches, a device wherein the one or more first semiconductor nanoribbons have a (110) crystallographic surface orientation along surfaces that are parallel with a plane extending along the first direction and the second direction, to incorporate a structural condition that would improve the logic transistor density and performance, as taught by Dewey.
Loubet, fails to show, with respect to claim #12, a device wherein the at least one of the one or more dies further comprises a dielectric spine between the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons, such that the one or more first semiconductor nanoribbons abut a first side of the dielectric spine and the one or more second semiconductor nanoribbons abut a second side of the dielectric spine.
Dewey teaches, with respect to claim #12, a device wherein the at least one of the one or more dies further comprises a dielectric spine (fig. #5a, item 507) between the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons, such that the one or more first semiconductor nanoribbons abut a first side of the dielectric spine and the one or more second semiconductor nanoribbons abut a second side of the dielectric spine (paragraph 0014-0015, 0047, 0049).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #12, to modified the invention of Loubet with the invention of Dewey, which teaches, a device wherein the at least one of the one or more dies further comprises a dielectric spine between the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons, such that the one or more first semiconductor nanoribbons abut a first side of the dielectric spine and the one or more second semiconductor nanoribbons abut a second side of the dielectric spine, to incorporate a structural condition that would improve the logic transistor density and performance, as taught by Dewey.
Loubet, fails to show, with respect to claim #14, a device further comprising a printed circuit board, wherein the chip package is attached to the printed circuit board.
Dewey teaches, with respect to claim #14, a device further comprising a printed circuit board, wherein the chip package is attached to the printed circuit board (paragraph 0065-0066).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #14, to modified the invention of Loubet with the invention of Dewey, which teaches, a device further comprising a printed circuit board, wherein the chip package is attached to the printed circuit board, to incorporate a structural condition that would provide a multiple of connection to various designed parameters, as taught by Dewey.
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Claim #19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Loubet (U.S. Pub. No, 2023/0411531), hereinafter referred to as "Loubet" as shown in the rejection of claim #15 above, and in further view of Balakrishnan et al., (U.S. Pat. No. 2017/0179128), hereinafter referred to as "Balakrishnan".
Loubet substantially shows the claimed invention as shown in the rejection of claim #15 above.
Loubet, fail to show, with respect to claim #19, a device further comprising a dielectric spine between the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons, such that the one or more first semiconductor nanoribbons abut a first side of the dielectric spine and the one or more second semiconductor nanoribbons abut a second side of the dielectric spine.
Balakrishnan teaches, with respect to claim #19, a device further comprising a dielectric spine between the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons, such that the one or more first semiconductor nanoribbons abut a first side of the dielectric spine and the one or more second semiconductor nanoribbons abut a second side of the dielectric spine (paragraph 0029).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #19, to modified the invention of Loubet with the invention of Balakrishnan, which teaches, a device further comprising a dielectric spine between the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons, such that the one or more first semiconductor nanoribbons abut a first side of the dielectric spine and the one or more second semiconductor nanoribbons abut a second side of the dielectric spine, to incorporate a structural condition that would reduce the crystallization thermal budget and therefore improve reduction of the crystallization temperature by combining prior art elements according to known methods to improving device performance, as taught by Balakrishnan.
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Claim #22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Loubet (U.S. Pub. No, 2023/0411531), hereinafter referred to as "Loubet", as shown in the rejection of claim #1 above and in view of PAN et al., (U.S. Pat. No. 2022/0068716), hereinafter referred to as "Pan".
Loubet substantially shows the claimed invention as shown in the rejection of claim #1 above.
Loubet fails to show, with respect to claim #22, a device wherein the n-channel device is an n-type metal oxide semiconductor (NMOS) device, and the p-channel device is a p-type metal oxide semiconductor (PMOS) device and wherein the first gate structure includes a first gate dielectric having a first layer of high-k dielectric material, and the second gate structure includes a second gate dielectric having a second layer of high-k dielectric material
Pan teaches, with respect to claim #22, a device wherein the n-channel device is an n-type metal oxide semiconductor (NMOS) device, and the p-channel device is a p-type metal oxide semiconductor (PMOS) device (paragraph 0022), and wherein the first gate structure includes a first gate dielectric having a first layer of high-k dielectric material (fig. #14a, item 1706) (paragraph 0062), and the second gate structure includes a second gate dielectric having a second layer of high-k dielectric material (paragraph 0048).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #22, to modified the invention of Loubet as modified by the invention of Pan, which teaches, a device wherein the n-channel device is an n-type metal oxide semiconductor (NMOS) device, and the p-channel device is a p-type metal oxide semiconductor (PMOS) device, and wherein the first gate structure includes a first gate dielectric having a first layer of high-k dielectric material, and the second gate structure includes a second gate dielectric having a second layer of high-k dielectric material, to incorporate a structural condition that would allow a higher gate capacitance to be achieved without further reducing the physical thickness of the gate structure, as taught by Pan.
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Claim #23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Loubet (U.S. Pub. No, 2023/0411531), hereinafter referred to as "Loubet", as shown in the rejection of claim #13 above and in view of PAN et al., (U.S. Pat. No. 2022/0068716), hereinafter referred to as "Pan".
Loubet substantially shows the claimed invention as shown in the rejection of claim #13 above.
Loubet fails to show, with respect to claim #23, a device wherein the first gate dielectric includes a first layer of high-k dielectric material, and the second gate dielectric includes a second layer of high-k dielectric material
Pan teaches, with respect to claim #23, a device wherein the first gate dielectric includes a first layer of high-k dielectric material, and the second gate dielectric includes a second layer of high-k dielectric material (paragraph 0048, 0062).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #23, to modified the invention of Loubet as modified by the invention of Pan, which teaches, a device wherein the first gate dielectric includes a first layer of high-k dielectric material, and the second gate dielectric includes a second layer of high-k dielectric material, to incorporate a structural condition that would allow a higher gate capacitance to be achieved without further reducing the physical thickness of the gate structure, as taught by Pan.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
10/05/2026
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
