Listed by the USPTO as STEVENSON, ANDRE C
Tech Center 2800 • Art Units: 2812 2816 2817 2899
This examiner grants 90% of resolved cases
STEVENSON, ANDRE C is assigned to Tech Center 2800 and Art Unit 2812. His profile records 883 resolved cases and an allowance rate of 89.6%. The interview lift is 7.2%, and the median time to allowance is 833 days. The case history shows a strong allowance outcome, while the limited interview measure suggests that interviews are not the principal distinguishing feature of the record.
The leading companies are ASM IP Holding B.V., Samsung Electronics Co., Ltd., and Intel Corporation. The firms are Snell & Wilmer (ASM IP Holding B.V.), SUGHRUE MION, PLLC, and VOLPE KOENIG. Applicants can plan around the reported allowance experience and timing, using interviews selectively rather than treating them as the central prosecution lever.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18734002 | SEMICONDUCTOR PACKAGE | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18660507 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Final Rejection | SAMSUNG ELECTRONICS CO., LTD. |
| 18622131 | WIRE BONDING APPARATUS AND SEMICONDUCTOR PACKAGE MANUFACTURED USING THE SAME | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18770001 | DISPLAY APPARATUS | Non-Final OA | Samsung Display Co., Ltd. |
| 18700286 | Organic Light Emitting Device and Display Apparatus | Final Rejection | BOE Technology Group Co., Ltd. |
| 18228122 | SUBSTRATE PROCESSING METHOD | Final Rejection | ASM IP Holding B.V. |
| 18199018 | SUBSTRATE PROCESSING METHOD | Final Rejection | ASM IP Holding B.V. |
| 17152592 | METHOD FOR DEPOSITION OF SILICON NITRIDE LAYER USING PRETREATMENT, STRUCTURE FORMED USING THE METHOD, AND SYSTEM FOR PERFORMING THE METHOD | Final Rejection | ASM IP Holding B.V. |
| 18734866 | CONDUCTIVE STRUCTURE AND INTERCONNECTS FOR ELECTRICALLY CONNECTING A SUBSTRATE AND AN INTERPOSER | Non-Final OA | QUALCOMM Incorporated |
| 17890005 | INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE POWER DELIVERY FOR MULTI-HEIGHT STANDARD CELL CIRCUITS | Non-Final OA | Intel Corporation |
| 17847555 | MOBILITY IMPROVEMENT IN GATE ALL AROUND TRANSISTORS BASED ON SUBSTRATE ORIENTATION | Final Rejection | Intel Corporation |
| 18177058 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS | Final Rejection | Mitsubishi Electric Corporation |
| 18728625 | SILICON CARBIDE SEMICONDUCTOR DEVICE | Non-Final OA | SUMITOMO ELECTRIC INDUSTRIES, LTD. |
| 18344583 | METHOD FOR FABRICATING ELECTRODE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME | Non-Final OA | SK hynix Inc. |
| 17142641 | DOPED SILICON NITRIDE FOR 3D NAND | Final Rejection | Applied Materials, Inc. |
| 18775706 | VOID ELIMINATION FOR GAP-FILLING IN HIGH-ASPECT RATIO TRENCHES | Non-Final OA | Taiwan Semiconductor Manufacturing Co., Ltd. |
| 18664861 | MEMORY DEVICE INCLUDING CANTILEVERED WORD LINES WITH TAB PORTIONS AND METHODS FOR FORMING THE SAME | Non-Final OA | SANDISK TECHNOLOGIES LLC |
| 18728751 | PEROVSKITE SOLAR CELL AND METHOD FOR PRODUCING SAME | Non-Final OA | HANWHA SOLUTIONS CORPORATION |
| 17941278 | METHOD OF PROCESSING SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING SYSTEM, AND RECORDING MEDIUM | Final Rejection | KOKUSAI ELECTRIC CORPORATION |
| 17881772 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM | Non-Final OA | KOKUSAI ELECTRIC CORPORATION |
| 18655582 | DETECTION USING SEMICONDUCTOR DETECTOR | Non-Final OA | NATIONAL TSING HUA UNIVERSITY |
| 18615918 | CHIP PACKAGE WITH ACTIVE SILICON BRIDGE | Final Rejection | Advanced Micro Devices, Inc. |
| 18559491 | METHOD FOR PROTECTING REACTIVE MATERIALS WITH ATOMICALLY THIN FILM | Non-Final OA | Cornell University |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy89.6% of resolved applications examined by Andre C Stevenson were allowed (883 resolved cases), compared with 82.1% across Art Unit 2812 over the last five years.
This examiner's interview lift is +7.2 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Andre C Stevenson took 833 days on average from filing to allowance.
Andre C Stevenson examines applications in Art Unit 2812 in Tech Center 2800 (Semiconductors, Circuits & Optics).
