DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the second subfin of claims 1, 8 and 15 with a top surface of the second subfin is above the top surface of the dielectric layer must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Note: the examiner suggests adding (a) a figure similar to Fig. 2E’ showing a cross-sectional view across device 103 of Fig. 2E and (b) a figure similar to Fig. 2G’ showing a cross-sectional view across device 103 of Fig. 2G. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: proper antecedent basis must be included in the specification to features related to the second subfin of claims 1, 8 and 15.
The examiner suggests amending the specification to recite the features related to the second subfin of claims 1, 8 and 15. No new matter should be entered.
Claim Objections
Claims are objected to because of the following informalities:
In claim 1, ln. 8, “a first direction” should read –the first direction--.
In claims 2, 6, 10 and 13, “the second direction” should read –a second direction--.
In claims 5 and 12, “the first and second directions” should read –the first direction and a second direction--.
In claim 15, last ln., “the second direction” should read –a second direction--.
In claims 6, 13, and 20, “the region” should read –a region--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-9 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek et al. (of record, US 20190237360 A1) in view of Hsiao et al. (US 20190378934 A1).
Regarding claim 1, Reznicek discloses an integrated circuit (Fig. 8) comprising:
a substrate having a (110) crystallographic surface orientation (105, [0018], “the crystal orientation of the silicon substrate 105 may be {100}, {110}, or {111}”);
a first (left) semiconductor device on the substrate, the first semiconductor device having one or more first bodies of semiconductor material (130a) extending in a first direction (horizontal) from a first source or drain region (170) to a second source of drain region (170);
a second (right) semiconductor device on the substrate, the second semiconductor device having one or more second bodies of semiconductor material (130a) extending in a first direction from the second source or drain region (170) to a third source or drain region (170);
a first (left) gate structure (190/195/197) wrapped around the one or more first bodies of semiconductor material (130a) and a second (right) gate structure wrapped around the one or more second bodies of semiconductor material (Fig. 8);
wherein each of the one or more first bodies of semiconductor material (130a) includes silicon and germanium ([0024], “the nanosheet channel layer(s) 130 can be suitable SiGe layer(s)”).
Reznicek fails to disclose a first subfin of semiconductor material beneath the one or more first bodies of semiconductor material, a second subfin of semiconductor material beneath the one or more second bodies of semiconductor material, and, a dielectric layer adjacent to at least the first subfin, wherein a top surface of the first subfin is below a top surface of the dielectric layer, and a top surface of the second subfin is above the top surface of the dielectric layer.
Hsiao discloses (Fig. 4) a first subfin (100A) of semiconductor material beneath the one or more first bodies of semiconductor material (101A-105A), a second subfin (100b) of semiconductor material beneath the one or more second bodies of semiconductor material (101B-105B), and, a dielectric layer (103) adjacent to at least the first subfin, wherein a top surface of the first subfin (100A/100T) is below a top surface of the dielectric layer, and a top surface of the second subfin (100B/110T) is above the top surface of the dielectric layer (Fig. 4).
It would have been obvious to one of ordinary skill in the art to include the subfin and dielectric arrangement of Hsiao in Reznicek before the effective filing date of the claimed invention so as to prevent thickness variations in nanowires and prevent negative effects of gate control ability (Hsiao, [0012]).
Regarding claim 3, Reznicek/Hsiao discloses the integrated circuit of claim 1, wherein the concentration of germanium in each of the one or more bodies of semiconductor material (130a, SiGe) is substantially consistent along an entire length of that body of semiconductor material in the first direction (no concentration variation disclosed, hence, presumed inherently consistent as claimed. [0024] – “the nanosheet channel layer(s) 130 can be suitable SiGe layer(s)” ).
In the event Reznicek/Hsiao does not meet the claim inherently, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at the claimed concentration arrangement in Reznicek/Hsiao so as to provide a SiGe channel suitable for P-type channel devices since the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 4, Reznicek fails to disclose the integrated circuit of claim 1, wherein the one or more second bodies of semiconductor material include silicon and less than 1 % germanium.
Hsiao discloses wherein the one or more second bodies of semiconductor material (101B-105B) include silicon and less than 1% germanium (“Si nanowires 101B, 102B, 103B, 104B, 105B”; no Ge disclosed).
It would have been obvious to one of ordinary skill in the art to include the material and arrangement of Hsiao in Reznicek before the effective filing date of the claimed invention so as to form complementary devices (NMOS and PMOS) on a common substrate.
Regarding claim 5, Reznicek/Hsiao discloses the integrated circuit of claim 1, wherein any one of the one or more first bodies of semiconductor material (101A-105A) and any one of the one or more second bodies of semiconductor material (101B-105B) are not aligned on a common plane extending in the first and second directions (Figs. 4 and 12).
Regarding claim 6, Reznicek/Hsiao discloses the integrated circuit of claim 1, wherein the first, second and third source or drain regions (170) do not have visible crystal facets when viewed using scanning electron microscopy (SEM) or transmission electron microscopy (TEM) along a cross-section through the region extending along the first direction and a third direction (into the page) that is orthogonal to both the first direction (horizontal) and the second direction (vertical. No facets are disclosed, hence, presumed inherently absent as claimed, Fig. 8)
In the event Reznicek/Hsiao does not meet the claim inherently, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at the claimed absence of facets in Reznicek/Hsiao so as to minimize defect formation in the source/drain and/or channels, and/or so as to achieve proper carrier mobility.
Regarding claim 7, Reznicek/Hsiao fails to disclose a printed circuit board comprising the integrated circuit of claim 1.
However, PCBs are well-know and commonly employed structures to facilitate integration of devices into systems of higher complexity; for example, a computer or a memory system. This is well-known.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to provide a PCB in addition with the IC of claim 1 in the device of Reznicek/Hsiao so as to facilitate integration of devices into systems of higher complexity and/or because the use of conventional materials (PCBs) to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 8, Reznicek discloses an electronic device (Fig. 8), comprising:
a substrate having a (110) crystallographic surface orientation (105, [0018], “the crystal orientation of the silicon substrate 105 may be {100}, {110}, or {111}”);
a first (left) semiconductor device on the substrate, the first semiconductor device having one or more first semiconductor nanoribbons (130a) extending in a first direction (horizontal) between a first source or drain region (170) and a second source of drain region (170);
a second (right) semiconductor device on the substrate, the second semiconductor device having one or more second semiconductor nanoribbons (130a) extending in the first direction from the second source or drain region (170) to a third source or drain region (170);
a first (left) gate structure (190/195/197) around the one or more first semiconductor nanoribbons (130a) and a second (right) gate structure around the one or more second semiconductor nanoribbons (Fig. 8);
wherein each of the one or more first semiconductor nanoribbons (130a) includes silicon and germanium ([0024], “the nanosheet channel layer(s) 130 can be suitable SiGe layer(s)”).
The examiner takes the position that the term “nanoribbons” does not impart a structural different to the claim and that 130a meet said limitation.
However, in the event a structural difference exists, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include nanoribbons as claimed and apply said structure to 130a of Reznicek so as to allow for high density integration and scaling of transistors and/or because the use of conventional materials (nanoribbons) to perform their known function is prima-facie obvious (MPEP 2144.07).
Reznicek fails to disclose a chip package comprising one or more dies, at least one of the one or more dies comprising the claimed electronic device.
However, packaged die(s) are well-know and commonly employed structures to facilitate integration of devices into systems of higher complexity; for example, a computer or a memory system. This is well-known.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to provide a packaged die(s) as claimed in the device of Reznicek so as to facilitate integration of devices into systems of higher complexity and/or because the use of conventional materials (packages and die(s)) to perform their known function is prima-facie obvious (MPEP 2144.07).
Furthermore, Reznicek fails to disclose a first subfin of semiconductor material beneath the one or more first semiconductor nanoribbons, a second subfin of semiconductor material beneath the one or more second semiconductor nanoribbons, and, a dielectric layer adjacent to at least the first subfin, wherein a top surface of the first subfin is below a top surface of the dielectric layer, and a top surface of the second subfin is above the top surface of the dielectric layer.
Hsiao discloses (Fig. 4) a first subfin (100A) of semiconductor material beneath the one or more first semiconductor nanoribbons (101A-105A), a second subfin (100b) of semiconductor material beneath the one or more second semiconductor nanoribbons (101B-105B), and, a dielectric layer (103) adjacent to at least the first subfin, wherein a top surface of the first subfin (100A/100T) is below a top surface of the dielectric layer, and a top surface of the second subfin (100B/110T) is above the top surface of the dielectric layer (Fig. 4).
It would have been obvious to one of ordinary skill in the art to include the subfin and dielectric arrangement of Hsiao in Reznicek before the effective filing date of the claimed invention so as to prevent thickness variations in nanowires and prevent negative effects of gate control ability (Hsiao, [0012]).
Regarding claim 9, Reznicek/Hsiao discloses the electronic device of claim 8, wherein the one or more semiconductor nanoribbons (130a) include silicon and germanium (SiGe) along an entire length of the one or more semiconductor nanoribbons in the first direction (no concentration variation disclosed, hence, presumed inherently consistent as claimed. [0024] – “the nanosheet channel layer(s) 130 can be suitable SiGe layer(s)” ).
In the event Reznicek/Hsiao does not meet the claim inherently, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at the claimed concentration arrangement in Reznicek/Hsiao so as to provide a SiGe channel suitable for P-type channel devices since the use the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 11, Reznicek fails to disclose the electronic device of claim 8, wherein the one or more second semiconductor nanoribbons include silicon and less than 1 % germanium.
Hsiao discloses wherein the one or more second semiconductor nanoribbons (101B-105B) include silicon and less than 1% germanium (“Si nanowires 101B, 102B, 103B, 104B, 105B”; no Ge disclosed).
It would have been obvious to one of ordinary skill in the art to include the material and arrangement of Hsiao in Reznicek before the effective filing date of the claimed invention so as to form complementary devices (NMOS and PMOS) on a common substrate.
Regarding claim 12, Reznicek/Hsiao discloses the electronic device of claim 8, wherein any one of the one or more first semiconductor nanoribbons (101A-105A) and any one of the one or more second semiconductor nanoribbons (101B-105B) are not aligned on a common plane extending in the first and second directions (Figs. 4 and 12).
Regarding claim 13, Reznicek/Hsiao discloses the electronic device of claim 8, wherein the first, second and third source or drain regions (170) do not have visible crystal facets when viewed using scanning electron microscopy (SEM) or transmission electron microscopy (TEM) along a cross-section through the region extending along the first direction and a third direction (into the page) that is orthogonal to both the first direction (horizontal) and the second direction (vertical. No facets are disclosed, hence, presumed inherently absent as claimed, Fig. 8)
In the event Reznicek/Hsiao does not meet the claim inherently, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at the claimed absence of facets in Reznicek/Hsiao so as to minimize defect formation in the source/drain and/or channels, and/or so as to achieve proper carrier mobility.
Regarding claim 14, Reznicek/Hsiao fails to disclose the electronic device of claim 8, further comprising a printed circuit board, wherein the chip package is attached to the printed circuit board.
However, PCBs are well-know and commonly employed structures to facilitate integration of devices into systems of higher complexity; for example, a computer or a memory system. This is well-known.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to provide a PCB and arrive at the claimed configuration in the device of Reznicek/Hsiao so as to facilitate integration of devices into systems of higher complexity and/or because the use of conventional materials (PCBs) to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 2, 4-5, 10-12 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek et al. (of record, US 20190237360 A1) in view Hsiao et al. (US 20190378934 A1) and Cheng et al. (of record, US 20170062428 A1).
Regarding claims 2 and 10, Reznicek/Hsiao fails to disclose (claim 2) the integrated circuit of claim 1, wherein the one or more bodies of first semiconductor material and the one or more bodies of second semiconductor material have a (110) crystallographic surface orientation along surfaces that are parallel with a plane extending in the first direction and the second direction and (claim 10) the electronic device of claim 8, wherein the one or more first
semiconductor nanoribbons and the one or more second semiconductor nanoribbons have a (110) crystallographic surface orientation along surfaces that are parallel with a plane extending in the first direction and the second direction.
Cheng discloses (claim 2) wherein the one or more bodies of first semiconductor material and the one or more bodies of second semiconductor material (16S and 18S) have a (110) crystallographic surface orientation along surfaces that are parallel with a plane extending in the first direction (horizontal) and the second direction (into page, Fig. 5, [0019] “For example, the crystal orientation of the handle substrate 10 and/or the first SiGe layer 14 may be {100}, {110}, or {111}”, [0026-0027]) and (claim 10) the electronic device of claim 8, wherein the one or more first semiconductor nanoribbons and the one or more second semiconductor nanoribbons (16S and 18S) have a (110) crystallographic surface orientation along surfaces that are parallel with a plane extending in the first direction (horizontal) and the second direction (into page, Fig. 5, [0019] “For example, the crystal orientation of the handle substrate 10 and/or the first SiGe layer 14 may be {100}, {110}, or {111}”, [0026-0027]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Cheng in Reznicek/Hsiao and arrive at the claimed invention so as to “enable tensily strained silicon nanowires within an nFET device region, and compressively stained silicon germanium alloy (SiGe) nanowires in a pFET device region” (Cheng, [0001]) on a common substrate.
Regarding claims 4-5, alternative rejection, Reznicek/Hsiao fail to explicitly disclose (claim 4) the integrated circuit of claim 1, wherein the one or more second bodies of semiconductor material include silicon and less than 1 % germanium and (claim 5) The integrated circuit of claim 1, wherein any one of the one or more first bodies of semiconductor material and any one of the one or more second bodies of semiconductor material are not aligned on a common plane extending in the first and second directions.
Cheng discloses (claim 4) wherein the one or more second bodies of semiconductor material (16/16S) include silicon and less than 1 % germanium ([0026] “Each strained silicon layer 16 of the material stack comprises a single crystalline silicon material”; no Ge disclosed with is less than 1% Ge, Fig. 5) and (claim 5) wherein any one of the one or more first bodies of semiconductor material (18S) and any one of the one or more second bodies of semiconductor material (16S) are not aligned on a common plane extending in the first and second directions (Fig. 5).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Cheng in Reznicek/Hsiao and arrive at the claimed invention so as to “enable tensily strained silicon nanowires within an nFET device region, and compressively stained silicon germanium alloy (SiGe) nanowires in a pFET device region” (Cheng, [0001]) on a common substrate.
Regarding claims 11-12, alternative rejection, Reznicek/Hsiao fail to explicitly disclose (claim 11) The electronic device of claim 8, wherein the one or more second semiconductor nanoribbons include silicon and less than 1 % germanium and (claim 12) the electronic device of claim 8, wherein any one of the one or more first semiconductor nanoribbons and any one of the one or more second semiconductor nanoribbons are not aligned on a common plane extending in the first and second directions.
Cheng discloses (claim 11) wherein the one or more second semiconductor nanoribbons (16/16S) include silicon and less than 1 % germanium ([0026] “Each strained silicon layer 16 of the material stack comprises a single crystalline silicon material”; no Ge disclosed with is less than 1% Ge, Fig. 5) and (claim 12) wherein any one of the one or more first semiconductor nanoribbons (18S) and any one of the one or more second semiconductor nanoribbons (16S) are not aligned on a common plane extending in the first and second directions (Fig. 5).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Cheng in Reznicek/Hsiao and arrive at the claimed invention so as to “enable tensily strained silicon nanowires within an nFET device region, and compressively stained silicon germanium alloy (SiGe) nanowires in a pFET device region” (Cheng, [0001]) on a common substrate.
Regarding claim 15, Reznicek discloses an integrated circuit (Fig. 8) comprising:
a first (left) semiconductor device, the first semiconductor device having one or more first semiconductor nanoribbons (130a) extending in a first direction (horizontal) between a first source or drain region and a second source or drain region (two 170s);
a second (right) semiconductor device, the second semiconductor device having one or more second semiconductor nanoribbons (130a) extending in the first direction from the second source or drain region to a third source or drain region (two 170s)
a first gate structure (190/195/197) around the one or more first semiconductor nanoribbons and a second gate structure (another 190/195/197) around the one or more second semiconductor nanoribbons (Fig. 8); and
wherein each of the one or more first semiconductor nanoribbons includes silicon and
germanium ([0024], “the nanosheet channel layer(s) 130 can be suitable SiGe layer(s)”).
The examiner takes the position that the term “nanoribbons” does not impart a structural different to the claim and that 130a meet said limitation.
However, in the event a structural difference exists, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include nanoribbons as claimed and apply said structure to 130a of Reznicek so as to allow for high density integration and scaling of transistors and/or because the use of conventional materials (nanoribbons) to perform their known function is prima-facie obvious (MPEP 2144.07).
Reznicek fails to disclose (a) a first subfin of semiconductor material beneath the one or more first semiconductor nanoribbons, a second subfin of semiconductor material beneath the one or more second semiconductor nanoribbons, and, a dielectric layer adjacent to the first sub fin beneath the first gate structure, wherein a top surface of the first sub fin is below a top surface of the dielectric layer, and a top surface of the second subfin is above the top surface of the dielectric layer, and, (b) wherein the one or more first semiconductor nanoribbons have a (110) crystallographic surface orientation along surfaces that are parallel with a plane extending in the first direction and the second direction.
Regarding (a), Hsiao discloses (Fig. 4) a first subfin (100A) of semiconductor material beneath the one or more first semiconductor nanoribbons (101A-105A), a second subfin (100b) of semiconductor material beneath the one or more second semiconductor nanoribbons (101B-105B), and, a dielectric layer (103) adjacent to the first subfin (100A) beneath the first gate structure (200), wherein a top surface of the first subfin (100A/100T) is below a top surface of the dielectric layer, and a top surface of the second subfin (100B/110T) is above the top surface of the dielectric layer (Fig. 4).
It would have been obvious to one of ordinary skill in the art to include the subfin and dielectric arrangement of Hsiao in Reznicek before the effective filing date of the claimed invention so as to prevent thickness variations in nanowires and prevent negative effects of gate control ability (Hsiao, [0012]).
Regarding (b), Cheng discloses wherein the one or more semiconductor nanoribbons (16S/18S) have a (110) crystallographic surface orientation along surfaces that are parallel with a plane extending in the first direction and the second direction (into page, Fig. 5, [0019] “For example, the crystal orientation of the handle substrate 10 and/or the first SiGe layer 14 may be {100}, {110}, or {111}”, [0026-0027]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Cheng in Reznicek/Hsiao and arrive at the claimed invention so as to “enable tensily strained silicon nanowires within an nFET device region, and compressively stained silicon germanium alloy (SiGe) nanowires in a pFET device region” (Cheng, [0001]) on a common substrate.
Regarding claim 16, Reznicek/Hsiao/Cheng discloses the integrated circuit of claim 15, wherein the one or more semiconductor nanoribbons (130a) include silicon and germanium (SiGe) along an entire length of the one or more semiconductor nanoribbons in the first direction (no concentration variation disclosed, hence, presumed inherently consistent as claimed. [0024] – “the nanosheet channel layer(s) 130 can be suitable SiGe layer(s)” ).
In the event Reznicek/Hsiao/Cheng does not meet the claim inherently, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at the claimed concentration arrangement in Reznicek/Hsiao/Cheng so as to provide a SiGe channel suitable for P-type channel devices since the use the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 17, Reznicek/Hsiao/Cheng discloses the integrated circuit of claim 15, further comprising a substrate having a (110) crystallographic surface orientation (Reznicek – [0018] or Cheng – [0019]).
Regarding claim 18, Reznicek/Hsiao/Cheng discloses (inherently) the integrated circuit of claim 15, wherein the concentration of germanium in a central portion of each of the one or more first semiconductor nanoribbons (130a) between the first and second source or drain regions (170s) is substantially the same as the concentration of germanium at first and second ends along the first direction of the corresponding one or more first semiconductor nanoribbons (no concentration variation disclosed, hence, presumed inherently consistent as claimed. [0024] – “the nanosheet channel layer(s) 130 can be suitable SiGe layer(s)” ).
In the event Reznicek/Hsiao/Cheng does not meet the claim inherently, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at the claimed concentration arrangement in Reznicek/Hsiao/Cheng so as to provide a SiGe channel suitable for P-type channel devices since the use the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 19, Reznicek/Hsiao/Cheng discloses the integrated circuit of claim 15, wherein the one or more second semiconductor nanoribbons include silicon and less than 1 % germanium (Hsiao – [0027] or Cheng – [0026]; no Ge disclosed in any of the references).
Regarding claim 20, Reznicek/Hsiao/Cheng discloses wherein the first, second and third
source or drains regions (all 170) do not have visible crystal facets when viewed using scanning electron microscopy (SEM) or transmission electron microscopy (TEM) along a cross-section through the region extending along the first direction and a third direction (into the page) that is orthogonal to both the first direction (horizontal) and the second direction (vertical. No facets are disclosed, hence, presumed inherently absent as claimed, Fig. 8)
In the event Reznicek/Hsiao/Cheng does not meet the claim inherently, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at the claimed absence of facets in Reznicek/Hsiao/Cheng so as to minimize defect formation in the source/drain and/or channels, and/or so as to achieve proper carrier mobility.
Response to Arguments
Applicant’s arguments, see p. 7-11, filed 5.18.2026, with respect to (a) the original specification having proper support for the second subfin and related structures of claims 1, 8 and 15 and (b) claims 1, 8 and 15 being definite have been fully considered and are persuasive. Specifically, applicant’s argument with regards to Figs. 2E, 2E’, 2G and 2G’ are persuasive.
The examiner recommends amending the drawings and specification to show/disclose the subject matter of the second subfin and related structures. No new matter should be entered.
Finally, the examiner notes that while the amendments to claims 1, 8 and 15 are minor, said amendments changed the scope of each of those claims and their dependents.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andres Munoz/Primary Examiner, Art Unit 2818
Prosecution Insights