Prosecution Insights
Last updated: April 19, 2026
Application No. 17/847,559

GATE ALL AROUND TRANSISTORS ON ALTERNATE SUBSTRATE ORIENTATION

Non-Final OA §112
Filed
Jun 23, 2022
Examiner
MUNOZ, ANDRES F
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
3 (Non-Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
2y 4m
To Grant
94%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
541 granted / 707 resolved
+8.5% vs TC avg
Strong +18% interview lift
Without
With
+17.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
36 currently pending
Career history
743
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
43.7%
+3.7% vs TC avg
§102
28.6%
-11.4% vs TC avg
§112
21.5%
-18.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 707 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2.9.2026 has been entered. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first and second subfins of claims 1, 8 and 15 with “a dielectric layer adjacent to the first subfin and the second subfin, wherein a top surface of the first subfin is below a top surface of the dielectric layer, and a top surface of the second subfin is above the top surface of the dielectric layer” (claims 1 and 8) and “a dielectric layer adjacent to the first sub fin beneath the first gate structure and adjacent to the second sub fin beneath the second gate structure, wherein a top surface of the first sub fin is below a top surface of the dielectric layer, and a top surface of the second subfin is above the top surface of the dielectric layer” (claim 15) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Note: these elements must be shown as part of a single embodiment. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claims 1, 8 and 15, the first and second subfins of claims 1, 8 and 15 with “a dielectric layer adjacent to the first subfin and the second subfin, wherein a top surface of the first subfin is below a top surface of the dielectric layer, and a top surface of the second subfin is above the top surface of the dielectric layer” (claims 1 and 8) and “a dielectric layer adjacent to the first sub fin beneath the first gate structure and adjacent to the second sub fin beneath the second gate structure, wherein a top surface of the first sub fin is below a top surface of the dielectric layer, and a top surface of the second subfin is above the top surface of the dielectric layer” (claim 15) cause the claims to fail to comply with the written description requirement. First, applicant’s arguments filed 1.7.2026 fail to indicate where support is found in the specification for the newly added limitations of claims 1, 8 and 15. Hence, the examiner cannot rely on applicant’s arguments to aid in determining if the claims meet the written description requirement. Second, while the specification/drawings disclose two figures in which (a) a subfin 122 is below a top surface of a dielectric 124 in Fig. 1B and (b) a subfin 219 is above a top surface of a dielectric 221 in Fig. 2E’, which the examiner presumes is the section of the specification the applicant may rely on for showing support for the claim amendments, there is no evidence that these two figures are included in a same final integrated circuit nor that they belong together in a single common embodiment because Figs. 1B and 2E’ show the same device 101 at different manufacturing steps since (a) Fig. 2E’ is an intermediate processing step wherein sacrificial gate structure 206 and first layers 210 are still present, (b) Fig. 1B includes gate structure 114 formed after removal of sacrificial gate structure 206 and first layers 210, and (c) Fig. 2G’ shows the removal of the sacrificial gate structure 206 and first layers 210 of first semiconductor device 101 wherein subfin 219 is, similar to Fig. 1B, below a top surface of a dielectric. PNG media_image1.png 398 1513 media_image1.png Greyscale Therefore, applicant does not have support for the claimed subject matter added to claims 1, 8 and 15 and none of the dependent claims addresses this deficiency. All claims 1-20 are rejected for failing to comply with the written description requirement. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Note: per MPEP 2173.03 inconsistencies between the specification and the claims can be the basis for indefiniteness rejections since MPEP 2173.03 states “A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty”. Regarding claims 1, 8 and 15, the first and second subfins of claims 1, 8 and 15 with “a dielectric layer adjacent to the first subfin and the second subfin, wherein a top surface of the first subfin is below a top surface of the dielectric layer, and a top surface of the second subfin is above the top surface of the dielectric layer” (claims 1 and 8) and “a dielectric layer adjacent to the first sub fin beneath the first gate structure and adjacent to the second sub fin beneath the second gate structure, wherein a top surface of the first sub fin is below a top surface of the dielectric layer, and a top surface of the second subfin is above the top surface of the dielectric layer” (claim 15) renders the claims indefinite because the claimed subject matter conflicts the with specification wherein MPEP 2173.03 states that conflicts/inconsistencies between the claims and the specification can be the basis for indefiniteness rejections. The specification/drawings disclose two figures in which (a) a subfin 122 is below a top surface of a dielectric 124 in Fig. 1B and (b) a subfin 219 is above a top surface of a dielectric 221 in Fig. 2E’; however, there is no evidence that these two figures are included in a same final integrated circuit nor that they belong together in a single common embodiment because Figs. 1B and 2E’ show the same device 101 at different manufacturing steps since (a) Fig. 2E’ is an intermediate processing step wherein sacrificial gate structure 206 and first layers 210 are still present, (b) Fig. 1B includes gate structure 114 formed after removal of sacrificial gate structure 206 and first layers 210, and (c) Fig. 2G’ shows the removal of the sacrificial gate structure 206 and first layers 210 of first semiconductor device 101 wherein subfin 219 is, similar to Fig. 1B, below a top surface of a dielectric. PNG media_image1.png 398 1513 media_image1.png Greyscale Therefore, the specification/drawings and the claims have inconsistencies/conflicts which lead to indefiniteness of the claims per MPEP 2173.03. None of the dependent claims addresses these deficiencies and all claims 1-20 are rejected under indefiniteness. Finally, no prior art is applied to the claims in view of MPEP 2173.06 which states “where there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of a claim, it would not be proper to reject such a claim on the basis of prior art”. Regarding claims 6, 13 and 20, “the region” lacks proper antecedent basis. Response to Arguments Applicant's arguments filed 1.7.2026 have been fully considered but they are not persuasive. The applicant alleges (p. 9) claims 1, 8 and 15 should be found allowable in view of the amendment directed to the two claims subfins and related structures, however, the claims are not in condition for allowance in view of the 35 USC 112 rejections above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Andres Munoz/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Jun 23, 2022
Application Filed
Feb 15, 2023
Response after Non-Final Action
Jul 25, 2025
Non-Final Rejection — §112
Oct 16, 2025
Interview Requested
Oct 23, 2025
Applicant Interview (Telephonic)
Oct 23, 2025
Examiner Interview Summary
Oct 24, 2025
Response Filed
Nov 06, 2025
Final Rejection — §112
Dec 29, 2025
Interview Requested
Jan 07, 2026
Response after Non-Final Action
Feb 09, 2026
Request for Continued Examination
Feb 11, 2026
Response after Non-Final Action
Feb 12, 2026
Non-Final Rejection — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
94%
With Interview (+17.8%)
2y 4m
Median Time to Grant
High
PTA Risk
Based on 707 resolved cases by this examiner. Grant probability derived from career allow rate.

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