DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: [0064] contains “control MUXs1120” which appears to be a typographical error.
Appropriate correction is required.
Claim Construction
Regarding claim 1, the preamble is given patentable weight. Claim 3 contains the limitation “the FFT butterfly circuit” in the body, which is referring to the limitations as recited in the preamble of claim 1. A skilled person in the art reading the claims would consider the claim in view of the body and preamble, and identify them limited to the technological environment of the FFT butterfly circuits. The body of the claim depends on the preamble for completeness, and gives life, meaning, and vitality to this claim. Therefore, the preamble of claim 1 should be afforded patentable weight.
Claim Interpretation
Claim 9 recites the limitation “wherein the FFT butterfly circuit is implemented in an application specific integrated circuit or a field programmable gate array”. The BRI of the claim encompasses implementing in either an application specific integrated circuit or a field programmable gate array. Therefore, the BRI of claim 9 requires only one of the implementation devicces to cover the scope of the claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9, 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 11, and 19 recite the limitations "the selection" and version of “the selected channel”. There is insufficient antecedent basis for these limitations in the claims. Claims 2-9 inherit the same deficiency by reasons of dependence on claim 1. Claims 12-18 inherit the same deficiency by reasons of dependence on claim 11. Claim 20 inherits the same deficiency by reasons of dependence on claim 19.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Apparatus claims 1-9 will be discussed first, followed by method claims 19-20, and followed by apparatus claims 10-18.
Claims 1-3, 9, 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 8194532 B1 Whyte (hereinafter “Whyte”) in view of US 20170026205 A1 Agee (hereinafter “Agee”) in view of US 20190243868 A1 Goswami (hereinafter “Goswami”).
Regarding claim 1, Whyte discloses a fast Fourier transform (FFT) butterfly circuit (Fig. 6-1, 6-2 co. 3 ln. 30-34, co. 7 ln. 31-34, co. 9 ln. 3-7) comprising:
a first multiplexer (Fig. 6-1, 6-2 “652” co. 7 ln. 59-65, co. 8 ln. 16-21) configured to select one of a first channel (Fig. 6-2 input line from “642” co. 9 ln. 16-19) or a delayed version of a second channel (Fig. 6-2 input line from “644” that forks to “652” and “654” co. 9 ln. 16-19), the selection (Fig. 6-1, 6-2 output of “652” co. 8 ln. 45-52) based on a frame index associated with the first channel and/or the second channel (co. 7 ln. 31-46);
a second multiplexer (Fig. 6-1, 6-2 “654” co. 7 ln. 59-65, co. 8 ln. 16-21) configured to select the one of the first channel or the delayed version of the second channel that was not selected by the first multiplexer (Fig. 6-2 input line from “644” that forks to “652” and “654” co. 9 ln. 16-19); and
a butterfly core circuit (Fig. 6-1, 6-2 “620” co. 7 ln. 59-65, co. 9 ln. 3-7) configured to
receive a delayed version of the selected channel from the first multiplexer (Fig. 6-1, 6-2 output of “652” co. 8 ln. 45-52) as a top butterfly branch (Fig. 6-2 output from “652” top line to “622” and diagonal to “624” co. 9 ln. 8-15),
receive the selected channel from the second multiplexer (Fig. 6-1, 6-2 output of “654” co. 8 ln. 45-52) as a bottom butterfly branch (Fig. 6-2 output from “654” bottom line to “624” and diagonal to “622” co. 9 ln. 8-15),
apply FFT twiddle factors (Fig. 6-2 “634, 636, 638” co. 9 ln. 34-40) to the bottom butterfly branch to generate a scaled bottom butterfly branch (Fig. 6-2 “674” multiplier receives “684” as an input and outputs at “670” to “640” to be selected through the layers of muxes “656, 658, 660” and “652, 654” co. 9 ln. 20-33, co. 7 ln. 66-67 bridging to co. 8 ln. 1-7, 11-57), and
generate a sum channel output as the sum of the top butterfly branch and the scaled bottom butterfly branch (Fig. 6-2 “622” output when adding co. 9 ln. 8-15), and a difference channel output as the difference between the top butterfly branch and the scaled bottom butterfly branch (Fig. 6-2 “624” output when subtracting co. 9 ln. 8-15).
Whyte discloses the claimed invention except for particular arrangements of parts. Whyte discloses scaling the bottom butterfly branch outside of the butterfly core circuit. However, it would have been obvious to one having ordinary skill in the art before the effective filing date to rearrange the operations to include such functions as part of the butterfly core circuit, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Further, it would have been obvious to try as an alternative embodiment (Fig. 2 “204”, “214”, “210” co. 5 ln. 4-20) places the multiplication at the respective bottom branch of the butterfly.
Whyte is silent with disclosing the frame index and the delayed version; and the second multiplexer receiving “the one of the first channel”.
Agee discloses the frame index ([0224-0225]
n
f
r
a
m
e
).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Whyte’s fast Fourier transform (FFT) butterfly circuitry with Agee’s index because they are in the claimed invention’s same field of endeavor of Fourier transforms ([0020-0021]). Modifying with Agee’s index facilitates the general FSFE implementation ([0225], [0145]), and therefore in practice reduces commensurately the computations of data time-band-width product with the number of adaptation frames to meet memory constraints (0227]). It would have been obvious to one of ordinary skill in the art to configure Whyte’s butterfly circuitry with Agee’s index as doing so would have been beneficial.
Whyte in view of Agee are silent with disclosing the delayed version; and the second multiplexer receiving “the one of the first channel”.
Goswami discloses the delayed version (Fig. 1a, 1b outputs from delay elements “106” [0054]; Fig. 2a, 2b outputs from delay elements “208a-d” [0059]). Goswami further discloses a second multiplexer configured to receive the one of the first channel (Fig. 1a, 1b “107” pair of multiplexers; Fig. 2a, 2b “207a-d” [0059]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Whyte in view of Agee’s modified fast Fourier transform (FFT) butterfly circuitry with Goswami’s delay elements to produce the delayed output version because they are in the claimed invention’s same field of endeavor of Fourier transforms ([0002]). Modifying with Goswami’s delay elements to produce the delayed output version would provide better support for pipelining approaches and more control over data configuration ([0079]). It would have been obvious to one of ordinary skill in the art to configure Whyte in view of Agee’s modified butterfly circuitry with Goswami’s delayed version as doing so would have been beneficial.
Further, it would have been obvious to try the particular connection of the second multiplexer receiving the first channel as an input as Goswami explicitly discloses, given the finite number of practical connections to input to the multiplexer. Making this modification would be beneficial as doing so would provide the modified invention with greater configurability according to required FFT size ([0091]).
Claim 19 is directed to a method that would be performed by the apparatus of claim 1. All limitations recited in claim 19, are the same in claim 1. The claim 1 analysis similarly applies, and claim 19 is similarly rejected.
Regarding claim 2, the teachings addressed in the claim 1 analysis and rejection
are incorporated, and Whyte discloses wherein the butterfly core circuit (see claim 1 mapping) comprises
a memory (Fig. 6-2 “634, 636, 638” co. 9 ln. 34-40) configured to store the FFT twiddle factors (Fig. 6-2 “TW1, TW2,
j
*
s
q
r
t
(
3
)
/
2
” co. 8 ln. 24-39, co. 9 ln. 34-40).
Regarding claim 3, the teachings addressed in the claim 2 analysis and rejection
are incorporated, and Whyte discloses wherein the FFT twiddle factors (see claim 2 mapping)
are selected (Fig. 6-2 “632” co. 9 ln 37-40) from the memory (Fig. 6-2 “634, 636, 638” co. 9 ln. 34-40) based on a size of an FFT for which the FFT butterfly circuit is employed (co. 7 ln. 66-67 bridging to co. 8 ln. 1-7, 11-57 dependent on stage of radix, stages as illustrated in Fig. 2, co. 5 ln. 40-46).
Regarding claim 9, the teachings addressed in the claim 1 analysis and rejection
are incorporated, and Whyte discloses wherein the FFT butterfly circuit (see claim 1 mapping)
is implemented in an application specific integrated circuit or a field programmable gate array (Fig. 8 co. 10 ln. 21-46).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Whyte in view of Agee in view of Goswami as applied to claim 1 above, and further in view of US 20080215656 A1 Hafuka et al. (hereinafter "Hafuka") in view of US 6574648 B1 Oohashi et al. (hereinafter “Oohashi”).
Regarding claim 4, the teachings addressed in the claim 2 analysis and rejection
are incorporated, and Whyte in view of Agee in view of Goswami discloses wherein the memory to select the FFT twiddle factors, and the frame index (see claim 1 mapping). The motivation to combine provided with respect to claim 1 equally applies.
Whyte in view of Agee in view of Goswami is silent with disclosing a bit extraction circuit configured to extract selected bits from the frame index for use as an address.
Hafuka discloses a bit extraction circuit configured to extract selected bits (Fig. 1 “24” [0056]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Whyte in view of Agee in view of Goswami’s modified fast Fourier transform (FFT) butterfly circuitry with Hafuka’s bit extraction circuit because they are in the claimed invention’s same field of endeavor of Fourier transforms ([Abstract]). Modifying with Hafuka’s bit extraction circuit reduces computational errors in overflow considerations ([0076-0078]). It would have been obvious to one of ordinary skill in the art to configure Whyte in view of Agee in view of Goswami’s modified butterfly circuitry with Hafuka’s bit extraction circuit as doing so would have been beneficial, displaying an improved error percentage when compared to previous processes ([0079]).
Whyte in view of Agee in view of Goswami in view of Hafuka is silent with disclosing the frame index for use as an address.
Oohashi discloses for use as an address (co. 8 ln. 18-24, 53-67; co. 15 ln. 55-60).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Whyte in view of Agee in view of Goswami in view of Hafuka’s modified fast Fourier transform (FFT) butterfly circuitry with Oohashi’s addressing feature because they are in the claimed invention’s same field of endeavor of Fourier transforms (co. 14 ln. 18-26). Modifying with Oohashi’s addressing feature reduces wasted circuitry area and scale while efficiently mapping data values to memory (co. 23 ln. 1-16). It would have been obvious to one of ordinary skill in the art to configure Whyte in view of Agee in view of Goswami in view of Hafuka’s modified butterfly circuitry with Oohashi’s addressing feature as doing so would have been beneficial.
Claims 5-8, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Whyte in view of Agee in view of Goswami as applied to claim 1 above, and further in view of Oohashi.
Regarding claim 5, the teachings addressed in the claim 1 analysis and rejection
are incorporated, and Whyte discloses further comprising the first multiplexer and the second multiplexer (see claim 1 mapping) and
a size of an FFT for which the FFT butterfly circuit is employed (co. 7 ln. 66-67 bridging to co. 8 ln. 1-7, 11-57 dependent on stage of radix, stages as illustrated in Fig. 2, co. 5 ln. 40-46).
Whyte in view of Agee in view of Goswami disclose the frame index (see claim 1 mapping). The motivation to combine provided with respect to claim 1 equally applies.
Whyte in view of Agee in view of Goswami are silent with disclosing a bit slice circuit configured to extract a selected bit from the frame index to control operation, the selected bit based on a size.
Oohashi discloses a bit slice circuit (Fig. 1 “102” co. 15 ln. 48-60) configured to extract a selected bit from the frame index to control operation (co. 17 ln. 19-46 control with respect to “31a, 31b” in Fig. 2 after signals are outputted), the selected bit based (co. 17 ln. 19-22, 46-53, bit signals selected) on a size.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Whyte in view of Agee in view of Goswami modified fast Fourier transform (FFT) butterfly circuitry with Oohashi’s addressing feature because they are in the claimed invention’s same field of endeavor of Fourier transforms (co. 14 ln. 18-26). Modifying with Oohashi’s bit slicing circuitry prepares input data before butterfly computations into proper form (co. 17 ln. 17-53, co. 21 ln. 1-4, 58-65), and even reduces required computations by omitting processing data that is not there (co. 21 ln. 1-4). It would have been obvious to one of ordinary skill in the art to configure Whyte in view of Agee in view of Goswami modified butterfly circuitry with Oohashi’s bit slicing circuitry as doing so would have been beneficial.
Regarding claim 6, the teachings addressed in the claim 5 analysis and rejection
are incorporated, and Whyte discloses further comprising
a third multiplexer (Fig. 6-2 “672” co. 9 ln. 20-25) configured to select one of the sum channel output (Fig. 6-2 “682” after first being processed by “658” and output to “644” and further outputted to “602”, processed by “604”, and input to “672” co. 7 ln. 66-67, ln. co. 8 ln. 1-4, 11-15, 40-45) or a delayed version of the difference channel output (Fig. 6-2 “684” input to “672” co. 9 ln. 23-25) as a first butterfly output channel (Fig. 6-2 output of “672” co. 9 ln. 27-33), the selection (Fig. 6-2 output of “672” based on “682” or “684” co. 9 ln. 27-33) based on the extracted selected bit and based on the frame (co. 7 ln. 31-46) index.
Whyte in view of Agee in view of Goswami disclose the frame index and the delayed version (see claim 1 mapping). The motivation to combine provided with respect to claim 1 equally applies.
Whyte in view of Agee in view of Goswami in view of Oohashi disclose based on the extracted selected bit (see claim 5 mapping). The motivation to combine provided with respect to claim 5 equally applies.
Regarding claim 7, the teachings addressed in the claim 6 analysis and rejection
are incorporated, and Whyte discloses further comprising
a fourth multiplexer (Fig. 6-2 “658” co. 9 ln. 16-19) configured to select the one of the sum channel output (Fig. 6-2 “682” input to “658” in “640” co. 8 ln. 21-24) or the delayed version of the difference channel output (Fig. 6-2 “684” input to “658” in “640”) that was not selected by the third multiplexer (Fig. 6-2 “672” co. 9 ln. 20-25) as a second butterfly output channel (Fig. 6-2 output of “658” co. 9 ln. 16-19).
Whyte in view of Agee in view of Goswami disclose the frame index and the delayed version (see claim 1 mapping). The motivation to combine provided with respect to claim 1 equally applies.
Claim 20 is directed to a method that would be performed by the apparatus of claims 6-7. All limitations recited in claim 20, are the same in claims 6-7. The claims 6-7 analysis similarly applies, and claim 20 is similarly rejected.
Regarding claim 8, the teachings addressed in the claim 7 analysis and rejection
are incorporated, and Whyte in view of Agee in view of Goswami discloses further comprising the first butterfly output channel (see claim 6 mapping) and the second butterfly output channel (see claim 7 mapping).
Further, Goswami discloses a delay circuit (Fig. 1a, 1b “106” [0054]; Fig. 2a, 2b “208a-d” [0059]) to delay to align ([0012], [0079-0080]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Whyte in view of US 20090252356 A1 Goodwin et al. (hereafter “Goodwin”).
Regarding claim 10, Whyte discloses a reconfigurable channelizer comprising:
a multi-stage fast Fourier transform (FFT) circuit (Fig. 6-1, 6-2 co. 3 ln. 30-34, co. 7 ln. 31-34, co. 9 ln. 3-7) configured to transform time domain input data to output frequency domain data distributed into frequency bins, wherein a number of the frequency bins is dynamically programmable; and
the multi-stage FFT circuit comprising a plurality of FFT butterfly circuits, each FFT butterfly circuit (Fig. 6-1, 6-2 “620” used repeatedly for each computation based on the mode co. 7 ln. 59-67, co. 8 ln. 1-4, 11-24, 40-63) configured to compute an FFT butterfly for an associated stage of the multi-stage FFT circuit (co. 7 ln. 66-67 bridging to co. 8 ln. 1-7, 11-57 dependent on stage of radix, mode based on stage as illustrated in Fig. 2, co. 5 ln. 40-46).
Whyte discloses the claimed invention limitation “FFT butterfly circuits” except for a plurality of “FFT butterfly circuits”. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to make a plurality of the “FFT butterfly circuits,” since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Further, it would have been obvious as modifying to include a plurality of FFT butterfly circuits would increase the amount of data the invention could process at once and thus, provide better support for handling larger values simultaneously (co. 4 ln. 29-56-61; co. 5 ln. 4-6).
Whyte is silent with disclosing configured to transform time domain input data to output frequency domain data distributed into frequency bins, wherein a number of the frequency bins is dynamically programmable.
Goodwin discloses configured to transform time domain input data (Fig. 7 “702” [0068]
x
1
[
t
]
…
x
m
[
t
]
) to output frequency domain data (Fig. 7 “706” [0068-0069]
X
1
k
,
l
…
X
m
k
,
l
) distributed into frequency bins, wherein a number of the frequency bins is dynamically programmable ([0063], [0071] frequency bin
k
).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Whyte’s fast Fourier transform (FFT) butterfly circuitry with Goodwin’s transformation features because they are in the claimed invention’s same field of endeavor of Fourier transforms ([0069]). Modifying with Goodwin’s transformation features so that data is in the frequency-domain presents the modified invention with a wider range of processing architectures that have low costs of FFT algorithms implementation ([0044]). It would have been obvious to one of ordinary skill in the art to configure Whyte’s butterfly circuitry with Goodwin’s transformation features as doing so would have been beneficial.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Whyte in view of Goodwin as applied to claim 10 above, and further in view of Agee in view of Goswami.
Claim 11 is directed to an apparatus that recites similar limitations to that of the apparatus of claim 1. All limitations recited in claim 11, are the same in claim 1. The claim 1 analysis similarly applies, and claim 11 is similarly rejected.
Claim 12 is directed to an apparatus that recites similar limitation to that of the apparatus of claims 2-3. All limitations recited in claim 12, are the same in claims 2-3. The claims 2-3 analysis similarly applies, and claim 12 is similarly rejected.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Whyte in view of Goodwin as applied to claim 10 above, and further in view of Agee in view of Goswami in view of Hafuka in view of Oohashi.
Claim 13 is directed to an apparatus that recites similar limitation to that of the apparatus of claim 4. All limitations recited in claim 13, are the same in claim 4. The claim 4 analysis similarly applies, and claim 13 is similarly rejected.
Claims 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Whyte in view of Goodwin as applied to claim 10 above, and further in view of Agee in view of Goswami in view of Oohashi.
Claims 14-17 are directed to an apparatus that recites similar limitation to that of the apparatus of claims 5-8. All limitations recited in claims 14-17, are the same in claims 5-8. The claims 5-8 analysis similarly applies, and claims 14-17 are similarly rejected.
Regarding claim 18, the teachings addressed in the claim 17 analysis and rejection are incorporated, and Whyte discloses wherein
the delay circuit is further configured to generate the delayed version of the second channel (Fig. 6-2 input line from “644” that forks to “652” and “654” co. 9 ln. 16-19) for a next stage of the multi-stage FFT circuit (co. 8 ln. 11-63, in the second and third modes corresponding to the next second and third butterfly stages of Fig. 2 “242, 244”).
Whyte is silent with disclosing the delay circuit is further configured to generate the delayed version.
Whyte in view of Goodwin in view of Agee in view of Goswami disclose the delay circuit is further configured to generate the delayed version. Further, Goswami discloses the delay circuit (Fig. 1a, 1b “106” [0054]; Fig. 2a, 2b outputs from delay elements “208a-d” [0059]) is further configured to generate the delayed version (Fig. 1a, 1b outputs from delay elements “106” [0054]; Fig. 2a, 2b outputs from delay elements “208a-d” [0059]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARKUS A VILLANUEVA whose telephone number is (703)756-1603. The examiner can normally be reached M - F 8:30 am - 5:30 pm.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151