Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/17/2025 has been entered.
Specification Objection Withdrawal
Applicant’s amendment of the title of the invention is acknowledged. Thus, the objection to specification is withdrawn.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 8 rejected under 35 U.S.C. 103 as being unpatentable over Chung (U.S. Patent Pub. No. 2018/0005703), in view of Nandakumar (U.S. Patent Pub. No. 2022/0375856) of record, in view of Yamashita (U.S. Patent Pub. No. 2005/0202219).
Regarding Claim 1
FIG. 7 of Chung discloses a semiconductor device, comprising: a first wiring (934); a first via conductive layer (933) reaching the first wiring; a first metal film (932) having a first portion, a second portion arranged on one end of the first portion and a third portion arranged on the other end of the first portion; a second metal film (936) arranged separately from the first metal film; a second via conductive layer (935) provided so as to reach the first wiring; and a second wiring (938), wherein the second portion of the first metal film is electrically connected to the first wiring via the first via conductive layer, wherein the second wiring is electrically connected to the first wiring via the second via conductive layer, wherein each of at least one part of the second portion of the first metal and at least one part of the third portion of the first metal has a wiring width larger than a wiring width of the first portion of the first metal (FIG. 3), and wherein the first metal film is a fuse element [0191], and the second metal film is a resistor element, wherein the first metal film and the second metal film is arranged in an upper layer of the first wiring and in a lower layer of the second wiring.
Chung is silent with respect to “a first interlayer dielectric layer arranged so as to cover the first wiring”; “a second interlayer dielectric layer arranged so as to cover the first metal film and the second metal film” and “a material of each of the first metal film and the second metal film includes silicon metal or nickel chromium.
FIG. 1 of Nandakumar discloses a similar semiconductor device, comprising a first metal film (120 under 128); a second metal film (124) arranged separately from the first metal film; a second interlayer dielectric layer (130) arranged so as to cover the first metal film and the second metal film; a second via hole (132) provided through the second interlayer dielectric layer from an upper surface of the second interlayer dielectric layer; a second via conductive layer embedded in the second via hole; and a second wiring (142) arranged on the upper surface of the second interlayer dielectric layer, wherein a material of each of the first metal film and the second metal film includes silicon metal or nickel chromium [0022], and wherein the first metal film is a fuse element, and the second metal film is a resistor element.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chung, as taught by Nandakumar. The ordinary artisan would have been motivated to modify Chung in the above manner for purpose of providing a high sheet resistance and low stress coefficient ([0035] of Nandakumar).
Modified Chung is silent with respect to “a first interlayer dielectric layer arranged so as to cover the first wiring”.
FIG. 1 of Yamashita discloses a similar semiconductor device, comprising a first wiring (7); a first interlayer dielectric layer (9) arranged so as to cover the first wiring; a first via conductive layer (15) embedded in the first interlayer dielectric layer and reaching the first wiring from an upper surface of the first interlayer dielectric layer; a second metal film (25) arranged on the upper surface of the first dielectric layer; a second interlayer dielectric layer (29) arranged so as to cover the second metal film, wherein a material of each of the second metal film includes silicon metal or nickel chromium [0164], and wherein the second metal film is a resistor element.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chung, as taught by Yamashita. The ordinary artisan would have been motivated to modify Chung in the above manner for purpose of providing protection ([0070] of Yamashita).
Regarding Claim 8
FIG. 1 of Nandakumar discloses the first metal film and the second metal film are arranged in same layer and have same composition [0022].
Claims 3 and 4 rejected under 35 U.S.C. 103 as being unpatentable over Chung, Yamashita and Nandakumar, in view of Matsumura (U.S. Patent Pub. No. 2011/0180901) of record.
Regarding Claim 3
Chung as modified by Yamashita and Nandakumar discloses Claim 1.
Chung as modified by Yamashita and Nandakumar is silent with respect to “the resistor element has a plurality of resistor portions, and wherein the plurality of resistor portions is connected in series or in parallel”.
FIG. 42 of Matsumura discloses a similar semiconductor device, wherein the resistor element has a plurality of resistor portions, and wherein the plurality of resistor portions is connected in series or in parallel [0064].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chung, as taught by Matsumura.
The ordinary artisan would have been motivated to modify Chung in the above manner, because the claimed configuration was a matter of choice, which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant (for example, allowing a current flow in a zigzag manner, see [0185] of Matsumura). In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04. Furthermore, it has been held by the courts that a change in shape or configuration, without any criticality, is nothing more than one of numerous shapes that one of ordinary skill in the art will find obvious to provide based on the suitability for the intended final application. See MPEP 2144.04 (IV) (B)).
Regarding Claim 4
FIG. 42 of Matsumura discloses the plurality of resistor portions is connected in series and arranged such that the resistor element meanders in plan view.
Claim 5 rejected under 35 U.S.C. 103 as being unpatentable over Chung, Yamashita and Nandakumar, in view of Hotta (CN 100559565) of record.
Regarding Claim 5
Chung as modified by Yamashita and Nandakumar discloses Claim 1.
Chung as modified by Yamashita and Nandakumar is silent with respect to “the resistor element has a plurality of resistor portions, and wherein the plurality of resistor portions is connected in series or in parallel”.
FIG. 23 of Hotta discloses a similar semiconductor device, wherein an area where the first wiring (49) and the first metal film (55) overlap is smaller than an area where the first wiring and the second metal film (52) overlap.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chung, as taught by Hotta. The ordinary artisan would have been motivated to modify Chung in the above manner for purpose of forming multilevel interconnections (Abstract of Hotta).
Claims 6 and 7 rejected under 35 U.S.C. 103 as being unpatentable over Chung, Yamashita and Nandakumar, in view of Kawamoto (JP H07230747) of record
Regarding Claim 6
Chung as modified by Yamashita and Nandakumar discloses Claim 1.
Chung as modified by Yamashita and Nandakumar is silent with respect to “a wiring length of the first metal film is smaller than a wiring length of the second metal film”.
FIG. 6 of Kawamoto discloses a similar semiconductor device, wherein a wiring length of the first metal film (14) is smaller than a wiring length of the second metal film (17).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chung, as taught by Kawamoto. The ordinary artisan would have been motivated to modify Chung in the above manner for purpose of improving protection reliability (Abstract of Kawamoto).
Regarding Claim 7
FIG. 7 of Kawamoto discloses a wiring width of the first metal film (14) is smaller than a wiring width of the second metal film (17).
Pertinent Art
Tottori (JP 2001044281) discloses a semiconductor device, comprising: a first wiring; a second wiring; a first metal film; and a second metal film arranged separately from the first metal film, wherein the first metal film and the second metal film is arranged in an upper layer of the first wiring and in a lower layer of the second wiring, wherein the first metal film is a fuse element. Lee (U.S. Patent Pub. No. 2016/0050717) discloses a fuse made of nickel-chromium alloy. Tamagawa (JP 2014072240) discloses the resistor element has a plurality of resistor portions, and wherein the plurality of resistor portions is connected in series or in parallel.
Conclusion
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897