DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1, 7 and 31 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show “a dielectric liner between the dielectric structure and the conductive material…in the second portion” as described in the specification (Para [0080, 0088]). Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 and 31-38 are rejected under 35 U.S.C. 103 as being unpatentable over Terasawa et al. (US 2019/0280001 A1, hereinafter Terasawa ‘001) in view of Ishiduki (US 2022/0093633 A1, hereinafter Ishiduki ‘633) in further view of Jhothiraman et al. (US 2022/0359391 A1, hereinafter Jhothiraman ‘391), in view of the following arguments.
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With respect to Claim 1 Terasawa ‘001 discloses an apparatus comprising (Fig 1-31):
memory cells (memory cells shown in Fig 19B, region 58, Para [0145], hereinafter MC) located on tiers (tiers of layers 132/146 and 232/246 shown in Fig 31, Para [0178 and 0183], hereinafter tiers) of the apparatus (memory device show in Fig 31);
control gates (layers 146 and 246, Fig 31, Para [0161]) for the memory cells (MC), the control gates (layers of 146 and 246) including a first control gate (246-1 as shown in annotated Fig 31 of Terasawa ‘001, Para [0161]) located on a first tier (tier comprising layers 246 as shown in annotated Fig 31 of Terasawa ‘001, hereinafter Tier1) of the tiers (tiers), and a second control gate (146-1 as shown in annotated Fig 31 of Terasawa ‘001, Para [0161]) located on a second tier (tier comprising layers 146 as shown in annotated Fig 31 of Terasawa ‘001, hereinafter Tier2) of the tiers (tiers), wherein respective portions of the control gates (portions of 146-1 and 246-1) form part of a staircase structure (annotated Fig 31 of Terasawa ‘001 shows portions of control gates, 146-1 and 246-1 form part of staircase structure, hereinafter SS);
a dielectric structure (44, Fig 29C, Para [0157]) over the control gates (annotated Fig 31 of Terasawa ‘001 and Para [0162] discloses dielectric 44 over gates 146-1);
a first conductive contact (86Y, Fig 30C, Para [0174]) and contacting (disclosed in Fig 30C and Para [0174]) the first control gate (246-1) at the staircase structure (SS), the first conductive contact (86Y) having a first length (first length of 86Y shown in annotated Fig 30C of Terasawa ‘001, herein after FL) in a direction (vertical direction as shown in Fig 30C) from the first tier (Tier1) to the second tier (Tier2); and
a second conductive contact (86x/96, Fig 30C, Para [0174]) formed in an opening (85, Fig 29B-29C, Para [0172]) in the dielectric structure (44) and contacting (disclosed in Fig 30C and Para [0174]) the second control gate (146-1) at the staircase structure (SS), the second conductive contact (86x/96) having a second length (second length of 86x/96 shown in annotated Fig 30C of Terasawa ‘001, herein after SL) in the direction (vertical direction as shown in Fig 30C) from the first tier (Tier1) to the second tier (Tier2), the second length (SL) being unequal to the first length (FL)(Fig 30C discloses 86x/96 and 86Y having unequal lengths), wherein:
the second conductive contact (86x/96) includes a first portion (first portion of 86x/96 shown in annotated Fig 30C/31 of Terasawa ‘001, hereinafter FP) and a second portion (second portion of 86x/96 shown in annotated Fig 30C/31 of Terasawa ‘001, hereinafter SP), the second portion (SP) is between the first portion (FP) and the second control gate (146-1), the first portion (FP) including a first region having a first width (first portion having a first region with a first width shown in annotated Fig 30C/31 of Terasawa ‘001), the second portion (SP) including a second region having a second width (second portion having a second region with a second width shown in annotated Fig 30C/31 of Terasawa ‘001), and the second width being greater than the first width (annotated Fig 30C/31 of Terasawa ‘001 discloses second width greater than the first width); the second conductive contact (86X/96) including a conductive material (86B, Fig 29C, Para [0172]) in the first portion (FP) and the second portion (SP) and a dielectric liner (853, Fig 29C, Para [0174]) between the dielectric structure and the conductive material (86B) in the first portion (FP); and
the first portion (FP) of the second conductive contact (86X/96) includes a third region having third width (first portion having a third region with a third width shown in annotated Fig 30C/31 of Terasawa ‘001), the first region is between the second region and the third region (annotated Fig 30C/31 of Terasawa ‘001 discloses first region between the second region and the third region), and the first width is less than the third width (annotated Fig 30C/31 of Terasawa ‘001 discloses FP has larger upper contact 96 (third width) with a width larger than the first width),
But Terasawa ‘001 fails to explicitly disclose wherein the dielectric structure includes a first dielectric material conformal to the staircase structure and a second dielectric material is conformal to the first dielectric material at the staircase structure.
Nevertheless, in a related endeavor (Fig 1-12 of Ishiduki ‘633), Ishiduki ‘633 teaches wherein the dielectric structure (70, Fig 6C of Ishiduki ‘633, Para [0058]) includes a first dielectric material (71, Fig 6C of Ishiduki ‘633, Para [0058]) conformal to the staircase structure (20a, Fig 6C, Para [0058])(Fig 6C of Ishiduki ‘633 discloses 71 is conformal to the staircase structure) and a second dielectric material (72, Fig 6C of Ishiduki ‘633, Para [0058]) is conformal (Fig 6C of Ishiduki ‘633 discloses 72 is conformal to 71) to the first dielectric material (71) at the staircase structure (20a).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ishiduki ‘633’s teaching of a dielectric structure includes a first dielectric material conformal to the staircase structure and a second dielectric material is conformal to the first dielectric material at the staircase structure into Terasawa ‘001’s apparatus. Terasawa ‘001 teaches a memory structure with conductive contacts and dielectric structures over the connection region of the conductive contacts to the control gate. Ishiduki ‘633 also teaches a memory structure with conductive contacts and dielectric structures over the connection region of the conductive contacts to the control gate and further teaches having the dielectric structures conformal to the staircase structure. The ordinary artisan would have been motivated to modify Terasawa ‘001 in the manner set forth above, at least, because the dielectric structures would provide dielectric protection to the control gate to reduce or eliminate parasitic capacitance and Ishiduki ‘633 further teaches (Para [0058]) that the top dielectric layer can act as an etch stop layer when forming the contact to the control gate.
As incorporated, the dielectric structure (70) that includes a first dielectric layer (71) and a second dielectric layer (72) conformal to the staircase structure as taught by Ishiduki ‘633 would be used over the staircase structure (SS) of Terasawa ‘001.
As incorporated, described above, a first conductive contact (86Y of Terasawa ‘001) would then be formed in the dielectric structure (70 of Ishiduki ‘633).
But Terasawa ‘001 as modified by Ishiduki ‘633 fails to explicitly disclose the second conductive contact including a dielectric liner between the dielectric structure and the conductive material in the second portion;
Nevertheless, in a related endeavor (Fig 2A-2G of Jhothiraman ‘391), Jhothiraman ‘391 teaches the second conductive contact (136 as shown in annotated Fig 2G of Jhothiraman ‘391, Para [0087]) including a dielectric liner (136a, Fig 2G of Jhothiraman ‘391, Para [0087]) between the dielectric structure (124, Fig 2G of Jhothiraman ‘391, Para [0071]) and the conductive material (136b, Fig 2G of Jhothiraman ‘391, Para [0087]) in the second portion (second portion of 136 as shown in annotated Fig 2G of Jhothiraman ‘391);
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Jhothiraman ‘391’s teaching of the second conductive contact including a dielectric liner between the dielectric structure and the conductive material in the second portion into Terasawa ‘001 as modified by Ishiduki ‘633’s apparatus. Terasawa ‘001 as modified by Ishiduki ‘633 teaches a memory structure with multiple tiers of memory layers, conductive contacts and dielectric structures over the connection region of the conductive contacts to the control gate with dielectric structure on the staircase structure. Jhothiraman ‘391 also teaches a memory structure with multiple tiers of memory layers and conductive contacts within a dielectric layer. Jhothiraman ‘391 further teaches a dielectric layer lining the conductive contact structure through the entire length of the conductive contact structure. The ordinary artisan would have been motivated to modify Terasawa ‘001 as modified by Ishiduki ‘633 in the manner set forth above, at least, because the dielectric lining extending the entire length of the conductive contact between the conductive material of the conductive contact and the dielectric structures would provide an additional layer of dielectric protection to the conductive contact structure that can reduce potential parasitic capacitance between contacts.
As incorporated, the teaching of Jhothiraman ‘391 of the dielectric lining (136a) extending the entire length of the conductive contact between the conductive material of the conductive contact and the dielectric structures would be used in the second conductive contact (86x/96) of Terasawa ‘001 as modified by Ishiduki ‘633 so that the dielectric liner (853) of Terasawa ‘001 as modified by Ishiduki ‘633 would extend the length of the second conductive contact.
With respect to Claim 2 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 1, and Terasawa ‘001 further discloses wherein:
the second portion (SP) of the second conductive contact (86x/96) includes a fourth region having a fourth width (second portion having a fourth region with a fourth width shown in annotated Fig 30C/31 of Terasawa ‘001), wherein the third width is greater than the fourth width (enlarged detail shown in Fig 30C shows SP has tapered shape and annotated Fig 30C/31 of Terasawa ‘001 further shows third region (containing width of 96) is greater than fourth width).
With respect to Claim 3 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 1, and Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 further discloses wherein the dielectric structure includes: a third dielectric material (165/265, Fig 30C, Para [0125]) over the second dielectric material (72 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above)(165/265 is over staircase structure, so would be over dielectric structure 70 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above), wherein each of the first (86Y) and second conductive contacts (86x/96) go through the first (71 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above), second (72 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above), and third dielectric materials (165/265)(as incorporated, described above, first and second dielectric materials (71 and 72) would be under 165/265 and therefore the contacts 86x/96 and 86Y would go through them as they contact the control gates as described above).
With respect to Claim 4 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 3, and Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 further discloses wherein the first dielectric (71 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above) material includes silicon dioxide (Para [0058] of Ishiduki ‘633 discloses 71 as silicon oxide).
With respect to Claim 5 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 3, and Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 further discloses wherein the second dielectric material (72 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above) includes silicon nitride (Para [0058] of Ishiduki ‘633 discloses 71 as silicon nitride).
With respect to Claim 6 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391discloses all limitations of the apparatus of claim 3, and Terasawa ‘001 further discloses wherein the third dielectric material (165/265) includes silicon dioxide (Para [0098 and 0124] disclose 165/265 formed of silicate glass which one of ordinary skill in the art will recognize comprises silicon dioxide).
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With respect to Claim 7 Terasawa ‘001 discloses an apparatus comprising (Fig 1-31):
memory cells (memory cells shown in Fig 19B, region 58, Para [0145], hereinafter MC) located on tiers (tiers of layers 132/146 and 232/246 shown in Fig 31, Para [0178 and 0183], hereinafter tiers) of the apparatus (memory device show in Fig 31);
control gates (layers 146 and 246, Fig 31, Para [0161]) for the memory cells (MC), the control gates (layers of 146 and 246) including respective portions that form a staircase structure (annotated Fig 31 of Terasawa ‘001 shows portions of control gates, (146 and 246) form part of staircase structure, hereinafter SS), the control gates (146 and 246) including a first control gate (246-1 as shown in annotated Fig 31 of Terasawa ‘001, Para [0161]) located on a first tier (tier comprising layers 246 as shown in annotated Fig 31 of Terasawa ‘001, hereinafter Tier1) of the tiers (tiers), and a second control gate (146-1 as shown in annotated Fig 31 of Terasawa ‘001, Para [0161]) located on a second tier (tier comprising layers 146 as shown in annotated Fig 31 of Terasawa ‘001, hereinafter Tier2) of tiers (tiers), the first control gate (246-1) including a first portion (first portion of 246-1 disclosed in annotated Fig 31 of Terasawa ‘001), the second control gate (146-1) including a second portion (second portion of 146-1 disclosed in annotated Fig 31 of Terasawa ‘001), the first and second portions being part of the portions that forms the staircase structure (SS)( annotated Fig 31 of Terasawa ‘001 discloses first and second portion are part of the portions that forms the staircase structure);
a first dielectric material (44, Fig 29C, Para [0157]);
a second dielectric material (853, Fig 29C, Para [0171]);
a third dielectric material (165/265, Fig 30C, Para [0125]) over the second dielectric material (853)(Fig 29C and Fig 30 discloses 165/265 over 44 and 853);
a first conductive contact (86Y, Fig 30C, Para [0174]) going through and third dielectric materials (165/265)(Fig 30C discloses 86Y going through 265) and contacting (disclosed in Fig 30C and Para [0174]) the first portion of the first control gate (246-1)(annotated Fig 30C of Terasawa ‘001 discloses contact 86Y going through 265 and contacting first portion of the first control gate 246-1), the first conductive contact (86Y) having a first length (first length of 86Y shown in annotated Fig 30C of Terasawa ‘001, herein after FL) in a direction (vertical direction as shown in Fig 30C) from the first tier (Tier1) to the second tier (Tier2); and
a second conductive contact (86x/96, Fig 31, Para [0174]) going through the first (44), second (853), and third dielectric materials (165/265) and contacting (disclosed in Fig 30C and Para [0174]) the second portion of the second control gate (146-1) (annotated Fig 30C of Terasawa ‘001 discloses contact 86x/96 going through 44, 853 and 165/265 and contacting second portion of the second control gate 146-1), the second conductive contact (86x/96) having a second length (second length of 86x/96 shown in annotated Fig 30C of Terasawa ‘001, herein after SL) in the direction (vertical direction as shown in Fig 30C) from the first tier (Tier1) to the second tier (Tier2), the second length (SL) being unequal to the first length (FL)(Fig 30C discloses 86x/96 and 86Y having unequal lengths), wherein:
the second conductive contact (86x/96) includes a first conductive portion (first portion of 86x/96 shown in annotated Fig 30C of Terasawa ‘001, hereinafter FP) and a second conductive portion (second portion of 86x/96 shown in annotated Fig 30C of Terasawa ‘001, hereinafter SP), the second conductive portion (SP) is between the first conductive portion (FP) and the second portion of the second control gate (146-1)(annotated Fig 30C discloses SP is between FP and the second portion of 146-1), the first conductive portion (FP) including a first region (first portion of 86x/96 shown in annotated Fig 30C/31 of Terasawa ‘001, hereinafter FP) having a first width (first portion having a first region with a first width shown in annotated Fig 30C/31 of Terasawa ‘001), the second conductive portion (SP) including a second region having a second width (second portion having a second region with a second width shown in annotated Fig 30C/31 of Terasawa ‘001), wherein the second width is greater than the first width (annotated Fig 30C/31 of Terasawa ‘001 discloses second width greater than the first width); and
the second dielectric material (853) includes a portion adjacent the second conductive portion (SP) of the second conductive contact (86x/96)(annotated Fig 30C of Terasawa ‘001 discloses 853 includes a portion adjacent the second portion of second conductive contact 86x/96).
But Terasawa ‘001 fails to explicitly disclose the a dielectric material conformal to the staircase structure; a second dielectric material conformal to the first dielectric material at the staircase structure; and a first conductive contact going through the first, second, dielectric materials.
Nevertheless, in a related endeavor (Fig 1-12 of Ishiduki ‘633), Ishiduki ‘633 teaches a first dielectric material (71, Fig 6C of Ishiduki ‘633, Para [0058]) conformal to the staircase structure (20a, Fig 6C, Para [0058])(Fig 6C of Ishiduki ‘633 discloses 71 is conformal to the staircase structure); a second dielectric material (72, Fig 6C of Ishiduki ‘633, Para [0058]) is conformal (Fig 6C of Ishiduki ‘633 discloses 72 is conformal to 71) to the first dielectric material (71) at the staircase structure (20a) and a first conductive contact (80j, fig 2B of Ishiduki ‘633, Para [0059]) going through the first (71), second (72), dielectric materials (Fig 2B of Ishiduki ‘633 discloses 80j going through dielectric materials 71 and 72).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ishiduki ‘633’s teachings of a dielectric material conformal to the staircase structure; a second dielectric material conformal to the first dielectric material at the staircase structure; and a first conductive contact going through the first, second, dielectric materials into Terasawa ‘001’s apparatus. Terasawa ‘001 teaches a memory structure with conductive contacts and dielectric structures over the connection region of the conductive contacts to the control gate. Ishiduki ‘633 also teaches a memory structure with conductive contacts and dielectric structures over the connection region of the conductive contacts to the control gate and further teaches having the dielectric structures conformal to the staircase structure. The ordinary artisan would have been motivated to modify Terasawa ‘001 in the manner set forth above, at least, because the dielectric structures would provide dielectric protection to the control gate to reduce or eliminate parasitic capacitance and Ishiduki ‘633 further teaches (Para [0058]) that the top dielectric layer can act as an etch stop layer when forming the contact to the control gate.
As incorporated, the dielectric structure (70) that includes a first dielectric layer (71) and a second dielectric layer (72) conformal to the staircase structure as taught by Ishiduki ‘633 would be used over the staircase structure (SS) of Terasawa ‘001.
As incorporated, described above, a first conductive contact (86Y of Terasawa ‘001) would then be going through the first (71 of Ishiduki ‘633), second (72 of Ishiduki ‘633), dielectric materials.
But Terasawa ‘001 as modified by Ishiduki ‘633 fails to explicitly disclose the second conductive contact including a conductive material in the first portion and the second portion and a dielectric liner between the third dielectric material and the conductive material in the first portion and the second portion,
Nevertheless, in a related endeavor (Fig 2A-2G of Jhothiraman ‘391), Jhothiraman ‘391 teaches the second conductive contact (136 as shown in annotated Fig 2G of Jhothiraman ‘391, Para [0087]) including a conductive material (136b, Fig 2G of Jhothiraman ‘391, Para [0087]) in the first portion (first portion as shown in annotated Fig 2G of Jhothiraman ‘391, hereinafter FP1) and the second portion (second portion as shown in annotated Fig 2G of Jhothiraman ‘391, hereinafter SP2), and a dielectric liner (136a, Fig 2G of Jhothiraman ‘391, Para [0087]) between the third dielectric material (124, Fig 2G of Jhothiraman ‘391, Para [0071]) and the conductive material (136b, Fig 2G of Jhothiraman ‘391, Para [0087]) in the first portion (FP1) and the second portion (SP2);
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Jhothiraman ‘391’s teaching of the second conductive contact including a conductive material in the first portion and the second portion and a dielectric liner between the third dielectric material and the conductive material in the first portion and the second portion into Terasawa ‘001 as modified by Ishiduki ‘633’s apparatus. Terasawa ‘001 as modified by Ishiduki ‘633 teaches a memory structure with multiple tiers of memory layers, conductive contacts and dielectric structures over the connection region of the conductive contacts to the control gate with dielectric structure on the staircase structure. Jhothiraman ‘391 also teaches a memory structure with multiple tiers of memory layers and conductive contacts within a dielectric layer. Jhothiraman ‘391 further teaches a dielectric layer lining the conductive contact structure through the entire length of the conductive contact structure. The ordinary artisan would have been motivated to modify Terasawa ‘001 as modified by Ishiduki ‘633 in the manner set forth above, at least, because the dielectric lining extending the entire length of the conductive contact between the conductive material of the conductive contact and the dielectric structures would provide an additional layer of dielectric protection to the conductive contact structure that can reduce potential parasitic capacitance between contacts.
As incorporated, the teaching of Jhothiraman ‘391 of the dielectric lining (136a) extending the entire length of the conductive contact between the conductive material of the conductive contact and the dielectric structures would be used in the second conductive contact (86x/96) of Terasawa ‘001 as modified by Ishiduki ‘633 so that the dielectric liner (136a of Jhothiraman ‘391) would extend the length of the second conductive contact of Terasawa ‘001 as modified by Ishiduki ‘633.
With respect to Claim 8 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 7, and Terasawa ‘001 discloses further wherein:
the first conductive portion (FP) of the second conductive contact (86x/96) includes a third region having a third width (first portion having a third region with a third width shown in annotated Fig 30C/31 of Terasawa ‘001); and
the second conductive portion (SP) of the second conductive contact (86x/96) includes a fourth region having a fourth width (second portion having a fourth region with a fourth width shown in annotated Fig 30C/31 of Terasawa ‘001), wherein the third width is greater than the fourth width (enlarged detail shown in Fig 30C shows SP has tapered shape and annotated Fig 30C/31 of Terasawa ‘001 further shows third region (containing width of 96) is greater than fourth width).
With respect to Claim 9 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 7, and Terasawa ‘001 further discloses wherein each of the first (86Y) and second conductive contacts (86x/96) is formed in an opening (85, Fig 29B-29C, Para [0172]) in the third dielectric material (165/265)(Fig 30C shows 86x/96 and 86Y contact the third dielectric material 165/265).
With respect to Claim 10 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 7, and Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 further discloses wherein the second dielectric material (72 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above) includes silicon nitride (Para [0058] of Ishiduki ‘633 discloses 71 as silicon nitride).
With respect to Claim 11 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 10, and Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 further discloses wherein the first dielectric (71 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above) material includes silicon dioxide (Para [0058] of Ishiduki ‘633 discloses 71 as silicon oxide).
With respect to Claim 12 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 11, and Terasawa ‘001 further discloses wherein the third dielectric material (165/265) includes silicon dioxide (Para [0098 and 0124] disclose 165/265 formed of silicate glass which one of ordinary skill in the art will recognize comprises silicon dioxide).
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With respect to Claim 31 Terasawa ‘001 discloses an apparatus comprising (Fig 1-31):
memory cells (memory cells shown in Fig 19B, region 58, Para [0145], hereinafter MC) located on tiers (tiers of layers 132/146 and 232/246 shown in Fig 31, Para [0178 and 0183], hereinafter tiers) of the apparatus (memory device show in Fig 31);
control gates (layers 146 and 246, Fig 31, Para [0161]) for the memory cells (MC), the control gates (layers of 146 and 246) including a first control gate (246-1 as shown in annotated Fig 31 of Terasawa ‘001, Para [0161]) located on a first tier (tier comprising layers 246 as shown in annotated Fig 31 of Terasawa ‘001, hereinafter Tier1) of the tiers (tiers), and a second control gate (146-1 as shown in annotated Fig 31 of Terasawa ‘001, Para [0161]) located on a second tier (tier comprising layers 146 as shown in annotated Fig 31 of Terasawa ‘001, hereinafter Tier2) of the tiers (tiers), wherein respective portions (portions of 146-1 and 246-1) of the control gates (146-1 and 246-1) form part of a staircase structure (annotated Fig 31 of Terasawa ‘001 shows portions of control gates, 146-1 and 246-1 form part of staircase structure, hereinafter SS);
a dielectric structure (44, Fig 29C, Para [0157]) over the control gates (annotated Fig 31 of Terasawa ‘001 and Para [0162] discloses dielectric 44 over gates 146-1);
a first conductive contact (86Y, Fig 30C, Para [0174]) and coupled to (disclosed in Fig 30C and Para [0174]) the first control gate (246-1) at the staircase structure (SS), the first conductive contact (86Y) having a first length (first length of 86Y shown in annotated Fig 30C of Terasawa ‘001, herein after FL) in a direction (vertical direction as shown in Fig 30C) from the first tier (Tier1) to the second tier (Tier2); and
a second conductive contact (86x/96, Fig 30C, Para [0174]) formed in the dielectric structure (44) and coupled to (disclosed in Fig 30C and Para [0174]) the second control gate (146-1) at the staircase structure (SS), the second conductive contact (86x/96) having a second length (second length of 86x/96 shown in annotated Fig 30C of Terasawa ‘001, herein after SL) in the direction (vertical direction as shown in Fig 30C) from the first tier (Tier1) to the second tier (Tier2), the second length (SL) being greater than the first length (FL) (Fig 30C discloses 86x/96 and 86Y having unequal lengths), wherein:
the second conductive contact (86x/96) includes a first portion (first portion of 86x/96 shown in annotated Fig 30C/31 of Terasawa ‘001, hereinafter FP) and a second portion (second portion of 86x/96 shown in annotated Fig 30C/31 of Terasawa ‘001, hereinafter SP), the second portion (SP) is between the first portion (FP) and the second control gate (146-1), the first portion (FP) including a first region having a first width (first portion having a first region with a first width shown in annotated Fig 30C/31 of Terasawa ‘001), the second portion (SP) including a second region having a second width (second portion having a second region with a second width shown in annotated Fig 30C/31 of Terasawa ‘001), and the second width being greater than the first width (annotated Fig 30C/31 of Terasawa ‘001 discloses second width greater than the first width); the second conductive contact (86X/96) including a conductive material (86B, Fig 29C, Para [0172]) in the first portion (FP) and the second portion (SP) and a dielectric liner (853, Fig 29C, Para [0174]) between the dielectric structure and the conductive material (86B) in the first portion (FP); and
the first portion (FP) of the second conductive contact (86x/96) includes a third region having third width (first portion having a third region with a third width shown in annotated Fig 30C/31 of Terasawa ‘001), the first region is between the second region and the third region (annotated Fig 30C/31 of Terasawa ‘001 discloses first region between the second region and the third region), and the first width is less than the third width (annotated Fig 30C/31 of Terasawa ‘001 discloses FP has larger upper contact 96 (third width) with a width larger than the first width),
But Terasawa ‘001 fails to explicitly disclose wherein the dielectric structure includes a first dielectric material conformal to the staircase structure, and a second dielectric material is conformal to the first dielectric material at the staircase structure.
Nevertheless, in a related endeavor (Fig 1-12 of Ishiduki ‘633), Ishiduki ‘633 teaches wherein the dielectric structure (70, Fig 6C of Ishiduki ‘633, Para [0058]) includes a first dielectric material (71, Fig 6C of Ishiduki ‘633, Para [0058]) conformal to the staircase structure (20a, Fig 6C, Para [0058])(Fig 6C of Ishiduki ‘633 discloses 71 is conformal to the staircase structure) and a second dielectric material (72, Fig 6C of Ishiduki ‘633, Para [0058]) is conformal (Fig 6C of Ishiduki ‘633 discloses 72 is conformal to 71) to the first dielectric material (71) at the staircase structure (20a).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ishiduki ‘633’s teaching of a dielectric structure includes a first dielectric material conformal to the staircase structure and a second dielectric material is conformal to the first dielectric material at the staircase structure into Terasawa ‘001’s apparatus. Terasawa ‘001 teaches a memory structure with conductive contacts and dielectric structures over the connection region of the conductive contacts to the control gate. Ishiduki ‘633 also teaches a memory structure with conductive contacts and dielectric structures over the connection region of the conductive contacts to the control gate and further teaches having the dielectric structures conformal to the staircase structure. The ordinary artisan would have been motivated to modify Terasawa ‘001 in the manner set forth above, at least, because the dielectric structures would provide dielectric protection to the control gate to reduce or eliminate parasitic capacitance and Ishiduki ‘633 further teaches that the top dielectric layer can act as an etch stop layer when forming the contact to the control gate.
As incorporated, the dielectric structure (70) that includes a first dielectric layer (71) and a second dielectric layer (72) conformal to the staircase structure as taught by Ishiduki ‘633 would be used over the staircase structure (SS) of Terasawa ‘001.
As incorporated, described above, a first conductive contact (86Y of Terasawa ‘001) would then be formed in the dielectric structure (70 of Ishiduki ‘633).
But Terasawa ‘001 as modified by Ishiduki ‘633 fails to explicitly disclose the second conductive contact including a dielectric liner between the dielectric structure and the conductive material in the second portion;
Nevertheless, in a related endeavor (Fig 2A-2G of Jhothiraman ‘391), Jhothiraman ‘391 teaches the second conductive contact (136 as shown in annotated Fig 2G of Jhothiraman ‘391, Para [0087]) including a dielectric liner (136a, Fig 2G of Jhothiraman ‘391, Para [0087]) between the dielectric structure (124, Fig 2G of Jhothiraman ‘391, Para [0071]) and the conductive material (136b, Fig 2G of Jhothiraman ‘391, Para [0087]) in the second portion (second portion of 136 as shown in annotated Fig 2G of Jhothiraman ‘391);
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Jhothiraman ‘391’s teaching of the second conductive contact including a dielectric liner between the dielectric structure and the conductive material in the second portion into Terasawa ‘001 as modified by Ishiduki ‘633’s apparatus. Terasawa ‘001 as modified by Ishiduki ‘633 teaches a memory structure with multiple tiers of memory layers, conductive contacts and dielectric structures over the connection region of the conductive contacts to the control gate with dielectric structure on the staircase structure. Jhothiraman ‘391 also teaches a memory structure with multiple tiers of memory layers and conductive contacts within a dielectric layer. Jhothiraman ‘391 further teaches a dielectric layer lining the conductive contact structure through the entire length of the conductive contact structure. The ordinary artisan would have been motivated to modify Terasawa ‘001 as modified by Ishiduki ‘633 in the manner set forth above, at least, because the dielectric lining extending the entire length of the conductive contact between the conductive material of the conductive contact and the dielectric structures would provide an additional layer of dielectric protection to the conductive contact structure that can reduce potential parasitic capacitance between contacts.
As incorporated, the teaching of Jhothiraman ‘391 of the dielectric lining (136a) extending the entire length of the conductive contact between the conductive material of the conductive contact and the dielectric structures would be used in the second conductive contact (86x/96) of Terasawa ‘001 as modified by Ishiduki ‘633 so that the dielectric liner (853) of Terasawa ‘001 as modified by Ishiduki ‘633 would extend the length of the second conductive contact.
With respect to Claim 32 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 31, and Terasawa ‘001 further discloses wherein:
the second portion (SP) of the second conductive contact (86x/96) includes a fourth region having a fourth width (second portion having a fourth region with a fourth width shown in annotated Fig 30C/31 of Terasawa ‘001), wherein the third width is greater than the fourth width (enlarged detail shown in Fig 30C shows SP has tapered shape and annotated Fig 30C/31 of Terasawa ‘001 further shows third region (containing width of 96) is greater than fourth width).
With respect to Claim 33 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 31, and Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 further discloses wherein the dielectric structure includes a third dielectric material (165/265, Fig 30C, Para [0125]) over the second dielectric material (72 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above)(165/265 is over staircase structure, so would be over dielectric structure 70 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above), wherein each of the first (86Y) and second conductive contacts (86x/96) go through the first (71 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above), second (72 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above), and third dielectric materials (165/265)(as incorporated, described above, first and second dielectric materials (71 and 72) would be under 165/265 and therefore the contacts 86x/96 and 86Y would go through them as they contact the control gates as described above).
With respect to Claim 34 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 33, and Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 further discloses wherein one of the first dielectric material (71 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above) and the second dielectric material (72 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above) includes silicon nitride (Para [0058] of Ishiduki ‘633 discloses 71 as silicon nitride).
With respect to Claim 35 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 33, and Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses further wherein the first dielectric material (71 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above) and the third dielectric material (165/265) include a same dielectric material (Para [0058] of Ishiduki ‘633 discloses 71 as a silicon oxide and Para [0098 and 0124] disclose 165/265 formed of silicate glass which one of ordinary skill in the art will recognize comprises silicon dioxide).
With respect to Claim 36 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 33, and Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 further discloses wherein the first dielectric (71 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above) material includes silicon dioxide (Para [0058] of Ishiduki ‘633 discloses 71 as silicon oxide).
With respect to Claim 37 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 36, and Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 further discloses wherein the second dielectric material (72 of Ishiduki ‘633 as incorporated in Terasawa ‘001 as described above) includes silicon nitride (Para [0058] of Ishiduki ‘633 discloses 71 as silicon nitride).
With respect to Claim 38 Terasawa ‘001 as modified by Ishiduki ‘633 and further modified by Jhothiraman ‘391 discloses all limitations of the apparatus of claim 37, and Terasawa ‘001 further discloses wherein the third dielectric material (165/265) includes silicon dioxide (Para [0098 and 0124] disclose 165/265 formed of silicate glass which one of ordinary skill in the art will recognize comprises silicon dioxide).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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