DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-17 in the reply filed on 11/12/25 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 recites the limitation "the IC chip signal route" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3, 4, 7, 8, and 9 is/are rejected under 35 U.S.C. 102(1)(a) as being anticipated by Karhabe et al. (US pub 20200273775).
With respect to claim 1, Karhabe et al. teach an integrated circuit (IC) device package, comprising (see figs. 1-9, particularly fig. 2D and associated text):
a package substrate (bottom part of 220) including a signal route 227 that extends a lateral length within a top metallization level (upper part); and
a routing structure (upper part of 220) to couple the package substrate with an IC chip 250, wherein the routing structure comprises:
a first metallization feature (one of 218/219) to couple the signal route with a first IC chip interconnect; and
a second metallization feature (the other of 218/219) coupled to a ground plane of the package substrate, wherein the second metallization feature is over at least a portion of the lateral length of the signal route.
With respect to claim 2, Karhabe et al. teach the second metallization feature is within a level of the routing structure most proximal to the package substrate. See fig. 2D and associated text.
With respect to claim 3, Karhabe et al. teach the package substrate comprises a third metallization feature (the bottom part of 227) coupled to the ground plane, the third metallization feature under at least a portion of the lateral length of the signal route (upper part of 227). See fig. 2D and associated text.
With respect to claim 4, Karhabe et al. teach the routing structure comprises an array of IC chip interconnect interfaces 231 in a level of the routing structure most distal from the package substrate; and the lateral length (227) extends beyond an edge of the array. See fig. 2D and associated text.
With respect to claim 7, Karhabe et al. teach an IC chip 250 interconnected to metallization features in a level of the routing structure most distal from the package substrate, wherein a first interconnect (one of 248) interface of the IC chip is coupled to the signal route and a second interconnect (the other of 248) interface of the IC chip is coupled to the ground plane. See fig. 2D and associated text.
With respect to claim 8, Karhabe et al. teach a package dielectric underfill 240 between the routing structure and the package substrate, wherein a portion of the package dielectric underfill is between the signal route and the second metallization feature. See fig. 2D and associated text.
With respect to claim 9, Karhabe et al. teach the lateral length (of signal route 227) extends beyond an edge of the IC chip. See fig. 2D and associated text.
Claim(s) 11-17 is/are rejected under 35 U.S.C. 102(1)(a) as being anticipated by Karhabe et al. (US pub 20200273775).
With respect to claim 11, Karhabe et al. teach a system, comprising (see figs. 1-9, particularly fig. 2D and associated text):
a package substrate (bottom part of 220) comprising:
a signal route 227 that extends a lateral length within a top metallization level; and
a plurality of interconnect interfaces (bottom part of 227) within a bottom metallization level;
an integrated circuit (IC) chip 250; and
a routing structure (upper part of 220) between the package substrate and the IC chip, wherein the routing structure comprises:
a first metallization feature (one of 218/219) coupled to the signal route; and
a second metallization feature (the other of 218/219) coupled to a ground plane of the package substrate, wherein the second feature is over at least a portion of the lateral length of the signal route.
With respect to claim 12, Karhabe et al. teach a host component coupled to the plurality of interconnect interfaces by a plurality of solder features (see para 0042); and a power supply coupled to the IC chip through one or more of the interconnect interfaces (see para 0043).
With respect to claim 13, Karhabe et al. teach a terminal of the power supply is coupled to the ground plane of the package substrate (see para 0043).
With respect to claim 14, Karhabe et al. teach the IC chip comprises memory circuitry, and wherein the system further comprises a second IC chip adjacent to the first IC chip, the second IC chip also coupled to the routing structure (see para 0026, 0029, and 0043).
With respect to claim 15, Karhabe et al. teach the package substrate comprises a core (middle), a plurality of front-side metallization levels (upper part of 227) over a first side of the core, and a plurality of back-side metallization levels (bottom part of 227) over a second side of the core; the top metallization level is one of the front-side metallization levels; and the bottom metallization level is one of the back-side metallization levels. See fig. 2D and associated text.
With respect to claim 16, Karhabe et al. teach the top metallization level is coupled to the routing structure through a plurality of solder interconnects 231,232. See fig. 2D and associated text.
With respect to claim 17, Karhabe et al. teach a package dielectric 240 between the solder interconnects and between the signal route and the second metallization feature. See fig. 2D and associated text.
Allowable Subject Matter
Claim 6 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 5 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner’s Cited References
The cited references generally show the similar or related structure having a routing structure having first and second metal elements between a chip and a substrate having metallization levels and first and second metal elements connected to signal and ground of metallization levels and chip as presently claimed by applicant.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897